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2022-06-28Convert CONFIG_HAS_FSL_DR_USB to KconfigTom Rini
This converts the following to Kconfig: CONFIG_HAS_FSL_DR_USB Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28Convert CONFIG_EHCI_HCD_INIT_AFTER_RESET to KconfigTom Rini
This converts the following to Kconfig: CONFIG_EHCI_HCD_INIT_AFTER_RESET Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28Convert CONFIG_EHCI_DESC_BIG_ENDIAN et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_EHCI_DESC_BIG_ENDIAN CONFIG_EHCI_MMIO_BIG_ENDIAN Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28ehci-mxs: Remove non-DM codeTom Rini
This code is not enabled anywhere, drop it. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28Convert CONFIG_EFLASH_PROTSECTORS to KconfigTom Rini
This converts the following to Kconfig: CONFIG_EFLASH_PROTSECTORS Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28Convert CONFIG_E1000_NO_NVM to KconfigTom Rini
This converts the following to Kconfig: CONFIG_E1000_NO_NVM Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28Merge branch '2022-06-28-mpc85xx-and-aspeed-fixes' into nextTom Rini
- Merge a PowerPC MPC85xx cleanup / fix, and aspeed linker fix
2022-06-28aspeed/ast2600: Fix SPL linker scriptJoel Stanley
The commit 99e2fbcb69f0 ("linker_lists: Rename sections to remove . prefix") changed the name of the linker list sections. As the Aspeed SPL linker wasn't in the tree yet, it missed the change. This updates the SPL linker to match arch/arm/cpu/u-boot-spl.lds which Aspeed was copied from. Fixes: 442a69c14375 ("configs: ast2600: Move SPL bss section to DRAM space") Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-28powerpc: mpc85xx: Set TEXT_BASE addresses to real base valuesPali Rohár
Currently CONFIG_SPL_TEXT_BASE and CONFIG_SYS_TEXT_BASE addresses are manually increased by 0x1000 due to .bootpg section. This section has size of 0x1000 bytes and is manually put by linker script before .text section (and therefore before base address) when CONFIG_SYS_MPC85XX_NO_RESETVEC is set. Due to this fact lot of other config options are manually increased by 0x1000 value to make correct layout. Note that entry point is not on CONFIG_SPL_TEXT_BASE (image+0x1000) but it is really on address CONFIG_SPL_TEXT_BASE-0x1000 (means at the start of the image). Cleanup handling of .bootpg section when CONFIG_SYS_MPC85XX_NO_RESETVEC is set. Put .bootpg code directly into .text section and move text base address to the start of .bootpg code. And finally remove +0x1000 value from lot of config options. With this removal custom PHDRS is not used anymore, so remove it too. After this change entry point would be at CONFIG_SPL_TEXT_BASE and not at address -0x1000 anymore. Tested on P2020 board with SPL and proper U-Boot. Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-27Merge branch '2022-06-27-add-armv8-sha1-sha256-support' into nextTom Rini
To quote the author: This series adds support for the SHA-1 and SHA-256 Secure Hash Algorithm for CPUs that have support of the ARM v8 Crypto Extensions. It Improves speed of integrity & signature checking procedures.
2022-06-27qemu_arm64: Enable CONFIG_ARMV8_CRYPTO supportTom Rini
Now that we can make use of CPU features for sha1/sha256, enable in QEMU so that we get some test coverage. Cc: Loic Poulain <loic.poulain@linaro.org> Cc: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-27armv8 SHA-256 using ARMv8 Crypto ExtensionsLoic Poulain
This patch adds support for the SHA-256 Secure Hash Algorithm for CPUs that have support for the SHA-256 part of the ARM v8 Crypto Extensions. It greatly improves sha-256 based operations, about 17x faster on iMX8M evk board. ~12ms vs ~208ms for a 20MiB kernel sha-256 verification. asm implementation is a simplified version of the Linux version (from Ard Biesheuvel). Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2022-06-27lib: sha256: Add support for hardware specific sha256_processLoic Poulain
Mark sha256_process as weak to allow hardware specific implementation. Add parameter for supporting multiple blocks processing. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2022-06-27armv8 SHA-1 using ARMv8 Crypto Extensions:Loic Poulain
This patch adds support for the SHA-1 Secure Hash Algorithm for CPUs that have support for the SHA-1 part of the ARM v8 Crypto Extensions. It greatly improves sha-1 based operations, about 10x faster on iMX8M evk board. ~12ms vs ~165ms for a 20MiB kernel sha-1 verification. asm implementation is a simplified version of the Linux version (from Ard Biesheuvel). Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2022-06-27sha1: Fix digest state size/typeLoic Poulain
sha1 digest size is 5*32-bit => 160-bit. Using 64-bit unsigned long does not cause issue with the current sha1 implementation, but could be problematic for vectorized access. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2022-06-27lib: sha1: Add support for hardware specific sha1_processLoic Poulain
Mark sha1_process as weak to allow hardware specific implementation. Add parameter to support for multiple blocks processing. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2022-06-27Merge tag 'xilinx-for-v2022.10' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.10 cpu: - Add driver for microblaze cpu net: - Add support for DM_ETH_PHY to AXI emac and emaclite xilinx: - Switch platforms to DM_ETH_PHY - DT chagnes in ZynqMP and Zynq - Enable support for SquashFS zynqmp: - Add support for KR260 boards - Move BSS from address 0 - Move platform identification from board code to soc driver - Improve zynqmp_psu_init_minimize versal: - Enable loading app at EL1 serial: - Setup default address and clock rates for DEBUG uarts pinctrl: - Add support for tri state and output enable properties relocate-rela: - Clean relocate-rela implementation for ARM64 - Add support for Microblaze microblaze: - Add support for runtime relocation - Rework cache handling (wiring, Kconfig) based on cpuinfo - Remove interrupt support timer: - Extract axi timer driver from Microblaze to generic location
2022-06-27timer: Add SPL_REGMAP dependency for Xilinx timerMichal Simek
Add SPL_REGMAP dependency when SPL is enabled. This can avoid compilation issues if timer is selected but SPL_REGMAP not. Reported-by: Ovidiu Panait <ovidiu.panait@windriver.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/8f6c187e04cb3127bf5148ae2dbbdf55b25ea544.1655982509.git.michal.simek@amd.com
2022-06-27xilinx: Enable support for SquashFSMichal Simek
Enable SquashFS for all xilinx platforms. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/dbe85afda8cd90ebfc537979d382808ff9bec160.1655982259.git.michal.simek@amd.com
2022-06-24arm64: zynqmp: Move helper functions below header includesStefan Herbrechtsmeier
Move helper functions in psu_init files below header includes to avoid forward declarations. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-15-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24tools: zynqmp_psu_init_minimize: Move helper functions below header includesStefan Herbrechtsmeier
Move helper functions below header includes to avoid forward declarations. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-14-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24tools: zynqmp_psu_init_minimize: Use CR instead of LFStefan Herbrechtsmeier
Use carriage return instead of line feed to support mangling across lines. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-13-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24tools: zynqmp_psu_init_minimize: Remove low level uart settingsStefan Herbrechtsmeier
There is no reason to do serial initialization. Uart driver does it already based on DT. Good effect is that it is clear which interface is console. The resulting change was done in past by commit 84d2bbf082fa ("arm64: zynqmp: Remove low level UART setting"). Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-12-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24xilinx: zynqmp: make spi flash support optionalStefan Herbrechtsmeier
The set_dfu_alt_info function use the CONFIG_SYS_SPI_U_BOOT_OFFS define to set the dfu_alt_info environment variable for qspi boot mode. Guard the usage of CONFIG_SYS_SPI_U_BOOT_OFFS to make spi flash support optional. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-11-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24xilinx: common: Separate display cpu info functionStefan Herbrechtsmeier
Move the print_cpuinfo function of CONFIG_DISPLAY_CPUINFO into its own source file to support reuse by other board vendors. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-10-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24xilinx: cpuinfo: Print soc machineStefan Herbrechtsmeier
Print the soc machine in the print_cpuinfo function. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-9-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24soc: xilinx: zynqmp: Add machine identification supportStefan Herbrechtsmeier
Add machine identification support based on the zynqmp_get_silicon_idcode_name function and use the soc_get_machine function of the soc uclass to get silicon idcode name for the fpga init. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-8-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24soc: xilinx: zynqmp: Remove redundant checks for zynqmp_mmio_readStefan Herbrechtsmeier
Remove the redundant SPL and CurrentEL checks for the zynqmp_mmio_read function call because the function itself runs the same checks. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-7-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24xilinx: zynqmp: Merge device listsStefan Herbrechtsmeier
Merge the svd / xck devices into to the common zynqmp device list. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-6-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24xilinx: zynqmp: Reuse shift macros to define masksStefan Herbrechtsmeier
Reuse the shift macros to define the masks. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-5-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24xilinx: zynqmp: Add macro for device type maskStefan Herbrechtsmeier
Add a macro for the device type mask of the id code. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-4-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24xilinx: zynqmp: Replace strncat with strlcatStefan Herbrechtsmeier
Replace strncat with strlcat to always produce a valid null-terminated string. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-3-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24firmware: zynqmp: Probe driver before useStefan Herbrechtsmeier
Probe the driver before use to ensure that the driver is always available and the global data are valid. Initialize the global data with zero and probe the driver if the global data are still zero. This allows a usage of the firmware functions from other drivers with arbitrary order between the drivers. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-2-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24firmware: zynqmp: Check if rx channel dev pointer is validStefan Herbrechtsmeier
Check if rx channel dev pointer is valid and not if the address of the pointer is valid. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24ARM: zynq: Fix size-cells for pl353 driverAmit Kumar Mahapatra
"size-cells" of the nand controller node should be 0 as the "reg" property of the nand device node contains the chip select number and not address information. The patch fixes the below compilation warning arch/arm/dts/zynq-zc770-xm011.dtb: Warning (reg_format): /axi/memory-controller@e000e000/nand-controller@0,0/nand@0:reg: property has invalid length (4 bytes) (#address-cells == 1, #size-cells == 1) Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/6e90665a2dad7fe8ade10b8f57101f8144963791.1655288559.git.michal.simek@amd.com
2022-06-24arm64: zynqmp: Fix usb node drive strength and slew rateAshok Reddy Soma
As per design, all input/rx pins should have fast slew rate and 12mA drive strength. Rest all pins should be slow slew rate and 4mA drive strength. Fix usb nodes as per this and remove setting of slow slew rate for all the usb gorup pins. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/b245c165f05845c1f3ab41a92c82b7ec1538cee4.1655288171.git.michal.simek@amd.com
2022-06-24microblaze: Remove interrupt handlerMichal Simek
The primary purpose for this code was timer. By converting it to CONFIG_TIMER there is no code which uses this implementation that's why remove it. If there is a need to handle interrupts this patch can be reverted in future. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/5f2decc5a30a5678490ebde26d8c6f5a5f873cda.1654684731.git.michal.simek@amd.com
2022-06-24microblaze: Convert axi timer to DM driverMichal Simek
Move axi timer driver from Microblaze to generic location. Origin implementation was irq based with counting down timer. CONFIG_TIMER drivers are designed differently that timer is free running up timer with automatic reload without any interrupt. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Michal Simek <michal.simek@amd.com> Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com
2022-06-24cpu: add CPU driver for microblazeOvidiu Panait
Add a basic CPU driver that retrieves information about the microblaze CPU core. cpu_ops handlers are implemented so that the "cpu" command can work properly: U-Boot-mONStR> cpu list 0: cpu@0 MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000 U-Boot-mONStR> cpu detail 0: cpu@0 MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000 ID = 0, freq = 50 MHz: L1 cache, MMU Note: cpu_ver_lookup[] and family_string_lookup[] arrays were imported from linux. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-14-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: add support for handling PVR dataOvidiu Panait
Add helper code for PVR (Processor Version Register) data handling. It will be used by the UCLASS_CPU driver to populate cpuinfo fields at runtime. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-13-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: Kconfig: introduce XILINX_MICROBLAZE0_FPGA_FAMILY optionOvidiu Panait
Provide a static Kconfig value for the target FPGA archtitecture, as it is done in Linux. The cpu-uclass driver will cross-check it with the value read from PVR10 register. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-12-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: cache: introduce flush_dcache_range()Ovidiu Panait
Align microblaze with the other architectures and provide an implementation for flush_dcache_range(). Also, remove the microblaze exception in drivers/core/device.c. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-11-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: cache: introduce cpuinfo structureOvidiu Panait
Introduce a minimal cpuinfo structure to hold cache related info. The instruction/data cache size and cache line size are initialized early in the boot to default Kconfig values. They will be overwritten with data from PVR/dtb if the microblaze UCLASS_CPU driver is enabled. The cpuinfo struct was placed in global_data to allow the microblaze UCLASS_CPU driver to also run before relocation (initialized global data should be read-only before relocation). gd_cpuinfo() helper macro was added to avoid volatile "-Wdiscarded-qualifiers" warnings when using the pointer directly. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-10-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com> (s/bralid/brlid/)
2022-06-24microblaze: cache: introduce flush_cache_all()Ovidiu Panait
All flush_cache() calls in microblaze code are supposed to flush the entire instruction and data caches, so introduce flush_cache_all() helper to handle this. Also, provide implementations for flush_dcache_all() and invalidate_icache_all() so that icache and dcache u-boot commands can work. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-9-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: cache: introduce Kconfig options for icache/dcache sizesOvidiu Panait
Replace XILINX_DCACHE_BYTE_SIZE macro with two Kconfig symbols for instruction and data caches sizes, respectively: CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE Also, get rid of the hardcoded value in icache_disable(). Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-8-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com> (s/bralid/brlid/g)
2022-06-24microblaze: cache: split flush_cache() functionOvidiu Panait
Factor out icache/dcache components from flush_cache() function. Call the newly added __flush_icache()/__flush_dcache() functions inside icache_disable() and dcache_disable(), respectively. There is no need to flush both caches when disabling a particular cache type. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-7-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: cache: improve icache Kconfig optionsOvidiu Panait
Replace CONFIG_ICACHE with a Kconfig option more limited in scope - XILINX_MICROBLAZE0_USE_WIC. It should be enabled if the processor supports the "wic" (Write to Instruction Cache) instruction. It will be used to guard "wic" invocations in microblaze cache code. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-6-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: cache: improve dcache Kconfig optionsOvidiu Panait
Replace CONFIG_DCACHE with a Kconfig option more limited in scope - XILINX_MICROBLAZE0_USE_WDC. It should be enabled if the processor supports the "wdc" (Write to Data Cache) instruction. It will be used to guard "wdc" invocations in microblaze cache code. Also, drop all ifdefs around flush_cache() calls and only keep one CONFIG_IS_ENABLED() guard within flush_cache() itself. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-5-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: cache: replace XILINX_USE_DCACHE -> CONFIG_DCACHEOvidiu Panait
XILINX_USE_DCACHE macro was removed in 7556fa09e0e ("microblaze: Simplify cache handling"), but it was still used in a couple of places. Replace those occurences with CONFIG_DCACHE. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-4-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: start.S: remove unused codeOvidiu Panait
in16/out16 routines seem to not be used anywhere in microblaze code, so remove them. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-3-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
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