| Age | Commit message (Collapse) | Author |
|---|
|
This is a preparation patch for adding A33 support, which will have a
mach name of sun8i-a33.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
|
|
sun6i and newer (derived) SoCs such as the sun8i-a23, sun8i-a33 and sun9i
have a various things in common, like having separate ahb reset control
registers, the SID living inside the pmic, custom pmic busses, new style
watchdog, etc.
This commit introduces a new hidden SUNXI_GEN_SUN6I Kconfig bool which can be
used to check for these features avoiding the need for an ever growing list
of "#if defined CONFIG_MACH_SUN?I" conditionals as we add support for more
"new style" sunxi SoCs.
Note that this commit changes the behavior of the gmac and hdmi code for
sun8i and the upcoming sun9i devices. This does not matter as sun8i does
not have gmac nor hdmi, and sun9i has new hardware-blocks for these so
the old code will not work there.
Also this is intentional as if a sun8i / sun9i variant which does use the
old hwblocks shows up then the GEN_SUN6I code paths will be the right ones
to use.
For completeness this also adds a SUNXI_GEN_SUN4I bool for A10/A13/A20.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
|
|
We do not use irqs in u-boot so remove the unused irq field, and all the
#ifdef-ery around the irq initialization.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
|
|
There is no reason not to and this make the #ifdef-ery easier to read.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
|
|
This is already invoked a few cycles later in monitor mode by
_secure_monitor (_sunxi_cpu_entry calls _do_nonsec_entry which triggers
_secure_monitor via smc #0). Drop it here, it serves no purpose.
CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
|
|
|
|
|
|
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
Move arch/arm/include/asm/arch-zynq/*
-> arch/arm/mach-zynq/include/mach/*
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
Move arch/arm/cpu/armv7/zynq/* -> arch/arm/mach-zynq/*
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
The comment line in arch/arm/cpu/armv7/zynq/config.mk says that
the option "-mfpu=neon" is necessary for compiling lowlevel_init.S.
We do not have to give it to all the source files.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
Enable SDHCI0 for zynqmp.
Add empty gpio.h because of sdhci requirement.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
Provide an option to write filesystem independend commands.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
Added the SPI driver support for ZynqMP
The controller is same as zynq SPI controller
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
|
|
Enable the i2c driver for ZynqMP
Also enable the eeprom for read and writes
to eeprom on ZynqMP
ZynqMP uses the same i2c controller as in Zynq
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
Add support for EMMC bootmode.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
Add support for Veloce - zynqmp emulation platform.
Platform doesn't support SDHCI.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
Fix wrong timer calculation in get_timer_masked incase of
overflow.
This fixes the issue of getting wrong time from get_timer()
calls.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
Remove the quirk SDHCI_QUIRK_NO_CD as it is not
required.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
Add support for loading sw for R5 with enabling for zynqmp.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
|
|
Define the mmu table till 2MB granularity
enable dcaches for zynqmp.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
Disable all level shifters before enabling
the PS-to-PL level shifters as it would
be good to disable all level shifters before
enabling the PS-to-PL in order to ensure that
it is in proper state
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
We are about to change the location for ps7_init files, breaking the
current work-flows. It is good time to drop the legacy ps7_init.c/h
support.
Going forward, please use ps7_init_gpl.c/h all the time.
If you are still using old Xilinx tools that are only able to
generate ps7_init.c/h, rename them into ps7_init_gpl.c/h.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
The PicoZed is a System-on-Module board which is marketed as part of
the ZedBoard/MicroZed/etc. collection. It includes a Zynq-7000
processor.
This patch adds support that covers all the variants of the PicoZed
including the SKUs with Z7010/Z7020 and Z7015/Z7030 Zynq chips. This
patch set however only covers support for the System-on-Module and does
not cover any extra components that are available on carrier boards
(except those that are fanned out of the module itself).
More information on this board, its variants and available carrier
boards is available at: http://zedboard.org/product/picozed
Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
On slow platforms not all baudrate setting is valid.
Check it directly in the driver and setup maximum possible
frequency.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
Enable GPIO driver and GPIO commands.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
Most of the code is taken (and adapted) from Linux kernel driver.
Just add CONFIG_ZYNQ_GPIO to you config to enable it
Signed-off-by: Andrea Scian <andrea.scian@dave.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
It is possible for CONFIG_XILINX_EMACLITE to be defined without
XILINX_EMACLITE_BASEADDR being defined as the EMAC Lite driver support
OF init. Check that the driver is enabled and the base address is
available before initializing with a static base address.
Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
|
|
|
|
These functions now rely on uclass_find_first/next_device() and assume that
they will either return failure (-ve error code) or a device. In fact,
coming to the end of a list is not considered failure and they return 0
in that case.
The logic to deal with this was replaced in commit acb9ca2a with just using
uclass_get_device_tail(). Add back the missing logic. This bug was
caught by unit tests but since they were broken for other reasons at the
time, this was not noticed.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
This was accidentally added by commit dd0b0122bacc
"serial: ns16550: Add an option to specify the debug UART register shift".
Remove it.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Simon Glass <sjg@chromium.org>
|
|
Trivial bug fix for commit 5a87c4174d18 (dm: core: Drop device
removal error path when not supported).
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
|
|
|
|
|
|
Upto now flash sector_size is assigned from params which isn't
necessarily a sector size from vendor, so based on the SECT_*
flags from flash_params the erase_size will compute and it will
become the sector_size finally.
Bug report (from Bin Meng):
=> sf probe
SF: Detected SST25VF016B with page size 256 Bytes, erase size 4 KiB,
total 2 MiB, mapped at ffe00000
=> sf erase 0 +100
SF: 65536 bytes @ 0x0 Erased: OK
Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Reported-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
|
With SPI flash moving to driver model, commit fbb0991 "dm: Convert
spi_flash_probe() and 'sf probe' to use driver model" ignored the
SST flash-specific write op (byte program & word program), which
actually broke the SST flash from wroking.
This commit makes SST flash work again under driver model, by adding
SST flash-specific handling in the spi_flash_std_write().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
|
|
Add a new member 'flags' in struct spi_flash to store the flash flags
during spi_flash_validate_params().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
|
|
The timeout value is never reset during the transfer. This means that when
transferring more data we eventually trigger the timeout.
This was reported on the mailing list:
"Spansion SPI flash read timeout with AM335x"
Signed-off-by: David Dueck <davidcdueck@googlemail.com>
CC: Tom Rini <trini@konsulko.com>
CC: Stefan Roese <sr@denx.de>
CC: Andy Pont <andy.pont@sdcsystems.com>
Tested-by: David Dueck <davidcdueck@googlemail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
|
|
Instead of hardcoding the 'fdtfile' variable, let's detect the SoC and
board variant on the fly and change the dtb name.
Based on the scheme done on am335x board.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-By: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
|
README file suggests to use 'fdtfile' for the dtb file name and
'fdt_addr_r' for the dtb address in RAM, so do as suggested.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
|
Introduce is_hummingboard() function that reads GPIOs that can distinguish
between Cubox-i and Hummingboard.
Print the board name accordingly.
Based on a patch from Rabeeh Khoury.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
|
Cubox-i and Hummingboard support several MX6 SoCs: mx6solo, mx6dual-lite,
mx6dual and mx6quad. Add support for the different SoC/memory sizes
combinations.
DDR initialization values were extracted from Solid-run internal U-boot.
Tested on a CuBox-i4Pro, HummingBoard-i2eX and HummingBoard-i1.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
|
Cubox-i and Hummingboard support several MX6 SoCs: mx6solo, mx6dual-lite,
mx6dual and mx6quad.
Use IOMUX_PADS() macro in order to prepare for the multi-SoC support.
Also pass 'MX6QDL' in the defconfig to indicate it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
|
The correct name of the defconfig file is 'mx6cuboxi_defconfig'.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
|
Arria V SocDK has same QSPI and SPI flash configuration as Socrates. Add
support for it.
Signed-off-by: Pavel Machek <pavel@denx.de>
|
|
|
|
|
|
|
|
Add device-tree handover to Linux kernel conforming with MIPS UHI [1].
Register $a0 will be set to the reserved value -2. The address of
the device-tree blob will be stored as KSEG0 address in $a1. $a2 and
$a3 are set to zero.
[1] http://prplfoundation.org/wiki/MIPS_documentation
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
|
