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The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper
logic to integrate these blocks in the device. The DDR subsystem is
used to provide an interface to external SDRAM devices which can be
utilized for storing program or data. Introduce support for the
DDR controller and DDR phy within the DDR subsystem.
Signed-off-by: Kevin Scholz <k-scholz@ti.com
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Add DT binding documentation for DDR sub system present on J721E device.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Added the following registers to the DDR configuration:
- ACIOCR0,
- ACIOCR3,
- V2H_CTL_REG,
- DX8SLxDQSCTL.
Modified enable_dqs_pd and disable_dqs_pd to only touch the associated
bit fields for pullup and pulldown registers (to preserve slew rate and
other bits in that same register). Also update the dts files in the same
patch to maintain git bisectability.
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Added training support for LPDDR4 and DDR3L DDRs. Also added/changed
some register configuration to support all 3 DDR types
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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The current configuration of DDR on AM654 base board is for 1600MTs but
the file name is specified as k3-am654-base-board-ddr4-1600MHz.dtsi.
Since 1600MHz is misleading, rename it to
k3-am654-base-board-ddr4-1600MTs.dtsi
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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U-Boot cleans and invalidate L1 and L2 caches before jumping to Linux
by set/way in cleanup_before_linux(). Additionally there is a custom
hook provided to clean and invalidate L3 cache.
Unfortunately on K3 devices(having a coherent architecture), there is no
easy way to quickly clean all the cache lines for L3. The entire address
range needs to be cleaned and invalidated by Virtual Address. This can
be implemented using the L3 custom hook but it take lot of time to clean
the entire address range. In the interest of boot time this might not be
a viable solution.
The best hit is to make sure the loaded Linux image is flushed so that
the entire image is written to DDR from L3. When Linux starts running with
caches disabled the full image is available from DDR.
Reported-by: Andrew F. Davis <afd@ti.com>
Reported-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Store the start and end of the OS image that is loaded in images
structure.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Once the arch specific boot_prepare_linux completes, boards wants to
have a custom preparation for linux. Add support for a custom
board_prep_linux.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Expand SPL_MULTI_DTB_FIT to accommodate usb peripheral nodes being
added to support SPL_DFU bootmode.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
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Enable configs for supporting SPL_DFU bootmode.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
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Add usb peripheral and usb phy nodes in spl to enable SPL_DFU bootmode.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
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- DWC3 improvements
- i.MX7 EHCI bugfix
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https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
Second set of u-boot-atmel features and fixes for 2020.01 cycle
This feature set includes Eugen's work on a new tiny flexcom driver and
eeprom mac retrieval for the sam9x60-ek board.
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https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx/FPGA changes for v2020.01 part 2
common:
- Fix manual relocation for repeatable commands
arm:
- Also clean up generated dtbos
microblaze:
- Add support for Manual relocation in crypto framework
- Tune and align architecture bootm support
zynq:
- DT sync ups
- Some defconfig updates
- Remove empty board_early_init_f()
zynqmp:
- Clean firmware handing via drivers/firmware/
- DT/defconfig name alignments
- DT cleanups with using firmware based clock driver
- Some defconfig updates
- Add IIO ina226 DT description
- Tune zynqmp_psu_init_minimalize.sh script
- Add single nand mini configuration, e-a2197, m-a2197-02/03 and zcu216
versal:
- Clean firmware handing via drivers/firmware/
- Add gpio support
- Enable DT overlay/USB/CLK/FPGA
- DT updates
- Tune mini configuration
spi:
- gqspi - Remove unused headers
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Some configs are selected in Kconfig and is no longer needed in the
defconfig files. Some configs (power domain, ram) are never used.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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Some drivers (clk, pinctrl, reset, ...) are necessary for reset of the
system, they should be always selected.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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This patch changes baudrate table for all boards preparing for using mtk
highspeed uart driver.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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This patch adds default eth pinctrl for all boards.
There are two pinctrl nodes used for two scenarios:
ephy_iot_mode - for IOT boards which have only one port (PHY0)
ephy_router_mode - For routers which have more than one ports
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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This adds default pinctrl (dual SPI chip select) for gardena smart gateway
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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This patch adds mmc related nodes for mt7628an.dtsi
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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This patch adds a dts property cd-active-high for builtin-cd mode to make
it configurable instead of using hardcoded active-low.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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This patch adds mmc support for MediaTek MT7620/MT7628 SoCs.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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This patch adds default p0led status and phy0 link polling for all boards.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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This patch add support for mt7628-eth to isolate LAN/WAN ports mainly to
prevent LAN devices from getting IP address from WAN.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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When received a packet with an invalid length recorded in rx descriptor,
we should free this rx descriptor to allow us to continue to receive
following packets.
Without doing so, u-boot will stuck in a dead loop trying to process this
invalid rx descriptor.
This patch adds a call to mt7628_eth_free_pkt() after received an invalid
packet length.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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The mt7628 has an embedded ethernet switch (5 phy ports + 1 cpu port).
Although in IOT mode only port0 is usable, the phy0 is still connected
to the switch, not the ethernet gmac directly.
This patch rewrites it and makes it optional. It can be turned on by adding
mediatek,poll-link-phy = <?> explicitly into the eth node. By default the
driver is switch mode with all 5 phy ports working without link detection.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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This patch removes hardcoded gpio settings as they have been replaced by
pinctrl in dts, and also replaces regmap-based phy reset with a more
generic reset controller.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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This patch adds slew rate calibration for mt76x8-usb-phy, removes code
which belongs to mt7620, and gets rid of using syscon and regmap by using
clock driver and reset controller.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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This patch updates reset controller node for mt7628
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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This patch adds reset controller driver for MediaTek MIPS platform and
header file for mt7628.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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This patch adds default pinctrl for uart nodes
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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This patch adds pinctrl node with default pin state for mt7628an.dtsi.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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This patch adds pinctrl support for mt7628, with a file for common pinmux
functions and a file for mt7628 which has additional support for pinconf.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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Currently this driver uses a different way to implement the spi xfer,
by modifying some fields of two registers, which is incompatible with the
MTK's original SDK linux driver. This will cause the flash data being
damaged by the SDK driver.
This patch lets the mt7621_spi_set_cs() restore the original register
fields after cs deactivated.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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The mt7621 spi controller supports continuous generic half-duplex spi
transaction. There is no need to cache xfer data at all.
To achieve this goal, the OPADDR register must be used as the first data
to be sent. And follows the eight generic DIDO registers. But one thing
different between OPADDR and DIDO registers is OPADDR has a reversed byte
order.
With this patch, any amount of data can be read/written in a single xfer
function call.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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This patch lets the spi driver to use clock provided by the clk driver
since the new clk-mt7628 driver provides accurate sys clock frequency.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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This patch adds clkctrl node for mt7628 and adds clocks property for
some node.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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This patch adds a clock driver for MediaTek MT7628/7688 SoC.
It provides clock gate control as well as getting clock frequency for
CPU/SYS/XTAL and some peripherals.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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All three UARTs of mt7628 are actually MediaTek's high-speed UARTs which
support baudrate up to 921600.
The high-speed UART is compatible with ns16550 when baudrate <= 115200.
Add compatible string to dtsi file so u-boot can use it when serial_mtk
driver is built in.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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The UART of MT7628 has fixed 40MHz input clock so there is no need to put
clock-frequency in every dts files. Just put it into the common dtsi file.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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This patch adds non-DM version for mtk hsuart driver and makes it
compatible with ns16550a driver in configuration.
This is needed in SPL with CONFIG_SPL_DM disabled for reducing size.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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This patch adds codes to enable FIFO and disable flow control taken from
ns16550 driver.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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The current brcmnand driver is based on 4.18 linux kernel which uses
mtd_set_ooblayout to set ecc layout. But nand base code in u-boot is from
old kernel which does not use this new API and expect nand_chip.ecc.layout
structure to be set. This cause nand_scan_tail function running into a bug
check if the device has a different oob size than the default ones.
This patch ports the brcmstb_choose_ecc_layout function from kernel 4.6.7
that supports the ecc layout struture and replaces the mtd_set_ooblayout
method
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
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Fixes commit 344db3f, which added missing bmips dtbs depending on their SoCs.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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These are no longer needed.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
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BCM63268 uses 4.0 HW nand controller, which is currently supported by
brcmnand driver.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
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BCM6362 uses old 2.2 HW nand controller, which isn't currently supported by
brcmnand driver.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
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