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2021-05-13fdt_support: move fdt_valid from cmd_fdt.c to fdt_support.cKory Maincent
Move the fdt_valid function to fdt_support. This changes allow to be able to test the validity of a devicetree in other c files. Update code syntax. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Maxime Ripard <maxime@cerno.tech>
2021-05-12Merge tag 'ti-v2021.07-rc3' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-ti - Initial support for AM64 EVM and SK - K3 DDR driver unification for J7 and AM64 platforms. - Minor fixes for TI clock driver
2021-05-12ARM: dts: k3-am642-sk: Add ethernet related DT nodesVignesh Raghavendra
Add CPSW related nodes for AM642 SK. There are two CPSW ports on the board but U-Boot supports only the first port. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12ARM: dts: k3-am64-main: Add CPSW DT nodesVignesh Raghavendra
AM64 as CPSW3G IP with 2 external ports. Add DT entries for the same (based on kernel DT). Disable second port as its by default set to ICSS usage on EVM. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12net: ti: am65-cpsw-nuss: Add a new compatible for AM64Vignesh Raghavendra
Add a new compatible to support AM64 SoC Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12net: ti: am65-cpsw-nuss: Don't cache disabled port IDVignesh Raghavendra
Currently driver may end up caching disabled port ID as active interface. Fix this by bailing out earlier in case port is marked disabled in the DT. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12net: ti: am65-cpsw-nuss: Prepare to support non primary ext portVignesh Raghavendra
CPSW NUSS IP on K3 SoCs can have more than one external port (upto 8) Therefore increase AM65_CPSW_CPSWNU_MAX_PORTS to 9 (8 ext + 1 Root port) as preparation to allow any one of the 8 ports to be used as ethernet interface in U-Boot. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12dma: ti: k3-udma: Add BCDMA and PKTDMA supportVignesh Raghavendra
Sync BCDMA and PKTDMA support from Kernel for AM64 SoC Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12dma: ti: k3-psil-am64: Add AM64 PSIL endpoint dataVignesh Raghavendra
Add AM64 SoC specific channel mapping and endpoint data. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12dma: ti: k3-psil: Extend PSIL EP data extension for AM64Vignesh Raghavendra
Extend PSIL EP data to include AM64 DMA specific information Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12dma: ti: k3-psil-am654: Drop unused PSIL EP static dataVignesh Raghavendra
ICSSG Ethernet driver uses two src threads per port (one per slice). Similarly CPSW uses one src thread. Drop PSIL EP static data for other src threads in order to reduce R5 SPL footprint. This makes AM65x board bootable again. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12soc: ti: k3-navss-ringacc: Remove unused ring modesVignesh Raghavendra
With AM64x supporting only K3_NAV_RINGACC_RING_MODE_RING or the exposed ring mode, all other K3 SoCs have also been moved to this common baseline. Therefore drop other modes such as K3_NAV_RINGACC_RING_MODE_MESSAGE (and proxy) to save on SPL footprint. There is a saving of ~800 bytes with this change for am65x_evm_r5_defconfig. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2021-05-12soc: ti: k3-navss-ringacc: Add AM64 ringacc supportVignesh Raghavendra
AM64 dual mode rings are modeled as pair of Rings objects which has common configuration and memory buffer, but separate real-time control register sets for each direction mem2dev (forward) and dev2mem (reverse). AM64 rings must be requested only using k3_ringacc_request_rings_pair(), and forward ring must always be initialized/configured. After this any other Ringacc APIs can be used without any callers changes. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12firmware: ti_sci: Update ti_sci_cmd_rm_udmap_tx_ch_cfg() API to the latestVignesh Raghavendra
Update struct ti_sci_msg_rm_udmap_tx_ch_cfg_req to latest ABI to support AM64x BCDMA Block copy channels. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12board: ti: am64x: Parse MAC address from board EEPROMVignesh Raghavendra
Parse MAC addresses from EEPROM and set them in the env. This is needed to get MAC address for additional ethernet ports on the EVM. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12configs: am64x_evm_a53: Enable support for building multiple dtbsLokesh Vutla
Enable all relevant configs for building multiple dtbs into a single fit image and load the right dtb for next stage. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12configs: am64x_evm_a53: Enable support for reading eepromLokesh Vutla
Enable relevant configs for reading eeprom data and updating env variables. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12configs: am64x_evm_a53: Enable configs for printing cpuinfoLokesh Vutla
Enable all relevant configs for printing CPU info. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12configs: am64x_evm_r5: Enable support for building multiple device treesLokesh Vutla
Enable defconfigs for building multiple device trees into a single FIT image. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12configs: am64x_evm_r5: Enable checks for spl and stack sizesLokesh Vutla
Enable relevant configs that checks for the size of image and stack: BSS: 4KB Initial MALLOC: 512KB Initial Stack: 8K SPL Image size can be: ~960KB Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12arm: dts: am642-r5-sk: Add r5 specific dtsLokesh Vutla
Add R5 specific dts for AM64 SK Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2021-05-12arm: dts: am642-sk: Add initial sk dtsLokesh Vutla
AM642 StarterKit (SK) board is a low cost, small form factor board designed for TI’s AM642 SoC. It supports the following interfaces: * 2 GB LPDDR4 RAM * x2 Gigabit Ethernet interfaces capable of working in switch and MAC mode * x1 USB 3.0 Type-A port * x1 UHS-1 capable µSD card slot * 2.4/5 GHz WLAN + Bluetooth 4.2 through WL1837 * 512 Mbit OSPI flash * x2 UART through UART-USB bridge * XDS110 for onboard JTAG debug using USB * Temperature sensors, user push buttons and LEDs * 40-pin Raspberry Pi compatible GPIO header * 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO) * 54-pin header for Programmable Realtime Unit (PRU) IO pins * Interface for remote automation. Includes: * power measurement and reset control * boot mode change Add basic support for AM642 SK. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12arm: dts: am642-evm: Add I2C nodesLokesh Vutla
Add I2C nodes for AM64 and enable pinmux for i2c0 for reading eeprom data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12arm: dts: k3-am642-r5-evm: Do not use power-domains for I2CLokesh Vutla
I2C EEPROM will be probed before SYSFW is available. So drop the power-domains property for I2C. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12arm: dts: k3-am64-evm: Make chip id available before pre-relocLokesh Vutla
Chipid will be needed for SoC detection for all stages of U-Boot. So make it u-boot,dm-spl Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12include: configs: Update env for selecting right dtbLokesh Vutla
Now that single defconfig can be used for booting AM64 EVM and SK, default device tree will not work for selecting dtb for kernel. Update the env to select right dtb based on eeprom. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12include: configs: am64x_evm: Optimize size of SPL BSSLokesh Vutla
Current BSS allocation of SPL is as below: size spl/u-boot-spl text data bss dec hex filename 144572 5484 1752 151808 25100 spl/u-boot-spl But 20KB is allocated currently for BSS. Reduce it to 4KB and save some space for stack. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12include: configs: am64x: Avoid overlap of BSS and stack areaLokesh Vutla
Avoid R5 SPL stack writing into ROM index table. Re-use the same space for storing EEPROM data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12arm: am64x: Add support for selecting DT based on EEPROMLokesh Vutla
Enable support for selecting DTB within SPL based on EEPROM. This will help to use single defconfig for both EVM and SK Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12board: ti: am64x: Add support for detecting multiple device treesLokesh Vutla
Update the board_fit_config_name_match() to choose the right dtb. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12board: ti: am64x: Enable support for reading EEPROM in R5 SPLLokesh Vutla
Include the relevant configs to enable support for reading EEPROM in R5SPL. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12board: ti: am64x: Add support for reading eeprom dataLokesh Vutla
I2C EEPROM data contains the board name and its revision. Add support for: - Reading EEPROM data and store a copy at end of SRAM - Updating env variable with relevant board info - Printing board info during boot. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12soc: ti: k3-socinfo: Add entry for AM64X SoC familyLokesh Vutla
Add support for AM64 SoC identification. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12configs: am64x_evm_r5: Enable GPIO regulatorNishanth Menon
Enable GPIO regulator. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12arm: dts: k3-am642-r5-evm: Add GPIO DDR VTT regulatorNishanth Menon
Add DDR VTT regulator. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12arm: dts: k3-am64-main: Add GPIO nodesNishanth Menon
Add main domain GPIO nodes. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12arm: mach-k3: am642: Add support for triggering ddr init from SPLDave Gerlach
In SPL, DDR should be made available by the end of board_init_f() so that apis in board_init_r() can use ddr. Adding support for triggering DDR initialization from board_init_f(). Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12arm: dts: k3-am642: Add ddr nodeDave Gerlach
Introduce ddr node for am642 needed for all ddr configurations. Also, introduce the 1600MTs DDR4 configuration that is supported on the am642-evm. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-ddrss: Enable vtt regulator if presentLokesh Vutla
Attempt to get and enable a vtt regulator if one is provided from the dts. If we do not find one, continue as not all platforms have this. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-ddrss: Introduce support for AM642 SoCsDave Gerlach
Introduce support for the AM64 DDRSS controller which uses the 16bit variation of the controller. This controller shares much functionality with the existing J721e support, so this patch introduces only the new code needed for am64 specific support from "_16bit_" files with headers under "16bit/" include path/. Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use with CONFIG_K3_DDRSS to allow selecting AM64 support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-ddrss: Introduce common driver with J7 SoC supportDave Gerlach
Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-ddrss: Introduce top-level CONFIG_K3_DDRSSDave Gerlach
Create a new CONFIG_K3_DDRSS option to select the common parts of the k3-ddrss driver. Also introduce a choice that depends on the top level option to select CONFIG_K3_J721E_DDRSS for j721e support, and update corresponding Kconfig as required. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: Rename to k3-ddrssDave Gerlach
Rename the k3-j721e folder under drivers/ram to k3-ddrss in preparation of introducing additional support for other platforms to the same driver. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_ctl_regs: Fix checkpatch issue for typesDave Gerlach
Use Linux style u32 instead of uint32_t. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_pi_macros: Fix indentation issuesDave Gerlach
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_phy_core_macros: Fix indentation issuesDave Gerlach
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_ddr_controller_macros: Fix indentation issuesDave Gerlach
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_data_slice_3_macros: Fix indentation issuesDave Gerlach
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_data_slice_2_macros: Fix indentation issuesDave Gerlach
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_data_slice_1_macros: Fix indentation issuesDave Gerlach
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
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