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2019-05-23armv7: timer: init timer with bootstagePatrick Delaunay
In initf_bootstage() we call bootstage_mark_name() which ends up calling timer_get_us() before timer_init(); that cause crash for stm32mp1. This patch solve the issue without changing the initialization sequence. See also commit 97d20f69f53e ("Enable CONFIG_TIMER_EARLY with bootstage") for other solution when DM is activated for TIMER. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: add bootcount supportPatrick Delaunay
Activate bootcount and use TAMP register to store the count value. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23mkimage: change stm32image header to manage binary informationPatrick Delaunay
To get more information from STM32 Header about the generated binary, we will add a new byte with the following field: replace padding byte 255 with 0x00 for "U-Boot" Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23i2c: stm32f7: improve loopback in timing algorithmNicolas Le Bayon
This avoids useless loops inside the I2C timing algorithm. Actually, we support only one possible solution per prescaler value. So after finding a solution with a prescaler, the algorithm can switch directly to the next prescaler value. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23i2c: stm32f7: Fix SDADEL minimum formulaNicolas Le Bayon
It conforms with Reference Manual I2C timing section. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: update RCC binding after kernel realignmentPatrick Delaunay
RCC is no more a mfd and add a complete example and alignment with latest TF-A binding Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: psci: add synchronization with ROM codePatrick Delaunay
Use SGI0 interruption and TAMP_BACKUP_MAGIC_NUMBER to synchronize the core1 boot sequence requested by core0 in psci_cpu_on(): - a initial interruption is needed in ROM code after RCC_MP_GRSTCSETR_MPUP1RST (psci_cpu_off) - the ROM code set to 0 the 2 registers + TAMP_BACKUP_BRANCH_ADDRESS + TAMP_BACKUP_MAGIC_NUMBER when magic is not egual to BOOT_API_A7_CORE0_MAGIC_NUMBER This patch solve issue for cpu1 restart in kernel. echo 0 > /sys/devices/system/cpu/cpu1/online echo 1 > /sys/devices/system/cpu/cpu1/online Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: cosmetic: bsec: reorder include filesPatrick Delaunay
Reorder the include files in alphabetic order. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: migrate PREBOOT to KconfigPatrick Delaunay
Use Kconfig to activate CONFIG_PREBOOT (empty by default). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: Move ENV_SIZE and ENV_OFFSET to KconfigPatrick Delaunay
Add arch stm32mp for ENV migration step and drop more items from include/configs/xxx.h. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: Move config SYS_MALLOC_LEN to KconfigPatrick Delaunay
This patch moves the the config SYS_MALLOC_LEN to Kconfig as it is already done for zynq arch in commit 01aa5b8f0503 ("Kconfig: Move config SYS_MALLOC_LEN to Kconfig for zynq") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-22Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
Changes from rc2 tag - Support PCIe Gen4 driver of the Mobiveil IP - NXP LS1028A SoC and platform support - Few SPI related config updates - Distinguish the ecc val by chassis version and move the ecc addr to dts - sp805 watchdog support
2019-05-22armv8: lx2160: Drop useless CONFIG_CMDLINE_EDITING from config.hAndy Shevchenko
commit 58c3e62040be ("armv8: lx2160ardb : Add support for LX2160ARDB platform") brought a new boards support with redundancy in the config.h. One of them is CONFIG_CMDLINE_EDITING which is removed by this change. Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Peng Ma <peng.ma@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22config: enable SP805 watchdog support for LS1028AQiang Zhao
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22arm: dts: fsl-ls1028a: add sp805 watchdog nodeQiang Zhao
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22driver: watchdog: add sp805 watchdog supportQiang Zhao
sp805 is watchdog on some NXP layerscape SoCs, adding it's driver. Configs CONFIG_WDT_SP805, CONFIG_WDT, CONFIG_CMD_WDT needs to be enabled to use it. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22configs: Unset CONFIG_SPI_BAR for all LS2080A/LS2081A defconfigsRajat Srivastava
Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22configs: Unset CONFIG_SPI_BAR for all LS1046A defconfigsRajat Srivastava
Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22configs: Unset CONFIG_SPI_BAR for all LS1088A defconfigsAshish Kumar
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE.Udit Agarwal
ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: Secure Boot: Modify boot_a_script definitionVinitha V Pillai
esbc_validate command will not be executed if “load” command for its header fails and will further execute the source command for bootscript, without its validation and boot process continues. To halt the boot process in case secure boot header is not loaded successfully, esbc_validate command is invoked separately after “load” command. The secure boot validation of the bootscript header will fail (if header is not loaded) and halts the boot process, which prevent source command from execution. Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22board: fsl: lx2160ardb: invert AQR107 pins polarityFlorin Chiculita
AQR107 PHYs interrupt pins are active-low, while the GIC expects a level-high signal. Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22scsi: ceva: Clean up the driver codePeng Ma
Distinguish the ecc val by chassis version and move the ecc addr to dts. Add ls1028a soc support. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22ARM: dts: Freescale: Add ecc addr for sata nodePeng Ma
Move the ecc addr from driver to dts. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22configs: Enable CONFIG_SPI_FLASH for ls1088ardb_defconfigChuanhua Han
Enables CONFIG_SPI_FLASH Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: ls1028aqds: Add support of LS1028AQDSYuantian Tang
LS1028AQDS Development System is a high-performance computing, evaluation, and development platform that supports LS1028A QorIQ Architecture processor. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang yuantian <andy.tang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: ls1028ardb: Add support for LS1028ARDBYuantian Tang
LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluation platform that supports the LS1028A family SoCs. This patch add basic support of the platform. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: ls1028a: Add NXP LS1028A SoC supportYuantian Tang
Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: lx2160a: enable PCIe supportHou Zhiqiang
Enable the PCIe Gen4 controller driver and e1000 for LX2160ARDB and LX2160AQDS boards. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: lx2160a: add PCIe controller DT nodesHou Zhiqiang
The LX2160A integrated 6 PCIe Gen4 controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22pci: ls_pcie_g4: add device tree fixups for PCI Stream IDsHou Zhiqiang
Add the infrastructure for Layerscape SoCs PCIe Gen4 controller to update device tree nodes to convey SMMU stream IDs in the device tree. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22kconfig: add dependency PCIE_LAYERSCAPE_GEN4 for FSL_PCIE_COMPATHou Zhiqiang
The LX2160A PCIe is using driver PCIE_LAYERSCAPE_GEN4 instead of PCIE_LAYERSCAPE. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCsHou Zhiqiang
Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe controller is based on the Mobiveil IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: lx2160a: add MMU table entries for PCIeHou Zhiqiang
The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: fsl-layerscpae: correct the PCIe controllers' region sizeHou Zhiqiang
The LS2080A has 8GB region for each PCIe controller, while the other platforms have 32GB. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: layerscape: use PCIe address macro for precompile PCIe MMU entryHou Zhiqiang
Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22configs: ls1046: Update mtd-id for QSPI nor in mtdparts variableKuldeep Singh
Update mtd-id for QSPI nor due to change introduced in mtd/spi in linux 5.0. commit 84d043185dbe ("spi: Add a driver for the Freescale/NXP QuadSPI controller") This modification is only for linux kernel version >= 5.0. To use bootargs for kernel < 5.0, use the following bootargs CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:2m(uboot),14m(free)" CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:2m(uboot),14m(free)" Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-21Merge git://git.denx.de/u-boot-mpc83xxTom Rini
- Update MPC83xx platform support to current best practices, etc.
2019-05-21Merge tag 'mmc-5-20' of https://github.com/MrVan/u-bootTom Rini
"Please pull mmc-5-20 for v2019.07, this is to avoid break i.MX53 boot."
2019-05-21Merge tag 'video-for-2019.07-rc3' of git://git.denx.de/u-boot-videoTom Rini
- update for using splashfile instead of location->name when loading the splash image from a FIT - updates for loading internal and external splash data from FIT - DM_GPIO/DM_VIDEO migration for mx53 cx9020 board - fix boot issue on mx6sabresd board after DM_VIDEO migration - increase the max preallocated framebuffer BPP to 32 in ipuv3 driver to prepare for configurations with higher color depth - allow to use vidconsole_put_string() in board code for text output on LCD displays
2019-05-21mpc83xx: Add gazerbeam boardDirk Eibach
The gdsys gazerbeam board is based on a Freescale MPC8308 SOC. It boots from NOR-Flash, kernel and rootfs are stored on SD-Card. On board peripherals include: - 2x 10/100 Mbit/s Ethernet (optional) Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gazerbeam: Add u-boot specific dts include fileMario Six
Add a U-Boot specific dts file, which encapsulates the needed modifications to the Gazerbeam Linux device tree. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gazerbeam: Import Linux DTMario Six
Import the Linux device tree for the Gazerbeam board. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21board: gazerbeam: Fix SC detectionMario Six
The single channel detection in the gazerbeam board driver was not implemented correctly. Fix the detection. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gdsys: ioep-fpga: Switch to gazerbeam-style reportingMario Six
Use a more extensive FPGA feature reporting style in the gdsys ioep-fpga driver. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gdsys: cmd_ioloop: Make DM compatibleMario Six
Make the ioloop command DM compatible, while keeping the old functionality for not-yet-converted boards. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gdsys: cmd_ioloop: Introduce commenting enumMario Six
Replace the boolean parameter of io_check_status that controls whether the status is printed or not with a documenting enum. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gdsys: cmd_ioloop: Fix style violationsMario Six
Fix some style violations in the ioloop command, and make the code more readable where possible. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gdsys: mpc8308: Add FPGA flavor optionMario Six
More recent versions of IHS FPGAs feature a different memory layout. Add a Kconfig option to differentiate between the legacy layout, and the new layout (which is used on the upcoming "Gazerbeam" and later boards). Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gdsys: Introduce GDSYS_LEGACY_DRIVERSMario Six
Future gdsys boards will switch from the legacy drivers in board/gdsys/common to DM-based drivers. Define a Kconfig option that disables the legacy drivers. Signed-off-by: Mario Six <mario.six@gdsys.cc>
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