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2018-05-14net: mvneta: Fix fault when wrong device treeMarek Behún
The driver does not check id phy_connect failed (for example on wrong property name in device tree). In such a case a fault occurs and the CPU is restarted. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: core: Cosmetic fixesMarek Behún
Move the reg_set* functions into comphy.h as static inline functions. Change return type of get_*_string to const char *. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14clk: armada-37xx: Support soc_clk_dumpMarek Behún
Add support for the clk dump command on Armada 37xx. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14spi: mvebu_a3700_spi: Use Armada 37xx clk driver for SPI clock frequencyMarek Behún
Since now we have driver for clocks on Armada 37xx, use it to determine SQF clock frequency for the SPI driver. Also change the default config files for Armada 37xx devices so that the clock driver is enabled by default, otherwise the SPI driver cannot be enabled. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14driver: clk: Add support for clocks on Armada 37xxMarek Behún
The drivers are based on Linux driver by Gregory Clement. The TBG clocks support only the .get_rate method. - since setting rate is not supported, the driver computes the rates when probing and so subsequent calls to the .get_rate method do not read the corresponding registers again The peripheral clocks support methods .get_rate, .enable and .disable. - the .set_parent method theoretically could be supported on some clocks (the parent would have to be one of the TBG clocks) - the .set_rate method would have to try all the divider values to find the best approximation of a given rate, and it doesn't seem like this should be needed in U-Boot, therefore not implemented Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Save/restore selector reg in SGMII initMarek Behún
In SGMII initialization PIN_PIPE_SEL has to be zero when resetting the PHY. Since comphy_mux already set the selector register to correct values, we have to store it's value before setting it to 0 and restore it after SGMII init. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Use comphy_mux on Armada 37xx.Marek Behún
Lane 0 supports SGMII1 and USB3. Lane 1 supports SGMII0 and PEX0. Lane 2 supports SATA0 and USB3. This is needed for Armada 37xx. This introduces new device tree bindings. AFAIK there is currently no driver for Armada 37xx comphy in Linux. When such a driver will be pushed into Linux, this will need to be rewritten accordingly. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Fix SGMII cfg and stat register addressesMarek Behún
The register addresses on lanes 0 and 1 are switched, first comes 1 and then 0. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: mux: Support nontrivial node order in selector registerMarek Behún
Currently comphy_mux supports only trivial order of nodes in pin selector register, that is lane N on position N*bitcount. Add support for nontrivial order, with map stored in device tree property mux-lane-order. This is needed for Armada 37xx. As far as I know, there is no driver for Armada 37xx comphy in the kernel. When such a driver comes, this will need to be rewritten to support the device tree bindings from the kernel. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: revise the USB3 comphy setting during power onzachary
This commit is based on commit d9899826 by zachary <zhangzg@marvell.com> from u-boot-marvell, see github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/d9899826 - According to design specification, the transmitter should be set to high impedence mode during electrical idle. Thus transmitter should detect RX at high impedence mode also, and delay is needed to accommodate high impedence off latency. Otherwise the USB3 will have detection issue that most of the time the USB3 device can not be detected at all, or be detected as USB2 device sometimes. Modified registers: RD005C302h (R181h) (0051h) Lane Configuration 1 Bit 6: set to 1 to let Tx detect Rx at HiZ mode Bit [3:4]: set to 2 to be delayed by 2 clock cycles Bit 0: set to 1 to set transmitter to high impedance mode during idle. - USB3 De-emphasize level of -3.5dB is mandatory, but USB3 MAC selects 0x2 (emphasize disabled) in the MAC_PHY_TXDEEMPH [1:0], while it is supposed to select 0x1(3.5dB emphasize). Thus need to override what comes from the MAC(by setting register 0x1c2 bit2 to 0x1) and to configure the overridded values of MAC_PHY_TXDEEMPH [1:0] to 0x1(bit15 of register 0x181 and bit0 of register 0x180). - According to USB3 application note, need to update below comphy registers: Set max speed generation to USB3.0 5Gbps(set RD005C04Ah bit[11:10] to 1) Set capacitor value to 0xF(set RF005C224 bit[3:0] to 0xF) Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Set USB3 RX wait depending on ref clockMarek Behún
According to specification, CFG_PM_RXDLOZ_WAIT should be set to 0x7 when reference clock is at 25 MHz. The specification (at least the version I have) does not mentoin the setting for 40 MHz reference clock, but Marvell's U-Boot sets 0xC in that case. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Access USB3 register indirectly on lane 2Marek Behún
When USB3 is on comphy lane 2 on the Armada 37xx, the registers have to be accessed indirectly via SATA indirect access. This is the case of the Turris Mox board from CZ.NIC. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Use reg_set_indirect istead of 2 reg_setsMarek Behún
Create a special function for indirect register setting, reg_set_indirect, and use it instead of the two calls to reg_set. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Use (!ret) instead of (ret == 0)Marek Behún
In U-Boot it is usually written this way. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Use same timeout for all register pollingMarek Behún
The timeout is set to PLL_LOCK_TIMEOUT in every call to comphy_poll_reg. Remove this parameter from the function. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Don't create functional macro for each registerMarek Behún
Currently there is for each register special functional macro, ie: LANE_CFG1_ADDR(u) GLOB_CLK_SRC_LO_ADDR(u) ... where can be either PCIE or USB3. Change this to one function PHY_ADDR(unit, addr). The code becomes: phy_addr(PCIE, LANE_CFG1) phy_addr(PCIE, GLOB_CLK_SRC_LO) ... Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Use reg_set16 instead of phy_write16Marek Behún
The macro phy_write16 is not used by the rest of the code, phy_read16 is not used at all. We also change the macro SGMIIPHY_ADDR to a static inline function. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Change return type of macro MVEBU_REGMarek Behún
All the calls to reg_set and friends have to cast the first argument to void __iomem *. Lets change the return type of the MVEBU_REG macro instead. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-13mmc: Improve tinificationMarek Vasut
Drop all the extra content from the MMC core, so that tiny MMC support is really tiny, no fancy anything. That means the tiny MMC support does only 1-bit transfers at default speed settings. Moreover, this patch drops duplicate instance of struct mmc mmc_static, which wasted about 360 bytes. Furthermore, since MMC tiny supports only one controller at all times, get rid of mallocating the ext csd backup and replace it with static array. All in all, this patch saves ~4 kiB of bloat from the MMC core, which on platforms with severe limitations can be beneficial. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> [trini: Fixup checkpatch.pl style warnings] Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-11Merge git://git.denx.de/u-boot-tegraTom Rini
2018-05-11SPDX: Correct SPDX tags from recent xilinx mergeTom Rini
Correct the SPDX tag format. Fixes: 3b52847a451a ("Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze") Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-11Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblazeTom Rini
Xilinx changes for v2018.07 microblaze: - Align defconfig zynq: - Rework fpga initialization and cpuinfo handling zynqmp: - Add ZynqMP R5 support - Wire and enable watchdog on zcu100-revC - Setup MMU map for DDR at run time - Show board info based on DT and cleanup IDENT_STRING zynqmp tools: - Add read partition support - Add initial support for Xilinx bif format for boot.bin generation mmc: - Fix get_timer usage on 64bit cpus - Add support for SD3.0 UHS mode nand-zynq: - Add support for 16bit buswidth - Use address cycles from onfi params scsi: - convert ceva sata to UCLASS_AHCI timer: - Add Cadence TTC for ZynqMP r5 watchdog: - Minor cadence driver cleanup
2018-05-11Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2018-05-11arm64: zynqmp: Enable UHS support for ZCU102 Rev1.0 boardSiva Durga Prasad Paladugu
This patch enables UHS support for ZynqMP zcu102 rev 1.0 board. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11mmc: zynq_sdhci: Add support for SD3.0Siva Durga Prasad Paladugu
This patch adds support of SD3.0 for ZynqMP. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11mmc: sdhci: Read capabilities register1 and update host capsSiva Durga Prasad Paladugu
This patch reads the capabilities register1 and update the host caps accordingly for mmc layer usage. This patch mainly reads for UHS capabilities inorder to support SD3.0. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11mmc: sdhci: Invoke platform specific tuning and delay routinesSiva Durga Prasad Paladugu
This patch adds support to invoke any platform specific tuning and delay routines if available. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11sdhci: Add new sdhci ops for platform specific tuning and delaysSiva Durga Prasad Paladugu
This patch adds new hooks for any platform specific tuning and tap delays programing. These are needed for supporting SD3.0. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11mmc: sdhci: Handle execute tuning command in sdhci_send_commandSiva Durga Prasad Paladugu
This patch upadted sdhci_send_command to handle execute tuning command. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11mmc: sdhci: Add support for disabling clockSiva Durga Prasad Paladugu
This patch adds support to disable clock if clk_disable was set and then enable or set clock if the clock was changed or clock was disabled when clock needs to be enabled. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11mmc: Changed the datatype of the variable to handle 64-bit archVipul Kumar
This patch changed the datatype of variable "start" from uint to ulong to work properly on 64-bit machines as well. Also the return type of get_timer() function is ulong. Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11arm: zynqmp: Add ZynqMP minimal R5 supportMichal Simek
Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot. This patch is adding minimal support to get U-Boot boot. U-Boot on R5 runs out of DDR with default configuration that's why DDR needs to be partitioned if there is something else running on arm64. Console is done via Cadence uart driver and the first Cadence Triple Timer Counter is used for time. This configuration with uart1 was tested on zcu100-revC. U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200) Model: Xilinx ZynqMP R5 DRAM: 512 MiB WARNING: Caches not enabled MMC: In: serial@ff010000 Out: serial@ff010000 Err: serial@ff010000 Net: Net Initialization Skipped No ethernet found. ZynqMP r5> There are two ways how to run this on ZynqMP. 1. Run from ZynqMP arm64 tftpb 20000000 u-boot-r5.elf setenv autostart no && bootelf -p 20000000 cpu 4 disable && cpu 4 release 10000000 lockstep or cpu 4 disable && cpu 4 release 10000000 split 2. Load via jtag when directly to R5 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11tools: zynqmpimage: Add bif supportAlexander Graf
The officially described way to generate boot.bin files for ZynqMP is to describe the contents of the target binary using a file of the "bif" format. This file then links to other files that all get packed into a bootable image. This patch adds support to read such a .bif file and generate a respective ZynqMP boot.bin file that can include the normal image and pmu files, but also supports image partitions now. This makes it a handy replacement for the proprietary "bootgen" utility that is currently used to generate boot.bin files with FSBL. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11MAINTAINERS: Declare tools/zynqmp* as Xilinx maintainedAlexander Graf
The zynqmpimage.c and the new zynqmpbif.c files are all maintained by Xilinx for the Zynq platforms. Let's match them accordingly in the MAINTAINERS file. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11tools: zynqmpimage: Move defines to headerAlexander Graf
We will add support for ZynqMP bif input files later, so let's move all structure definitions into a header file that can be used by that one as well. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11tools: zynqmpimage: Add partition read supportAlexander Graf
The zynqmp image format has support for inline partitions which are used by FSBL to describe payloads that are loaded by FSBL itself. While we can't create images that contain partitions (yet), we should still at least be able to examine them and show the user what's inside when we analyze an image created by bootgen. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11arm64: zynqmp: Show model information instead of custom IDENT_STRINGMichal Simek
DISPLAY_BOARDINFO in OF case show model identification string from DT. Enable this feature instead of custom IDENT_STRING which does the same thing. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Alexander Graf <agraf@suse.de>
2018-05-11arm64: zynqmp: Simplify boot_target variable compositionMichal Simek
Call calloc for space allocation only at one location and include if/else to sprintf. This will simplify run time device adding based on id aliases. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Alexander Graf <agraf@suse.de>
2018-05-11arm64: zynqmp: Setup MMU map for DDR at run timeNitin Jain
This patch fills the MMU map for DDR at run time based on information read from Device Tree or automatically detected from static configuration. The patch is needed because for systems which has for example 1GB of memory but MMU map is 2GB there could be spurious accesses which was seen in past when mapping is not fitting with actual memory installed. Signed-off-by: Nitin Jain <nitin.jain@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11arm64: zynqmp: Enable cadence WDT for zcu100Michal Simek
Enable watchdog on zcu100 to make sure if there is a bug in the u-boot there is proper reset. Watchdog expires and PMU fw is informed and based on setting proper action is taken. The patch is enabling reset-on-timeout feature and also fixing fixed clock rate for watchdog where 100MHz is max (and also default) clock value. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11arm64: zynqmp: Wire watchdog internalsMichal Simek
Enable watchdog in full U-Boot. Similar changes were done by: "arm: zynq: Wire watchdog internals" (sha1: e6cc3b25d721c3001019f8b44bfaae2a57255162) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11watchdog: cadence: Show used timeout valueMichal Simek
Debug message was showing timeout value which was passed to start function but there is a checking if this value can be setup. The patch is moving this debug printf function below checking. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11arm64: zynqmp: Reset FPD Watchdog on zcu100Michal Simek
Low level configuration didn't reset FPD Watchdog that's why accessing it caused u-boot hang. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11nand: zynq: Send address cycles as per onfi parameter pageSiva Durga Prasad Paladugu
Send address cycles as per value read from onfi parameter page for Read and write commands instead of using a hard coded value. This may vary for different parts and hence use it from onfi parameter page value. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11nand: zynq: Add support for 16-bit buswidthSiva Durga Prasad Paladugu
This patch adds support for 16-bit buswidth by determining the bus width based on mio configuration. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11MAINTAINERS: zynqmp: Point to proper zynqmp folderMichal Simek
Point to Zynqmp arm64 cpu folder not to Zynq arm32. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11serial: zynq: Remove header depedency on arm header structureMichal Simek
There is no need to have arm hardware header in this driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11timer: Add Cadence TTC timer counter supportMichal Simek
This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11microblaze: Dont enable UBI support by defaultSiva Durga Prasad Paladugu
This patch removes UBI support from defconfig and it can be enabled from menuconfig as per need. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11arm64: zynqmp: Add new defconfig for zc1275 revBSiva Durga Prasad Paladugu
This patch enables support zc1275 revB board. It has SD added compared to revA. The same configuration will work for RevC boards aswell. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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