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2022-09-14test: unit test for eficonfigMasahisa Kojima
Provide a unit test for the eficonfig command. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-09-14doc:eficonfig: add documentation for eficonfig commandMasahisa Kojima
Add documentation for eficonfig command. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-09-14doc:bootmenu: add description for UEFI boot supportMasahisa Kojima
The bootmenu enumerates the UEFI boot options for boot device selection. This commit adds the description how the UEFI boot work in bootmenu. This commit also adds "Synopsis", "Description" and "Configuration" sections to follow the U-Boot command documentation format. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-09-14eficonfig: add "Change Boot Order" menu entryMasahisa Kojima
This commit adds the menu entry to update UEFI BootOrder variable. User moves the entry with UP/DOWN key, changes the order with PLUS/MINUS key, press SPACE to activate or deactivate the entry, then finalizes the order by ENTER key. If the entry is activated, the boot index is added into the BootOrder variable in the order of the list. The U-Boot menu framework is well designed for static menu, this commit implements the own menu display and key handling for dynamically change the order of menu entry. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
2022-09-14eficonfig: scan media device in eficonfig startupMasahisa Kojima
In eficonfig startup, scan media devices and update the UEFI boot option. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
2022-09-14bootmenu: add removable media entriesMasahisa Kojima
UEFI specification requires booting from removal media using a architecture-specific default image name such as BOOTAA64.EFI. This commit adds the removable media entries into bootmenu, so that user can select the removable media and boot with default image. The bootmenu automatically enumerates the possible bootable media devices supporting EFI_SIMPLE_FILE_SYSTEM_PROTOCOL, add it as new UEFI boot option(BOOT####) and update BootOrder variable. This automatically generated UEFI boot option has the dedicated guid in the optional_data to distinguish it from the UEFI boot option user adds manually. This optional_data is removed when the efi bootmgr loads the selected UEFI boot option. This commit also provides the BOOT#### variable maintenance feature. Depending on the system hardware setup, some devices may not exist at a later system boot, so bootmenu checks the available device in each bootmenu invocation and automatically removes the BOOT#### variable corrensponding to the non-existent media device. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
2022-09-14eficonfig: add "Delete Boot Option" menu entryMasahisa Kojima
This commit adds the menu entry to delete the UEFI boot option. User moves the entry with UP/DOWN key, changes, then presses ENTER key to delete the selected boot option. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
2022-09-14menu: add KEY_PLUS, KEY_MINUS and KEY_SPACE handlingMasahisa Kojima
This is preparation to support menu-driven UEFI BootOrder variable updated by KEY_PLUS, KEY_MINUS and KEY_SPACE. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-09-14eficonfig: add "Edit Boot Option" menu entryMasahisa Kojima
This commit adds the menu entry to edit the existing BOOT#### variable contents. User selects the item from the boot option list, then user can edit the description, file path and optional_data. Note that automatically generated boot option entry by bootmenu to support the removable media device is filtered out and user can not edit the automatically generated entry. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
2022-09-14eficonfig: menu-driven addition of UEFI boot optionMasahisa Kojima
This commit add the "eficonfig" command. The "eficonfig" command implements the menu-driven UEFI boot option maintenance feature. This commit implements the addition of new boot option. User can select the block device volume having efi_simple_file_system_protocol and select the file corresponding to the Boot#### variable. User can also enter the description and optional_data of the BOOT#### variable in utf8. This commit adds "include/efi_config.h", it contains the common definition to be used from other menus such as UEFI Secure Boot key management. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
2022-09-13Merge branch '2022-09-13-add-aspeed-spi-controller' into nextTom Rini
To quote the author: This patch series aims to porting ASPEED FMC/SPI memory controller driver with spi-mem interface. spi-mem dirmap framework is also synchronized from Linux. These patches have been verified on AST2600, AST2500 and AST2400 EVBs.
2022-09-13mtd: spi-nor-ids: Add Winbond W25Q512JVQ IDChin-Ting Kuo
Add ID for Winbond W25Q512JVQ device which is supported on AST2600 EVB by default. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2022-09-13spi: aspeed: Clock frequency adjustment supportChin-Ting Kuo
Driver can configure the SPI clock frequnecy to the target value of "spi-max-frequency" property in the device tree. The frequency is divided from HCLK, 200MHz. Usually, the ASPEED SPI clock frequency range is between 12.5MHz and 100MHz. On AST2600, the lowest SPI clock frequency can be about 780kHz. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-09-13spi: aspeed: Support customized decoded address rangesChin-Ting Kuo
If "decoded-ranges" is defined in the device tree, the driver will apply the decoded address ranges from this property to the controller during probe stage. This patch refers to the following OpenBMC u-boot patch. https://patchwork.ozlabs.org/project/openbmc/list/?series=306969 Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-09-13spi: aspeed: Adjust decoded range size supportChin-Ting Kuo
There are some known HW problems about decoded range register configurations on existing AST2500 and AST2600 platforms. Additional callback function, adjust_decoded_sz, is added to solve these problems on each platform. Besides, aspeed_spi_trim_decoded_size function is added to modify overall decoded address size for fitting the maximum AHB decoded size. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-09-13configs: aspeed: Enable CONFIG_SPI_DIRMAPChin-Ting Kuo
Enable CONFIG_SPI_DIRMAP on ASPEED platforms. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-09-13spi: aspeed: SPI dirmap read supportChin-Ting Kuo
From the HW point of view, the performance of command read mode is greater than user mode slightly. Thus, dirmap read framework is introduced to achieve this goal. In dirmap_create, command read mode is configured. Usually, the decoded address area with flash size is assigned to each CS. CPU can thus access the SPI flash as normal memory in dirmap_read function. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-09-13mtd: spi-nor: Use spi-mem dirmap APIChin-Ting Kuo
This adds support for the dirmap API to the spi-nor subsystem, as introduced in Linux commit df5c21002cf4 ("mtd: spi-nor: use spi-mem dirmap API"). This patch is synchronize from the following patch https://patchwork.ozlabs.org/project/uboot/patch/20210205043924.149504-4-seanga2@gmail.com/ The corresponding Linux kernel SHA1 is df5c21002cf4. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Signed-off-by: Sean Anderson <seanga2@gmail.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
2022-09-13spi-mem: Add dirmap API from LinuxChin-Ting Kuo
This adds the dirmap API originally introduced in Linux commit aa167f3fed0c ("spi: spi-mem: Add a new API to support direct mapping"). This also includes several follow-up patches and fixes. Changes from Linux include: * Added Kconfig option * Changed struct device to struct udevice * Changed struct spi_mem to struct spi_slave This patch is obtained from the following patch https://patchwork.ozlabs.org/project/uboot/patch/20210205043924.149504-3-seanga2@gmail.com/ The corresponding Linux kernel SHA1 is aa167f3fed0c. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Signed-off-by: Sean Anderson <seanga2@gmail.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
2022-09-13arm: dts: aspeed: Update SPI flash node settingsChin-Ting Kuo
For both AST2500 and AST2600, there are three SPI controllers, FMC(Firmware Memory Controller), SPI1 and SPI2. The clock source is HCLK. Following is the basic information for ASPEED SPI controller. AST2500: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x37ffffff - SPI2: CS number: 2 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x38000000 - 0x3fffffff AST2600: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x3fffffff - SPI2: CS number: 3 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x50000000 - 0x5fffffff Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-09-13spi: aspeed: Support AST2400 platformChin-Ting Kuo
Although AST2400 is EOL officially, in order to achieve sustainability and completeness, AST2400 part is added. For AST2400, - Five CSs are supported by FMC controller. - SPI1 controller only supports single CS and there is no address segment address register. The CE control register of SPI1 is located at the offset 0x04 and the 4-byte address mode control bit is bit 13 of this register. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-09-13configs: aspeed: Enable SPI flash featuresChin-Ting Kuo
- Enable ASPEED SPI controller driver. - Enable SPI flash memory configurations. - Enable configurations for SPI flash manufacturers supported on both ASPEED AST2500 and AST2600 AVL. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-09-13spi: aspeed: Add ASPEED SPI controller driverChin-Ting Kuo
Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface for AST2500 and AST2600 platform. There are three SPI memory controllers embedded in an ASPEED SoC. - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM fetches initial device boot image from FMC chip select(CS) 0. - SPI1: Play the role of a SPI Master controller. Or, there is a dedicated path for HOST(X86) to access its BIOS flash mounted under BMC. spi-aspeed-smc.c implements the control sequence when SPI1 is a SPI master. - SPI2: It is a pure SPI flash controller. For most scenarios, flashes mounted under it are for pure storage purpose. ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. Three types of command mode are supported, normal mode, command read/write mode and user mode. - Normal mode: Default mode. After power on, normal read command 03h or 13h is used to fetch boot image from SPI flash. - AST2500: Only 03h command can be used after power on or reset. - AST2600: If FMC04[6:4] is set, 13h command is used, otherwise, 03h command. The address length is decided by FMC04[2:0]. - Command mode: SPI controller can send command and address automatically when CPU read/write the related remapped or decoded address area. The command used by this mode can be configured by FMC10/14/18[23:16]. Also, the address length is decided by FMC04[2:0]. This mode will be implemented in the following patch series. - User mode: It is a traditional and pure SPI operation, where SPI transmission is controlled by CPU. It is the main mode in this patch. Each SPI controller in ASPEED SoC has its own decoded address mapping. Within each SPI controller decoded address, driver can assign a specific address region for each CS of a SPI controller. The decoded address cannot overlap to each other. With normal mode and command mode, the decoded address accessed by the CPU determines which CS is active. When user mode is adopted, the CS decoded address is a FIFO, CPU can send/receive any SPI transmission by accessing the related decoded address for the target CS. This patch only implements user mode initially. Command read/write mode will be implemented in the following patches. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-09-13pinctrl: aspeed: FWSPICS1 and SPI1CS1 pin supportChin-Ting Kuo
Add FWSPICS1 and SPI1CS1 in AST2500 pinctrl group. On AST2500 EVB, FWSPICS1 can be supported by default. An extra jumper, J45, should be configured before enabling SPI1CS1. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2022-09-13clk: aspeed: Get HCLK frequency supportChin-Ting Kuo
User can get correct HCLK frequency during driver probe stage by adding the following configuration in the device tree. "clocks = <&scu ASPEED_CLK_AHB>". Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2022-09-13Merge tag 'xilinx-for-v2023.01-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2023.01-rc1 cmd: - bdinfo - guard LMB code to run only when LMB is enabled timer: - convert arm twd timer to DM power-domain: - Skip loading config object for Versal xilinx: - Fix logic when dfu_alt_info is generated - Define only mmc devnum not partition - Add xlnx prefix to GEM compatible string - Add missing tca6416 to zynqmp SC - vck190 - Add env redund offset - Enable CMD_GREPENV/SETEXPR by default - Move board_get_usable_ram_top() to common location - Add support for SOC detection net/gem: - Check rate before setting it up microblaze: - drop CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE - Show cache size in bdinfo spi: - cadence_qspi: driver updates - zynqmp_gqspi: driver updates - zynqmp_gqspi: Add tap delays for Versal zynq: - Enable mkeficapsule compilation - Use CONFIG_SPL_FS_LOAD_PAYLOAD_NAME for dfu_alt_info - Align bss and end of u-boot image to 64bits - Align qspi node name with Linux kernel - DT: List OCM memory zynqmp: - Fix AES cache handling with a user provided key - SOM: Add mtd partition for secure OS storage area - Add ref_clk property for REFCLKPER calculation - Fix mdio bus description for vck190-sc xilinx-mini: - Remove unneeded configs - Disable LMB versal: - Enable i2c mux pca954x by default - Define CONFIG_CQSPI_REF_CLK - Enable power domain driver - Enable zynqmp_gqspi driver
2022-09-13Merge branch '2022-09-12-update-pytests-for-more-parellel-support' into nextTom Rini
To quote the author: This series makes a further attempt to get closer to having all tests run in parallel. It introduces a new 'make pcheck' option which runs tests in parallel, skipping those that are not compatible. A number of fixes are included for existing tests. The vboot test is updated to only run a single scenario in 'quick' mode. This makes use of pytest's parallel-testing features. The resulting times (including incremental building with LTO) on a 16-core machine are as follows: make pcheck - 1 minute 6 seconds make qcheck - 3 minutes make check - 5 minutes 15 seconds Note that this is not a fair comparison, since 'make pcheck' omits a number of tests, even more than 'make qcheck'.
2022-09-13xilinx: common: Add support for SOC detectionMichal Simek
Code supports board detection based on information available in EEPROM in legacy or FRU format. But this is not enough for emulation and simulation systems which are lacking these identification EEPROMs. But SOC itself has normally registers for SOC identification. Based on them it is possible to compose detected name. That's why prepare infrastructure in common location for SOC platform detection which is called before board platform detection. SOC platform detection shouldn't detect real silicon and should fallback to current existing mechanism to identify boards based on EEPROMs. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/329a8da338927b082e26a958bf69bb18af072420.1662460837.git.michal.simek@amd.com
2022-09-13xilinx: Fix mdio bus description for vck190-scMichal Simek
Current behavior is that eth_phy_get_mdio_bus Net: FEC: can't find phy-handle ZYNQ GEM: ff0b0000, mdio bus ff0b0000, phyaddr 0, interface sgmii eth0: ethernet@ff0b0000 Net: ZYNQ GEM: ff0b0000, mdio bus ff0b0000, phyaddr 0, interface sgmii eth0: ethernet@ff0b0000 Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/5b7da5808136b3f579c0cf7a3431b56c758655e9.1662460749.git.michal.simek@amd.com
2022-09-13ARM: zynq: DT: List OCM memoryMichal Simek
Description OCM with mmio-sram driver. In 99% use cases OCM is mapped high that's why it is placed on fixed location. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/a951dbe885640197efe3e91bb9fa5caedb54b387.1662460712.git.michal.simek@amd.com
2022-09-13ARM: zynq: Align qspi node name with Linux kernelMichal Simek
Nodes should follow generic rules where compatible and reg properties should be listed on the top of node. That's why sync it up. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/922dca6227cb0aa4f79e6d3595c5f280ba020684.1662460540.git.michal.simek@amd.com
2022-09-13arm64: versal: Enable zynqmp_gqspi driverAshok Reddy Soma
Versal supports gqspi ip, so enable zynqmp_gqspi driver for Versal platforms. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20220825125906.11581-7-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13spi: zynqmp_qspi: Code alignmentAshok Reddy Soma
Few lines are extented to next line though they can fit in 80 character limit, align them to single line. No functional change. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20220825125906.11581-6-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13spi: zynqmp_gqspi: Fix issue of reading more than 32bits lengthAshok Reddy Soma
As the flash sizes are increasing day by day, QSPI can have devices of size > 512MB. In qspi driver we are trying to read all the data at once using DMA. The DMA descriptor destination size is only 29bits long. QSPIDMA_DST_SIZE 0xFF0F0804 BITS: 1:0 Reserved to keep word alignment BITS: 28:2 Number of 4-byte words the DMA will transfer BITS: 31:29 Reserved: Returns 0 when read, writes ignored So we can only transfer data of 0x1FFFFFF0(512MB minus 4bytes) bytes. Anything above will overflow this register and will ignore higher bits above 29 bits. Change the DMA functionality if the requested size is greater than or equal to 512MB to read 256MB chunks. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20220825125906.11581-5-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13spi: zynqmp_gqspi: Add support for IO modeAshok Reddy Soma
Add support for io-mode transfers. This is necessary for UBIFS to work properly with spi-nor devices. The driver will work in IO mode when "has-io-mode" is passed from device tree instead of DMA. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20220825125906.11581-4-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13arm64: versal: Define zynqmp_mmio_write() for versalMichal Simek
GQSPI driver is using it but this function is never called for Versal because it is removed by linker. But function should be declared to avoid this build warning: drivers/spi/zynqmp_gqspi.c: In function 'zynqmp_qspi_set_tapdelay': drivers/spi/zynqmp_gqspi.c:378:3: warning: implicit declaration of function 'zynqmp_mmio_write' [-Wimplicit-function-declaration] 378 | zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20220825125906.11581-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13spi: zynqmp_gqspi: Add tap delays for VersalAshok Reddy Soma
Add tap delays for Versal platform and re-align the tapdelays code. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20220825125906.11581-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13spi: cadence-qspi: Use priv instead of plat across the driverAshok Reddy Soma
As per driver model we should enumerate plat structure only in of_to_plat() and should be used only in probe(). Copy required plat structure info into priv structure in probe() and use priv structure across the driver. So replace plat with priv structure across the driver. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220824113847.7482-4-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13spi: cadence_qspi: Call read_setup for STIG_READAshok Reddy Soma
In cadence_spi_read_id we are using STIG mode to read flash id's. Call cadence_qspi_apb_command_read_setup() to setup cmd, addr and data bus width properly before cadence_qspi_apb_command_read(). Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220824113847.7482-3-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13spi: cadence-qspi: Correct flash reset function nameAshok Reddy Soma
In cadence_spi_probe, cadence_qspi_versal_flash_reset() is called to reset the flash device. Looks like there is a mistake in previous series of patches where it is defined as cadence_spi_versal_flash_reset() but called as cadence_qspi_versal_flash_reset. Since there is a weak function defined with the same name this issue was not caught. Fix the issue by renaming cadence_spi_versal_flash_reset as cadence_qspi_versal_flash_reset(). Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220824113847.7482-2-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13microblaze: add arch_print_bdinfo() implementationOvidiu Panait
Allow bdinfo command to print icache/dcache information: U-Boot-mONStR> bdinfo boot_params = 0x00000000 DRAM bank = 0x00000000 -> start = 0x04000000 -> size = 0x04000000 flashstart = 0x00000000 flashsize = 0x00000000 flashoffset = 0x00000000 baudrate = 9600 bps relocaddr = 0x07f76000 reloc off = 0x02f76000 Build = 32-bit current eth = unknown ethaddr = (not set) IP addr = <NULL> fdt_blob = 0x07fec7e0 new_fdt = 0x00000000 fdt_size = 0x00000000 lmb_dump_all: memory.cnt = 0x1 memory[0] [0x4000000-0x7ffffff], 0x04000000 bytes flags: 0 reserved.cnt = 0x1 reserved[0] [0x7e94b8c-0x7ffffff], 0x0016b474 bytes flags: 0 devicetree = embed icache = 32 KiB icache line = 4 Bytes dcache = 32 KiB dcache line = 4 Bytes Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220829170205.1274484-4-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13cmd: bdinfo: introduce bdinfo_print_size() helperOvidiu Panait
Add bdinfo_print_size() helper to display size variables (such as cache sizes) in bdinfo format. The size is printed as "xxx Bytes", "xxx KiB", "xxx MiB", "xxx GiB", etc as needed; Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Reviewed-by: Jason Liu <jason.hui.liu@nxp.com> Link: https://lore.kernel.org/r/20220829170205.1274484-3-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13cpu: microblaze: add error handling in microblaze_cpu_get_desc()Ovidiu Panait
Check snprintf() return value for errors. Make microblaze_cpu_get_desc() directly return snprintf() error code if ret < 0. Otherwise, if the return value is greater than or equal to size, the resulting string is truncated, so return -ENOSPC. Fixes: 816226d27e ("cpu: add CPU driver for microblaze") Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220829170205.1274484-2-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13microblaze: drop CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZEOvidiu Panait
These macros are not used anymore in microblaze code since commit f113d7d303467 ("Convert CONFIG_SPL_STACK to Kconfig"), so remove them. Fixes: f113d7d303467 ("Convert CONFIG_SPL_STACK to Kconfig") Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220829170205.1274484-1-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13net: gem: Check rate before setting it upMichal Simek
On QEMU setting rate for fixed clock is failing. That's why check a rate first if the rate is the same there is no need to ask for the change. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/bc465ffd4904bfd65208b782daa06732b915db54.1661502645.git.michal.simek@amd.com
2022-09-13xilinx: versal: Disable LMB for mini configurationsMichal Simek
There shouldn't be a reason to have LMB on for these configurations. LMB was already disabled for ZynqMP by commit 0063487a5b60 ("configs: zynqmp: Disable LMB for mini u-boot"). Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/17d1e9b50b2fd032352911f94f4f213828e0a3f7.1662460892.git.michal.simek@amd.com
2022-09-13arm64: xilinx: Move board_get_usable_ram_top() to common locationMichal Simek
The commit ce39ee28ec31 ("zynqmp: Do not place u-boot to reserved memory location") adds functionality for ZynqMP to read reserved memory node and do not place U-Boot to reserved location. This functionality is generic across all Xilinx SOCs that's why move it to common location to be used by all Xilinx SOCs. On zynq platform this is also fixing issue where U-Boot was placed to locating which was reserved already which ends up with error message "ERROR: reserving fdt memory region failed (addr=30000000 size=10000000 flags=4)" which is shown when bdinfo is called. Tested on vck190, zcu102, zc706 and kc705 to cover all platforms. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/b0817807912f7c7af6a8e1cf9ee04e5ab5de5f6a.1661430188.git.michal.simek@amd.com
2022-09-13ARM: zynq: Align bss and end of u-boot image to 64bitsMichal Simek
The main reason is that DT memory reserved code is expecting DT to be 64bit aligned. For more information take a look at commit 5bd5ee02b23b ("xilinx: zynqmp: Check that DT is 64bit aligned"). Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/9f3688cda188d8ea0b462df2aa08a10ddcc9c149.1661938136.git.michal.simek@amd.com
2022-09-13xilinx: Enable CMD_GREPENV/SETEXPR by defaultMichal Simek
Enable both of these commands in Xilinx SoCs to be able to use them in boot scripts. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1a612be7e09e9bc502f30e1f025441ccf8accba5.1661340513.git.michal.simek@amd.com
2022-09-13xilinx: Add env redund offsetT Karthik Reddy
ENV_OFFSET_REDUND config is by default set to 0 for flashes. Saving the env variables is overwriting data at 0 offset, which is wrong. So add default redund env offset for Zynq, ZynqMP, Versal and microblaze platforms. Configured ENV_OFFSET_REDUND offsets by ENV_OFFSET + (2 * ENV_SIZE). In case of versal, we configured ENV_OFFSET_REDUND at 0x7F00000 instead of 0x7F80000. As BOOT_SCRIPT_OFFSET is already configured at 0x7F80000. Added ENV_OFFSET_REDUND in Kconfig for microblaze due to dependency of ENV_IS_IN_SPI_FLASH config. Below table specifies platform specific env and env redund offsets. PLAT ENV_OFFSET ENV_OFFSET_REDUND ---- ---------- ----------------- ZYNQ 0xE0000 0xE40000 ZYNQMP 0x1E00000 0x1E80000 VERSAL 0x7F40000 0x7F00000 MICROBLAZE 0x1080000 0x10C0000 Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/92656dc08f0f5a749d62b71ca6e77fe1be72e9e0.1661340204.git.michal.simek@amd.com
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