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if we have no NAND-Chip, we don't need the gpmc-controller and therefore
is no need to init it.
Cc: trini@ti.com
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
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Cc: trini@ti.com
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
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Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
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For usage of timer6 within B&R we need this defines to enable clock
modules and clk-source.
Also the 'Timer register bits' are expanded.
By the way we add defines for all timers within AM335x SoC.
Cc: trini@ti.com
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
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After enabling a module, SW has to wait on IDLEST bit
until it is Fully functional. This wait is missing for UART module
and there is a immediate access of UART registers after this. So there
is a chance of hang on this module( This can happen when we are running
from MPU SRAM). So waiting for IDLEST bit.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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loadbootenv expects devtype variable to be set. This is missing in
mmcboot command. With this the following error comes:
U-Boot# run mmcboot
mmc0 is current device
SD/MMC found on device 0
** Bad device usb 0 **
** Bad device usb 0 **
Fixing this by setting devtype as mmc.
Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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commit a0a37183bd7 "ARM: omap: merge GPMC initialization code for
all platform" needs CONFIG_NOR, CONFIG_NAND or CONFIG_CMD_ONENAND
to be set to access flash. Add CONFIG_NAND for tam3517 derived
boards to prevent the following error: "nand: error: Unable to
find NAND settings in GPMC Configuration - quitting"
cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
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Enable support of nand ecclayout command.
Acked-By: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
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Currently PWREMU_MGMT is not configured in the Linux generic UART
driver as this register seems to be specific TI UART IP. So this
needs to be enabled in u-boot to use UART1 from kernel space.
Acked-By: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
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With the changes to the i2c framework (and adopting the omap24xx_i2c
driver to them) we can no longer call i2c functions prior to gd having
been set and cleared. When SPL booting, this is handled by setting gd
to point to SRAM in s_init. However in the cases where we are loaded
directly by ROM (memory mapped NOR or QSPI) we need to make use of the
normal hooks to slightly delay these calls.
Signed-off-by: Tom Rini <trini@ti.com>
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We have two contexts for booting these platforms. One is SPL which is
roughly: reset, cpu_init_crit, lowlevel_init, s_init, sdram_init, _main,
board_init_f from SPL, ... then U-Boot loads. The other is a
memory-mapped XIP case (NOR or QSPI) where we do not run an SPL. In
this case we go, roughly: reset, cpu_init_crit, lowlevel_init, s_init,
_main, regular board_init_f.
In the first case s_init will set a valid gd and then be able to call
sdram_init which in many cases will need i2c (which needs a valid gd for
gd->cur_i2c_bus). In this second case we must (and are able to and
should) defer sdram_init() into dram_init() called by board_init_f as gd
will have been set in _main and cleared in board_init_f.
Signed-off-by: Tom Rini <trini@ti.com>
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The patch populates the slave data which will be used by flash driver to
set the flash quad enable bit.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
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The ePOS EVM and EVM SK have QSPI as an option to boot. Add a qspiboot
target that utilizes QSPI for env and so forth as an example of best
practices. As QSPI is booted from directly we need to chang
CONFIG_SYS_TEXT_BASE.
Note that on ePOS EVM the QSPI and NAND are mutually exclusive choices
we need to handle that elsewhere, once NAND support is also added.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
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updates documentation with explanation on how to select ECC schemes.
Signed-off-by: Pekon Gupta <pekon@ti.com>
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This patch add support for BCH16_ECC to omap_gpmc driver.
*need to BCH16 ECC scheme*
With newer SLC Flash technologies and MLC NAND, and large densities, pagesizes
Flash devices have become more suspectible to bit-flips. Thus stronger
ECC schemes are required for protecting the data.
But stronger ECC schemes have come with larger-sized ECC syndromes which require
more space in OOB/Spare. This puts constrains like;
(a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data.
(b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B.
Due to (b) this scheme can only be used with NAND devices which have enough
OOB to satisfy following equation:
OOBsize per page >= 26 * (page-size / 512)
Signed-off-by: Pekon Gupta <pekon@ti.com>
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GPMC can support simultaneous processing of 8 512Byte data chunks, in parallel
Signed-off-by: Pekon Gupta <pekon@ti.com>
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GPMC_NAND_ECC_LP_x16_LAYOUT
OMAP3 used GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT macros
to configure GPMC controller for x7 or x8 bit device connected to its interface.
Now this information is encoded in CONFIG_SYS_NAND_DEVICE_WIDTH macro, so above
macros can be completely removed.
Signed-off-by: Pekon Gupta <pekon@ti.com>
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bus-width
GPMC controller needs to be configured based on bus-width of the NAND device
connected to it. Also, dynamic detection of NAND bus-width from on-chip ONFI
parameters is not possible in following situations:
SPL: SPL NAND drivers does not support ONFI parameter reading.
U-boot: GPMC controller iniitalization is done in omap_gpmc.c:board_nand_init()
which is called before probing for devices, hence any ONFI parameter
information is not available during GPMC initialization.
Thus, OMAP NAND driver expected board developers to explicitely write GPMC
configurations specific to NAND device attached on board in board files itself.
But this was troublesome for board manufacturers as they need to dive into
lengthy platform & SoC documents to find details of GPMC registers and
appropriate configurations to get NAND device working.
This patch instead adds existing CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config
hich indicates that connected NAND device has x16 bus-width. And then based on
this config GPMC driver itself initializes itself based on NAND bus-width. This
keeps board developers free from knowing GPMC controller specific internals.
Signed-off-by: Pekon Gupta <pekon@ti.com>
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As per following Sections in ONFI Spec, GET_FEATURES and SET_FEATURES also need
byte-addressing on 16-bit devices.
*Section: Target Initialization"
"The Read ID and Read Parameter Page commands only use the lower 8-bits of the
data bus. The host shall not issue commands that use a word data width on x16
devices until the host determines the device supports a 16-bit data bus width
in the parameter page."
*Section: Bus Width Requirements*
"When the host supports a 16-bit bus width, only data is transferred at the
16-bit width. All address and command line transfers shall use only the lower
8-bits of the data bus. During command transfers, the host may place any value
on the upper 8-bits of the data bus. During address transfers, the host shall
set the upper 8-bits of the data bus to 00h."
So porting following commit from linux kernel
commit e34fcb07a6d57411de6e15a47724fbe92c5caa42
Author: David Mosberger <davidm@egauge.net> (preserving authorship)
mtd: nand: fix GET/SET_FEATURES address on 16-bit devices
Signed-off-by: Pekon Gupta <pekon@ti.com>
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As per following Sections in ONFI Spec, NAND_CMD_READID should use only
lower 8-bit for transfering command, address and data even on x16 NAND device.
*Section: Target Initialization"
"The Read ID and Read Parameter Page commands only use the lower 8-bits of the
data bus. The host shall not issue commands that use a word data width on x16
devices until the host determines the device supports a 16-bit data bus width
in the parameter page."
*Section: Bus Width Requirements*
"When the host supports a 16-bit bus width, only data is transferred at the
16-bit width. All address and command line transfers shall use only the lower
8-bits of the data bus. During command transfers, the host may place any value
on the upper 8-bits of the data bus. During address transfers, the host shall
set the upper 8-bits of the data bus to 00h."
Thus porting following commit from linux-kernel to ensure that column address
is not altered to align to x16 bus when issuing NAND_CMD_READID command.
commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7
mtd: nand: force NAND_CMD_READID onto 8-bit bus
Author: Brian Norris <computersforpeace@gmail.com> (preserving authorship)
The NAND command helpers tend to automatically shift the column address
for x16 bus devices, since most commands expect a word address, not a
byte address. The Read ID command, however, expects an 8-bit address
(i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or
0x20).
This fixes the column address for a few drivers which imitate the
nand_base defaults.
Signed-off-by: Pekon Gupta <pekon@ti.com>
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Porting below commit from linux-tree, preserving original authorship & commit log
commit bd9c6e99b58255b9de1982711ac9487c9a2f18be
Author: Brian Norris <computersforpeace@gmail.com>
mtd: nand: don't use read_buf for 8-bit ONFI transfers
Use a repeated read_byte() instead of read_buf(), since for x16 buswidth
devices, we need to avoid the upper I/O[16:9] bits. See the following
commit for reference:
commit 05f7835975dad6b3b517f9e23415985e648fb875 (from linux-tree)
Author: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Date: Thu Dec 5 22:22:04 2013 +0100
mtd: nand: don't use {read,write}_buf for 8-bit transfers
Now, I think that all barriers to probing ONFI on x16 devices are
removed, so remove the check from nand_flash_detect_onfi().
Signed-off-by: Pekon Gupta <pekon@ti.com>
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This patch
omap-elm.c: replaces -ve integer value returned during errorneous condition,
with proper error-codes.
omap-gpmc.c: updates omap-gpmc driver to pass error-codes returned from
omap-elm driver to upper layers
Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
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This patch tries to avoid some local pointer dereferences, by using common
local variables in omap_correct_data_bch()
Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
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This patch renames 'struct nand_bch_priv' which currently holds private data only
for BCH ECC schemes, into 'struct omap_nand_info' so that same can be used for
all ECC schemes
Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
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This patch prepares to refactor 'struct nand_bch_priv' -> 'struct omap_nand_info'
And thus performs following clean-ups:
- remove nand_bch_priv.type: use nand_bch_priv.ecc_scheme instead
- remove nand_bch_priv.mode: <unused>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
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This patch adds macros for following parameters of ELM Hardware engine
- ELM_MAX_CHANNELS: ELM can process 8 data streams simultaneously
- ELM_MAX_ERRORS: ELM can detect upto 16 ECC error when using BCH16 scheme
Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
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between BCH4/BCH8/BCH16
ELM hardware engine support ECC error detection for multiple ECC strengths like
+------+------------------------+
|Type | ECC syndrome length |
+------+------------------------+
|BCH4 | 6.5 bytes = 13 nibbles |
|BCH8 | 13 byte = 26 nibbles |
|BCH16 | 26 bytes = 52 nibbles |
+------+------------------------+
Current implementation of omap_elm driver uses ECC syndrom length (in 'nibbles')
to differentiate between BCH4/BCH8/BCH16. This patch replaces it with 'bch_type'
Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
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There is no dependency of omap_elm.c on omap_gpmc.h
Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
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When the map_sysmem, then the fatwrite command can support sandbox.
Following command will show how to use it:
=> sb bind 0 sd.img
=> fatls host 0
=> fatwrite host 0 $memaddr filename $filesize
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Simon Glass <sjg@chromium.org>
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The tools mkimage, dumpimage, fit_info, fit_check_sign
always have the common libraries to be linked,
so HOSTLOADLIBES_* can be consolidated a little bit.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Remove the common infrastructure of nand_spl and
clean-up the code inside ifdef(CONFIG_NAND_U_BOOT)..endif.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Commit 3d5a335c announced that all the nand_spl boards
would be removed before v2014.07 release.
Also update README.scrapyard.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Commit 3d5a335c announced that all the nand_spl boards
would be removed before v2014.07 release.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Commit 3d5a335c announced that all the nand_spl boards
would be removed before v2014.07 release.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Commit 3d5a335c announced that all the nand_spl boards
would be removed before v2014.07 release.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Commit 3d5a335c announced that all the nand_spl boards
would be removed before v2014.07 release.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Commit 3d5a335c announced that all the nand_spl boards
would be removed before v2014.07 release.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Because cmd_mkimage is used in various subdirectories,
it seems reasonable to define it in scripts/Makefile.lib.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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We already have cmd_shipped in scripts/Makefile.lib.
Use it rather than defining a new command cmd_copy.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Emails to the following addresses have been bouncing.
Albin Tonnerre <albin.tonnerre@free-electrons.com>
Anton Shurpin <shurpin.aa@niistt.ru>
Brent Kandetzki <brentk@teleco.com>
Dan Malek <dan@embeddedalley.com>
Frank Panno <fpanno@delphintech.com>
Gary Jennejohn <garyj@denx.de>
Hayden Fraser <Hayden.Fraser@freescale.com>
Eric Millbrandt <emillbrandt@dekaresearch.com>
Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
Kumar Gala <kumar.gala@freescale.com>
Joe D'Abbraccio <ljd015@freescale.com>
John Zhan <zhanz@sinovee.com>
Keith Outwater <Keith_Outwater@mvis.com>
Julien May <julien.may@miromico.ch>
Kári Davíðsson <kd@flaga.is>
Kyle Moffett <Kyle.D.Moffett@boeing.com>
Leo Sartre <lsartre@adeneo-embedded.com>
Mike Dunn <mikedunn@newsguy.com>
Dave Ellis <DGE@sixnetio.com>
Chan-Taek Park <c-park@ti.com>
Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
I am Ccing the current working addresses for some of them.
If you want to get back an Orphan board to Active,
please update your email address.
Please do it only if you still have a real hardware to test on.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Albin Tonnerre <albin.tonnerre@gmail.com>
Cc: Anton Shurpin <anton.shurpin@gmail.com>
Cc: Brent Kandetzki <brent.kandetzki@stw-technic.com>
Cc: Dan Malek <dan.malek@konsulko.com>
Cc: Gary Jennejohn <gljennjohn@googlemail.com>
Cc: Haavard Skinnemoen <haavard.skinnemoen@gmail.com> ?
Cc: Hans-Christian Egtvedt <egtvedt@samfundet.no>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Mike Dunn <mikedunn@newsguy.com>
CC: Jerry Van Baren <vanbaren@cideas.com>
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Due to the FIT_MAX_HASH_LEN constant not having been updated
to support SHA256 signatures one will always see a buffer
overflow in fit_image_process_hash when signing images that
use this larger hash. This is exposed by vboot_test.sh.
Signed-off-by: Michael van der Westhuizen <michael@smart-africa.com>
Acked-by: Simon Glass <sjg@chromium.org>
[trini: Rework a bit so move the exportable parts of hash.h outside of
!USE_HOSTCC and only need that as a new include to image.h]
Signed-off-by: Tom Rini <trini@ti.com>
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The offset of module information is at 128, different from DDR3.
Signed-off-by: York Sun <yorksun@freescale.com>
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This is a workaround for 32 bit hardware limitation of TDM.
T1040 has 36 bit physical addressing, TDM DMAC register
are 32 bit wide but need to store address of CCSR space
which lies beyond 32 bit address range. This workaround
creats a LAW to enable access of TDM DMA to CCSR by
mapping CCSR to overlap with DDR.
A hole of 16M is created in memory using device tree. This
workaround law is set only if "tdm" is defined in hwconfig.
Also disable POST tests and add LIODN for TDM
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Crossbars and IDT were not getting configured for Serdes2 protocol
0x9d for B4420.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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SerDes PLL is calibrated at reset. When the junction temperature
delta from the time the PLL is calibrated exceeds +56C/-66C,
jitter may increase and can cause PLL to unlock.
This workaround overwrite the SerDes registers with new values,
to calibrate SerDes registers.
These values are known to work fine for all temperature ranges.
This workaround is valid for B4, T4 and T2 platforms, so
added in their config.
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
[York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs]
Reviewed-by: York Sun <yorksun@freescale.com>
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When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun <yorksun@freescale.com>
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Add a new serdes2 protocol 0x27.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Replace 80 mircoseconds delay with polling flag ESPI_EV_TXE.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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A-007186: SerDes PLL is calibrated at reset. It is possible
for jitter to increase and cause the PLL to unlock when the
temperature delta from the time the PLL is calibrated exceeds
+56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using
XnVDD of 1.5 V). No issues are seen with LC VCO. The protocols
only using Ring VCOs are impacted.
Workaround:
For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring
VCO, this need to use alternate serdes protocols. Alternate
option has the same functionality as the original option; the
only difference being LC VCO rather than Ring VCO.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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