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2022-02-05tools/mxsimage: Remove fclose on empty FILE pointerMattias Hansson
If `sb_load_cmdfile()` fails to open the configuration file it will jump to error handling where the code will try to `fclose()` the FILE pointer which is NULL causing `mkimage` to segfault. This patch removes the label for error handling and instead returns immediately which skips the `fclose()` and prevents the segfault. The errno is also described in the error message to guide users. Signed-off-by: Mattias Hansson <hansson.mattias@gmail.com> Reviewed-by: Wolfgang Denk <wd@denx.de>
2022-02-05imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO boardAriel D'Alessandro
Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for: - 1GiB DDR4 RAM - 16 GiB eMMC - SD card - Gigabit ethernet - USBOTG1 peripheral - fastboot Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05colibri-imx8x: add on-module gpio expander fxl6408Oleksandr Suvorov
The FXL6408 GPIO expander manages critical devices, including on-module USB hub. Configure the expander to switch the USB hub into bypass mode, allowing to use on-carrier-board USB hub. Signed-off-by: Oleksandr Suvorov <cryosay@gmail.com> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2022-02-05GPIO: fxl6408: Add support for FXL6408 GPIO expanderOleksandr Suvorov
Initial support for Fairchild's 8 bit I2C gpio expander FXL6408. The CONFIG_FXL6408_GPIO define enables support for such devices. Based on: https://patchwork.kernel.org/patch/9148419/ Signed-off-by: Oleksandr Suvorov <cryosay@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2022-02-05imx8mm-cl-iot-gate-optee: add CONFIG_SPL_MMC and CONFIG_SPL_SERIALYing-Chun Liu (PaulLiu)
Previously these two options are called CONFIG_SPL_MMC_SUPPORT and CONFIG_SPL_SERIAL_SUPPORT. During the transition they are removed by accident. Thus adding them back. Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: uboot-imx <uboot-imx@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05spi: mxc_spi: remove redundant code in spi_xchg_single()Haolin Li
The value of cnt is overwritten without being used. Signed-off-by: Haolin Li <li.haolin@qq.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05arm: imx8m: imx8mm-cl-iot-gate: detect extension boardYing-Chun Liu (PaulLiu)
Extension boards can be added to Compulab's iot-gate-imx8mm. We implement extension board manager for detecting the extension boards. Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: uboot-imx <uboot-imx@nxp.com>
2022-02-05arm: dts: imx8mm-cl-iot-gate: add Compulab's ied overlaysYing-Chun Liu (PaulLiu)
add the following overlays: - IED extension board - CAN/TPM/ADC extension board on IED board. Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: uboot-imx <uboot-imx@nxp.com>
2022-02-05imx8ulp: ddr: Fix DDR frequency request issueYe Li
After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp:ddr: saving the dram config timing data into sramJacky Bai
On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: implement to obtain the SoC current temperatureAlice Guo
Obatin the SoC current temperature in print_cpuinfo(). Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: clock: Handle the DDRLOCKED when setting DDR clockYe Li
The DDRLOCKED bit in CGC2 DDRCLK will auto lock up and down by HW according to DDR DIV updating or DDR CLK halt status change. So DDR PCC disable/enable will trigger the lock up/down flow. We need wait until unlock to ensure clock is ready. And before configuring the DDRCLK DIV, we need polling the DDRLOCKED until it is unlocked. Otherwise writing ti DIV bits will not set. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: clock: Support to enable/disable the ADC1 clockAlice Guo
This patch implements enable_adc1_clk() to enable or disable the ADC1 clock on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: Update ethernet mac to get from fuseYe Li
Get the MAC address from fuse bank5 word 3 and 4. It has MSB first at lowest address, so have a reverse order with other iMX used in mac.c Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: clock: Support to reset DCNano and MIPI DSIYe Li
When LPAV is allocated to RTD, the LPAV won't be reset. So we have to reset DCNano and MIPI DSI in u-boot before enabling the drivers Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: clock: Reset DDR controller before clock enableYe Li
The LPAV is not allocated to APD when dual boot, so LPAV won't reset when APD is reset. We have to explicitly reset the DDR, otherwise its initialization will fail. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: Workaround LPOSC_TRIM fuse load issueYe Li
8ULP ROM should read the LPOSC trim BIAS fuse to fill the CGC0 LPOSCCTRL[7:0], but it writes a fixed value on A0.1 revision. A0.2 will fix the issue in ROM. But A0.1 we have to workaround it in SPL by setting LPOSCCTRL BIASCURRENT again. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: Remove freescale name from CPU revisionYe Li
Remove the freescale vendor name from CPU revision print to align with other i.MX platforms Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: Fix DCNANO QoS settingYe Li
The setting does not have effect because we should set it after power on the PS16 for NIC AV. So move it after upower_init which has powered on all PS Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: Set DCNANO read QoS on NIC_LPAV to highestYe Li
To avoid DCNANO underrun issue on high loading test, set its read Qos on NIC_LPAV to highest Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp_evk: Control LPI2C0 PCA6416 and TPM0 for displayYe Li
The board use IO9 of PCA6416 on LPI2C0 and TPM0 for MIPI DSI MUX and backlight. However the LPI2C0 and TPM0 are M33 resources, in this patch we simply access them, but this is a temporary solution. We will modify it when M33 FW changes to set MIPI DSI panel as default path and enable backlight after reset. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: rdc: allow A35 access flexspi0 memYe Li
For singel boot, set flexspi0 mem to be accessed by A35 Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: clock: Add MIPI DSI clock and DCNano clockYe Li
Add the DSI clock enable and disable with PCC reset used. Add the LCD pixel clock calculation and configuration for DCNano Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: clock: Support LPAV clocks in cgc and pccYe Li
Add the PCC5 clocks support and more LPAV clocks and PLL4 PFD in CGC. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: assign PXP/HIFI4/EPDC to APD domainPeng Fan
Assign the PXP/HIFI4/EPDC to APD domain, otherwise APD not able to receive interrupts from the modules. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05arm: imx8ulp: Allocate LPAV resources to AP domainYe Li
When single boot, assign AP domain as the master domain of the LPAV. Allocates LPAV master and slave resources like GPU, DCNano, MIPI-DSI eDMA channel and eDMA request to APD Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: soc: Check the DBD_EN fuse before setting RDCYe Li
S400 enables RDC only when the DBD_EN is fused. Otherwise, the RDC is allowed by all masters. Current S400 has issue if the XRDC has released to A35, then A35 reset will fail in ROM due to S400 fails to get XRDC. So temp work around is checking the DBD_EN, if it is not fused, we don't need to call release XRDC or TRDC. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05ARM: imx8m: support env in fat and ext4Ricardo Salveti
Change boot device logic to also allow environment stored in fat and in ext4 when booting from SD or from eMMC. As the boot device check for SD and for eMMC was depending on ENV_IS_IN_MMC being defined, change the ifdef blocks at env_get_location to use IS_ENABLED instead for all modes, returning NOWHERE when no valid mode is found. Signed-off-by: Ricardo Salveti <ricardo@foundries.io> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05imx: nandbcb: Fix printf format in write_fcbPali Rohár
Correct printf format for unsigned long long is %llx and not %llxx. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05mxs: power: Change sequence of enabling DCDC switchesLukasz Majewski
The imx28 uses following voltage supplies hierarchy: VDD_5V (VDD_BAT) -> VDDIO -> VDDA -> VDDMEM \-----> VDDD One shall first enable DCDC on the parent source (VDDIO) and then follow with its children. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05imx8mm-venice-gw7902: fix M2_RST# gpio pinmuxTim Harvey
Fix the invalid gw7902 M2_RST# gpio pinmux. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05mx7ulp_com: add support for SPLRicardo Salveti
Add EA iMX7ULP COM board support for building SPL. Signed-off-by: Ricardo Salveti <ricardo@foundries.io> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2022-02-05mx7ulp: select soc featuresOleksandr Suvorov
Force selecting features present in SoC i.MX7ULP. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2022-02-05arm: imx: imx8mq: add support to get values for more clocksHeiko Thiery
Return the root clock values for MXC_CSPI_CLK, MXC_I2C_CLK, MXC_UART_CLK and MXC_QSPI_CLK. At least for the I2C clock the missing support leads to a wrong configured I2C frequency. The expected value is 100kHz but the resulting value is about 1MHz. Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05colibri-imx7: improve env badblock managementFrancesco Dolcini
Use the complete 512kb (4 blocks) nand partition reserved for u-boot environment instead of just the first block, this allows the module to have a working environment even if 3 blocks are bad. Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2022-02-03Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
This is the promised second part of the sunxi PR for 2022.04, albeit technially outside of the merge window. We were working on this full steam since the beginning of the year, and it deserves to be merged, I think. The main attraction is support for the F1C100s SoC, which sports a venerable ARM926 core. Support for this SoC and the LicheePi Nano board has been in Linux for years, and U-Boot patches were posted mid last year already. The new SoC using ARMv5 also means that the bulk of the new code should not touch any existing boards, although we did some refactorings first, of course, which actually cleans up some existing sunxi code. Compile tested for all 160 sunxi boards, and briefly tested on BananaPi M1, OrangePi Zero, Pine64 and Pine-H64. Tested by others on their boards, including F1C100s and F1C200s devices.
2022-02-04configs: sunxi: Add support for Lichee Pi NanoIcenowy Zheng
The Lichee Pi Nano is a board based on the F1C100s. Add defconfigs for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04ARM: dts: suniv: Add device tree files and bindings for F1C100sIcenowy Zheng
Add device tree files for suniv and Lichee Pi Nano it is a board based on F1C100s. dt-bindings/dts are synced with 5.16.0 Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04mach-sunxi: Add support for SUNIV architectureIcenowy Zheng
Add support for the suniv architecture, which is newer ARM9 SoCs by Allwinner. The design of it seems to be a mixture of sun3i, sun4i and sun6i. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04configs: sunxi: Add common SUNIV headerIcenowy Zheng
Adds support for SUNIV and the F1C100s. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04sunxi: board: Add support for SUNIVIcenowy Zheng
Generic Timer Extension is not available on SUNIV. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04sunxi: Add F1C100s DRAM initial supportIcenowy Zheng
Add support for F1C100s internal dram controller. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04ARM: sunxi: Add clock and uart to sunxi headersIcenowy Zheng
This patch aims to add header files for the suniv. The header files included add support for uart, and clocks. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04arm: arm926ej-s: Add sunxi codeIcenowy Zheng
Some Allwinner SoCs use ARM926EJ-S core. Add Allwinner/sunXi specific code to ARM926EJ-S CPU dircetory. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04mach-sunxi: Move timer code to mach folderJesse Taube
Both armv7 and arm926ejs use this timer code so move it to mach-sunxi. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04arm: arm926ej-s: start.S: port save_boot_params support from armv7 codeIcenowy Zheng
The ARMv7 start code has support for saving some boot params at the entry point, which is used by some SoCs to return to BROM. Port this to ARM926EJ-S start code. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04sunxi-common.h: remove pointless #ifdefsAndre Przywara
Remove some pointless #ifdefs from this file, as there are quite too many of them already. Some definitions don't really hurt to have in any case, so remove the pointless CONFIG_MMC guard around CONFIG_MMC_SUNXI_SLOT. The BOARD_SIZE_LIMIT applies regardless of ARM64 or not (now), so remove that guard as well. The maximum number of MMC devices does not depend on CONFIG_ENV_IS_IN_MMC, so move that out to simplify the file. Last but not least CONFIG_SPL_BOARD_LOAD_IMAGE serves no real purpose anymore: it's unconditionally defined for all sunxi boards, and protects nothing applicable outside of sunxi code anymore. Just remove it. Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04armv8: remove no longer needed lowlevel_init.SAndre Przywara
When we added Allwinner SoC support to ARMv8, we needed to pull in an implementation of lowlevel_init() calling the C function s_init(), as sunxi required it as this time. The last few patches got rid of this bogus requirement, and as sunxi was still the only user, we can now remove this lowlevel_init.S from ARMv8 altogether. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2022-02-04sunxi: move early "SRAM setup" into separate fileAndre Przywara
Currently we do some magic "SRAM setup" MMIO writes in s_init(), copied from the original BSP U-Boot. The comment speaks of this being required before DRAM access gets enabled, but there is no indication that this would actually be required that early. Move this out of s_init(), into board_init_f(). Since this actually only affects a very few older SoCs, the actual code goes into the cpu/armv7 directory, to move it out of the way for all other SoCs. This also uses the opportunity to convert some #ifdefs over to the fancy IS_ENABLED() macros used in actual C code. We keep the s_init() stub around for now, since armv8's lowlevel_init still relies on it. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2022-02-04sunxi: move Cortex SMPEN setting into start.SAndre Przywara
According to their TRMs, Cortex ARMv7 CPUs with SMP support require the ACTLR.SMPEN bit to be set as early as possible, before any cache or TLB maintenance operations are done. As we do those things still in start.S, we need to move the SMPEN bit setting there, too. This introduces a new ARMv7 wide symbol and code to set bit 6 in ACTLR very early in start.S, and moves sunxi boards over to use that instead of the custom code we had in our board.c file (where it was called technically too late). In practice we got away with this so far, because at this point all the other cores were still in reset, so any broadcasting would have been ignored anyway. But it is architecturally cleaner to do it early, and we move a core specific piece of code out of board.c. This also gets rid of the ARM_CORTEX_CPU_IS_UP kludge I introduced a few years back, and moves the respective logic into the new Kconfig entry. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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