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2019-04-23ARM: meson: add G12a supportJerome Brunet
Add support for the Amlogic G12A SoC, which is a mix between the new physical memory mapping of AXG and the functionnalities of the previous Amlogic GXL/GXM SoCs. To handle the internal ethernet PHY, the Amlogic G12A SoCs now embeds a dedicated PLL to feed the internal PHY. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-23clk: meson: add g12a supportJerome Brunet
Add basic support for the Amlogic G12A clock controller based on the AXG driver. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-03-15armv7: ls102xa: Add workaround for DDR erratum A-008850Alison Wang
Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03armv8: fsl-layerscape: avoid DT fixup warningLaurentiu Tudor
sec_firmware reserves JR3 for it's own usage and deletes the JR3 node from the device tree. This causes this warning to be issued when doing the device tree fixup: WARNING could not find node fsl,sec-v4.0-job-ring: FDT_ERR_NOTFOUND. Fix it by excluding the device tree fixup for the JR reserved by sec_firmware. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03armv8: fsl-layerscape: fix SEC QI ICID setupLaurentiu Tudor
The SEC QI ICID setup in the QIIC_LS register is actually an offset that is being added to the ICID coming from the qman portal. Setting it with a non-zero value breaks SMMU setup as the resulting ICID is not known. On top of that, the SEC QI ICID must match the qman portal ICIDs in order to share the isolation context. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8: layerscape: move TZASC and TZPC configs to KconfigRajesh Bhagat
Moves FSL_TZASC_400 and FSL_TZPC_BP147 configs to Kconfig for LS1088A and LS2088A platforms. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19lx2160aqds : Add support for LX2160AQDS platformPankaj Bansal
LX2160AQDS is a development board that supports LX2160A family SoCs. This patch add base support for this board. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> [PK: Sqaush patch for "secure boot defconfig" & add maintainer] Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8: lx2160a: Update CONFIG_SYS_FSL_PEBUF_BASEPriyanka Jain
As per hardware documentation, CONFIG_SYS_FSL_PEBUF_BASE for lx2160a is 0x1c00000000 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-15usb: Rename SPL_USB_SUPPORT to SPL_USB_STORAGEAbel Vesa
Since there is the SPL_USB_HOST_SUPPORT for enabling USB support in SPL, makes more sense to rename the SPL_USB_SUPPORT as SPL_USB_STORAGE. Everything that is not part of the usb storage support in SPL is now build under SPL_USB_HOST_SUPPORT. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-15ddr: vybrid: Add DDRMC calibration related registers (DQS to DQ)Lukasz Majewski
This commit provides extra defines needed for DDR memory controller calibration (read leveling performing). Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
2019-02-01rockchip: Add support for chromebook_bobSimon Glass
Bob is a 10-inch chromebook produced by Asus. It has two USB 3.0 type-C ports, 4GB of SDRAM, WiFi and a 1280x800 display. It uses its USB ports for both power and external display. It includes a Chrome OS EC (Cortex-M3) to provide access to the keyboard and battery functions. Support so far includes only: - UART - SDRAM - MMC, SD card - Cros EC (but not keyboard) Not included: - Keyboard - Display - Sound - USB - TPM Bob is quite similar to Kevin, the Samsung Chromebook Plus, but support for this is not provided in this series. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01rockchip: Implement spl_gpio in the GPIO driverSimon Glass
Allow rockchip boards to use GPIOs before driver model is ready. This is really only useful for setting GPIOs to enable the early debug console, if needed on some platforms. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01rockchip: Move pull-up/down enum into a common fileSimon Glass
At present this enum is only available to rk3288. Move it so that other rockchip SoCs can access it. It is needed for the SPL GPIO driver for rk3999 in a later patch. Also adjust the enum name to lower case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01rockchip: rk3288: Add i2s pinctrl and clock supportSimon Glass
Add support for setting pinctrl and clock for I2S on rk3288. This allows the sound driver to operate. These settings were created by rkmux.py Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-31video: Add Meson Video Processing Unit DriverNeil Armstrong
This adds video output support for Amlogic GXBB/GXL/GXM chips. The supported ports are CVBS and HDMI (based on DW_HDMI). When using HDMI, only DMT modes are supported. There is support for simple-framebuffer (CONFIG_VIDEO_DT_SIMPLEFB) Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jorge Ramire-Ortiz <jramirez@baylibre.com> Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com> [narmstrong: fixed defines alignment in meson_canvas.c] Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-30Merge tag 'u-boot-imx-20190129' of git://git.denx.de/u-boot-imxTom Rini
For 2019.04
2019-01-28imx: Check the PL310 version for applying errataYe Li
Apply errata based on PL310 version instead of compile time. Also set Prefetch offset to 15, since it improves memcpy performance by 35%. Don't enable Incr double Linefill enable since it adversely affects memcpy performance by about 32MB/s and reads by 90MB/s. Tested with 4K to 16MB sized src and dst aligned buffer. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ye Li <ye.li@nxp.com>
2019-01-28ARM: imx: fix: Provide correct enum values for ONENAND/NOR boot recognitionLukasz Majewski
According to "Table 5-1. Boot Device Select" (page 335, i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 4, 09/2017) the BOOT_CFG1[3] have following values (regarding EIM booting): 0 - NOR flash and 1 - ONENAND This commit provides correct identification of the boot medium for IMX6Q boards booting from NOR memory (MCCMON6 is one of them). Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-01-25poplar: clean up board level mmc initialization codeShawn Guo
We have converted mmc to driver model on Poplar. So let's clean up board level mmc initialization code. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-01-24Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
2019-01-24arm64: zynqmp: Move SoC sources to mach-zynqmpMichal Simek
Similar changes was done for Zynq in past and this patch just follow this pattern to separate cpu code from SoC code. Move arch/arm/cpu/armv8/zynqmp/* -> arch/arm/mach-zynqmp/* And also fix references to these files. Based on "ARM: zynq: move SoC sources to mach-zynq" (sha1: 0107f2403669f764ab726d0d404e35bb9447bbcc) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-18Merge tag 'fsl-qoriq-for-v2019.04-rc1' of git://git.denx.de/u-boot-fsl-qoriqTom Rini
Add TFA boot flow for more boards Add TFA boot defconfig for ls1088a and ls2088a. Add dts fixup for PCIe endpoint and root complex.
2019-01-18reset: Add Allwinner RESET driverJagan Teki
Add common reset driver for all Allwinner SoC's. Since CLK and RESET share common DT compatible, it is CLK driver job is to bind the reset driver. So add CLK bind call on respective SoC driver by passing ccu map descriptor so-that reset deassert, deassert operations held based on ccu reset table defined from CLK driver. Select DM_RESET via CLK_SUNXI, this make hidden section of RESET since CLK and RESET share common DT compatible and code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18clk: Add Allwinner A64 CLK driverJagan Teki
Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18sunxi: board: Add i2c initialization for sun50iStefan Mavrodiev
To use TWI0/1/2 the user can select CONFIG_I2C#_ENABLE. However even the controller is enabled, the mux for the pins are not set. This patch follows the existing mux method. Since the pads are different, separate check is added for each i2c. Tested with A64-SOM204 board. Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-17armv8: fsl-layerscape: properly configure qdma ICIDLaurentiu Tudor
The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17armv8: ls1043a: add SVR definitions for 23x23 package siliconHou Zhiqiang
LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-14reset: MedaiTek: add reset controller driver for MediaTek SoCsWeijie Gao
This patch adds reset controller driver for MediaTek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-01-14poplar: add DWC2 OTG gadget supportShawn Guo
It enables DWC2 OTG gadget driver support for Poplar board. As usb2_phy_init() is being always called from board_init(), we can save the call from board_usb_init(). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2019-01-10Merge tag 'u-boot-imx-20190110' of git://git.denx.de/u-boot-imxTom Rini
Fixes for 2019.01
2019-01-09ARM: vf610: ddrmc: fix initialization completion detectionStefan Agner
The CR80 register has multiple interrupt bits, the code is supposed to check bit 8 but instead uses a logical and. In most cases this probably did not affect real operations since at that stage typically none of the other bits are set. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-01-09ARM: vf610: ddrmc: fix CR138 preprocessor defineStefan Agner
According to the data sheet bits 10-8 are PHYDRAM_CK_EN. Fix mask to allow setting PHYDRAM_CK_EN correctly. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-01-09ARM: vf610: ddrmc: program Dummy DDRBYTE1/2Stefan Agner
The Vybrid reference manual VFXXXRM Rev. 0 10/2016 states in chapter 5.2.6.1 DUMMY PADS (DDR/QuadSPI) that those pads need to be programed for correct operation of DDR. Assume the default DDR pin configuration which seems to work well on a Colibri VF50. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2019-01-09arm: Round the dma_alloc_coherent memory size to cache line alignedYe Li
When running usb dwc3 gadget driver, we meet random USB enumeration failure in fastboot. The root cause is a cache coherence issue. When it happens, the ctrl_req in gadget driver is allocated at 0xfe932f40, and the usb_composite_dev (cdev) is allocated at 0xfe932f60. So after we submit the setup request (cache flushed) to USB controller, any accessing to usb_composite_dev variable will cause the cache line refill, then when setup transfer is completed, reading the setup data in ctrl_req will gets old value from cache not from memory. The ctrl_req is allocated by API dma_alloc_coherent, but u-boot don't have cohernet memory. so it still needs cache maintain operations before/after HW accessing. Since the cache flush or invalidate bases on cache line, so when the allocated memory size is not cache line aligned, potentially it may meet such issue. This patch modifies the dma_alloc_coherent API to round the size to cache line aligned. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-01-01Merge tag 'u-boot-imx-20190101' of git://www.denx.de/git/u-boot-imxTom Rini
imx for 2019.01 - introduce support for i.MX8M - fix size limit for Vhybrid / pico boards - several board fixes - w1 driver for MX2x / MX5x
2019-01-01imx8m: ddr: removed unused macrosPeng Fan
Remove unused DDRC register macros. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01drivers: ddr: introduce DDR driver for i.MX8MPeng Fan
Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01imx: imx8m: add lpddr4 header filePeng Fan
Introduce lpddr4 header file Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01imx: imx8m: clock refactor dram pll partPeng Fan
Refactor dram_pll_init to accept args to configure different pll freq. Introduce dram_enable_bypass and dram_disable_bypass Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01imx: rename mx8m,MX8M to imx8m,IMX8MPeng Fan
Rename mx8m,MX8M to imx8m,IMX8M Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jon Nettleton <jon@solid-run.com>
2019-01-01imx: introduce is_imx8mq helperPeng Fan
Introduce is_imx8mq header macro Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01imx: cpu: add CHIP_REV_2_1 macroPeng Fan
Introduce CHIP_REV_2_1 macro. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-12-14usb: musb-new: Add support for DM_USBJean-Jacques Hiblot
Enable DM for USB peripheral in the musb-new driver. Also make sure that the driver can be used in the SPL. This implies that: * the driver must work with and without the OF_CONTROL option. That in turn, implies that the platform data can be passed in a struct ti_musb_platdata or be read from the dtb * usb.o is linked in the SPL if host support is enabled Another change is that the driver does not fail to bind (and stop the boot process) if one of the child driver does not bind. Reporting the error is enough. This kind of error would appear if the port is configured in the DTS but the driver is not activated in the config. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-10Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriqTom Rini
Add TFA boot flow for some Layerscape platforms Add support for lx2160a SoC [trini: Add a bunch of missing MAINTAINERS entries] Signed-off-by: Tom Rini <trini@konsulko.com>
2018-12-10i2c: omap24xx_i2c: Use platdata to probe the deviceJean-Jacques Hiblot
This allows the driver to be used without OF_CONTROL. AM335x support DM_SPL but does not use SPL_OF_CONTROL. Enabling DM_I2C in SPL thus requires that the omap I2C can be passed platdata. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2018-12-10i2c: omap24xx_i2c: Move away from SoC specific headers for reg offsetVignesh R
Move away from SoC specific headers to handle different register layout. Instead use driver data to get appropriate register layouts like in the kernel. While at it, perform some mostly cosmetic alignment/cleanup in the functions being updated. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2018-12-07gpio: stm32f7: Move STM32_GPIOS_PER_BANK into gpio.hPatrice Chotard
To allow access to this define by other driver, move it into gpio.h Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-07gpio: stm32f7: Add gpio bank holes managementPatrice Chotard
In some STM32 SoC packages, GPIO bank has not always 16 gpios. Several cases can occur, gpio hole can be located at the beginning, middle or end of the gpio bank or a combination of these 3 configurations. For that, gpio bindings offer the gpio-ranges DT property which described the gpio bank mapping. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-07arm: implement {in, out}_{16, 32} and {clr, set, clrset}bits_{16, 32}Álvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-06armv8: lx2160a: Add LX2160A SoC SupportPriyanka Jain
LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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