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2023-10-19serial: sh: Add RZ/G2L SCIF supportPaul Barker
Extend the existing driver to support the SCIF serial ports on the Renesas RZ/G2L (R9A07G044) SoC. This also requires us to ensure that if there is a reset signal defined in the device tree, it is de-asserted before we try to talk to the SCIF module. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Tested-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # R-Car H3 Salvator-XS
2023-10-17board: rzg2l: Add RZ/G2L SMARC EVK boardPaul Barker
The Renesas RZ/G2L SMARC Evaluation Board Kit consists of the RZ/G2L System-on-Module (SOM) based on the R9A07G044L2 SoC, and a common SMARC carrier board. The ARM TrustedFirmware code for the Renesas RZ/G2L SoC family passes a devicetree blob to the bootloader as an argument in the same was previous R-Car gen3/gen4 SoCs. This blob contains a compatible string which can be used to identify the particular SoC we are running on and this is used to select the appropriate device tree to load. The configuration renesas_rzg2l_smarc_defconfig is added to support building for this target. In the future this defconfig will be extended to support other SoCs and evaluation boards from the RZ/G2L family. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-17arm: rmobile: Support RZ/G2L memory mapPaul Barker
The memory map for the RZ/G2L family differs from that of previous R-Car Gen3/Gen4 SoCs. A high level memory map can be seen in figure 5.2 (section 5.2.1) of the RZ/G2L data sheet rev 1.30 published May 12, 2023. A summary is included here (note that this is a 34-bit address space): * 0x0_0000_0000 - 0x0_0002_FFFF SRAM area * 0x0_0003_0000 - 0x0_0FFF_FFFF Reserved area * 0x0_1000_0000 - 0x0_1FFF_FFFF I/O register area * 0x0_2000_0000 - 0x0_2FFF_FFFF SPI Multi area * 0x0_3000_0000 - 0x0_3FFF_FFFF Reserved area * 0x0_4000_0000 - 0x1_3FFF_FFFF DDR area (4 GiB) * 0x1_4000_0000 - 0x3_FFFF_FFFF Reserved area Within the DDR area, the first 128 MiB are reserved by TrustedFirmware. The region from 0x43F00000 to 0x47DFFFFF inclusive is protected for use in TrustedFirmware/OP-TEE, but all other memory is included in the memory map. This reservation is the same as used in R-Car Gen3/Gen4 and RZ/G2{H,M,N,E} SoCs. DRAM information is initialised based on the data in the fdt. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-17arm: rmobile: Add CPU detection for RZ/G2LPaul Barker
The ARM TrustedFirmware code for the Renesas RZ/G2L SoC family passes a devicetree blob to the bootloader as an argument in the same was previous R-Car Gen3/Gen4 SoCs. This blob contains a compatible string which can be used to identify the particular SoC we are running on. We do this as reading the DEVID & PRR registers from u-boot is not sufficient to differentiate between the R9A07G044L (RZ/G2L) and R9A07G044C (RZ/G2LC) SoCs. An additional read from offset 0x11861178 is needed but this address is in the OTP region which can only be read from the secure world (i.e. TrustedFirmware). So we have to rely on TrustedFirmware to determine the SoC and pass this information to u-boot via an fdt blob. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-17arm: rmobile: Include <asm/types.h> in headerPaul Barker
We don't want to rely on source files including <asm/types.h> before <asm/arch/rmobile.h>. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-16gpio: Add RZ/G2L GPIO driverPaul Barker
This driver adds support for the gpio features of the GPIO/PFC module in the Renesas RZ/G2L (R9A07G044) SoC. The new `rzg2l-pfc-gpio` driver is bound to the same device tree node as the `rzg2l-pfc-pinctrl` driver as the same hardware block provides both GPIO and pin multiplexing features. This patch is based on the corresponding Linux v6.5 driver (commit 52e12027d50affbf60c6c9c64db8017391b0c22e). Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-16pinctrl: renesas: Add RZ/G2L PFC driverPaul Barker
This driver adds support for the pinctrl features of the GPIO/PFC module in the Renesas RZ/G2L (R9A07G044) SoC. A multi-function `rzg2l-pfc` driver is defined for UCLASS_NOP, which binds the `rzg2l-pfc-pinctrl` UCLASS_PINCTRL driver dynamically. We also define common macros and functions for the PFC in <renesas/rzg2l-pfc.h>. This makes it easy to add an additional UCLASS_GPIO driver for the GPIO functionality of this module in a follow-up patch. This patch is based on the corresponding Linux v6.5 driver (commit 52e12027d50affbf60c6c9c64db8017391b0c22e). Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-16arm: rmobile: Restrict PINCTRL_PFC selection to R-Car gen3/gen4Paul Barker
The RZ/G2L family uses CONFIG_RCAR_64 but does not share a common PFC driver with the R-Car gen3 & gen4 boards. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-16clk: renesas: Add RZ/G2L & RZ/G2LC CPG driverPaul Barker
This driver provides clock and reset control for the Renesas R9A07G044L (RZ/G2L) and R9A07G044C (RZ/G2LC) SoC. It consists of two parts: * driver code which is applicable to all SoCs in the RZ/G2L family. * static data describing the clocks and resets which are specific to the R9A07G044{L,C} SoCs. The identifier r9a07g044 (without a final letter) is used to indicate that both SoCs are supported. clk_set_rate() and clk_get_rate() are implemented only for the clocks that are actually used in u-boot. The CPG driver is marked with DM_FLAG_PRE_RELOC to ensure that its bind function is called before the SCIF (serial port) driver is probed. This is required so that we can de-assert the relevant reset signal during the serial driver probe function. This patch is based on the corresponding Linux v6.5 driver (commit 52e12027d50affbf60c6c9c64db8017391b0c22e). Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-16arm: rmobile: Add basic R9A07G044L SoC supportPaul Barker
Add a config option for the R9A07G044L SoC used in the RZ/G2L so that we can make use of this in the subsequent driver patches. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-16arm: rmobile: Add basic RZ/G2L family supportPaul Barker
The Renesas RZ/G2L family includes the following ARM SoCs: * RZ/G2L (r9a07g044l) * RZ/G2LC (r9a07g044c) * RZ/G2UL (r9a07g043u) * RZ/V2L (r9a07g054l) Support for individual SoCs and evaluation boards will be added in separate patches. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-09-06ARM: rmobile: Clean up rmobile_cpuinfo_idx()Marek Vasut
Clean the function up a bit further. Return immediately on match and return ARRAY_SIZE() - 1 on failure. Add proper comment in that case. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2023-08-19arm: rmobile: Fix off-by-one error in cpuinfoPaul Barker
In rmobile_cpuinfo_idx() there is an off-by-one error in accessing the rmobile_cpuinfo array. At the end of the loop, i is equal to the array size, i.e. rmobile_cpuinfo[i] accesses one entry past the end of the array. The last entry in the array is a fallback value so the loop should count to ARRAY_SIZE(rmobile_cpuinfo) - 1 instead, this will leave i equal to the index of the fallback value if no match is found. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-08-13ARM: rmobile: Update little‐endian byte order option in srec_cat commandHai Pham
Since srecord v1.60, option "-Little_Endian_CONSTant" is deprecated. Fix the build warnings by updating little‐endian byte order option in srec_cat command when generating loader header. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-06-12Merge tag v2023.07-rc4 into nextTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-06-08ARM: renesas: Add R8A77980 V3HSK board and CPLD codeValentine Barshak
Add board code for the R8A77980 V3HSK board. Add CPLD sysreset driver to the R-Car V3H SK board. Extracted from a larger patch by Valentine Barshak. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Sync configs and board code with V3H Condor, squash CPLD driver in]
2023-06-08ARM: renesas: Add R8A77970 V3MSK board and CPLD codeValentine Barshak
Add board code for the R8A77970 V3MSK board. Add CPLD sysreset driver to the R-Car V3M SK board. Extracted from a larger patch by Valentine Barshak. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Sync configs and board code with V3M Eagle, squash CPLD driver in]
2023-06-08ARM: rmobile: Identify R-Car D3 R8A77995 r1.1 SoCHai Pham
Add support to identify R8A77995 r1.1 SoC. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> [Marek: Slight update to commit message, spell out the SoC model]
2023-06-08ARM: rmobile: Identify R-Car M3-W R8A7796 r1.1/1.2 SoCHiroyuki Yokoyama
r8a7796 cpu revision v1.2 has the same information as revision v1.1. This patch fixes revision display at startup to "rev 1.1/1.2". Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> [Marek: Slight update to commit message, spell out the SoC model]
2023-05-13ARM: rmobile: Add support for Renesas RZ/N1 SoCRalph Siemsen
The RZ/N1 is a family of SoC devices from Renesas, featuring: * ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3 * Integrated SRAM up to 6MB * Integrated gigabit ethernet switch * Optional DDR2/3 controller * I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD Add basic support for this family, modeled on the existing RZA1. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-04-07ARM: renesas: Add R8A779G0 V4H White Hawk board codeHai Pham
Add board code for R8A779G0 V4H White Hawk board. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Synchronize configuration symbols which are now switched to Kconfig Mallocate gd->bd->bi_boot_params, i.e. drop the assignment Sort headers, use clrbits_le32(), use BIT macros where appropriate Use CONFIG_SYS_CLK_FREQ for counter frequency instead of custom macro]
2023-04-07ARM: renesas: Add R8A779G0 V4H Kconfig entry and PRR IDHai Pham
Add Kconfig entry and PRR ID to support R8A779G0 V4H SoC. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Update commit message]
2023-04-07ARM: renesas: Add R8A779F0 S4 Spider board codeHai Pham
Add board code for R8A779F0 S4 Spider board. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Synchronize configuration symbols which are now switched to Kconfig Mallocate gd->bd->bi_boot_params, i.e. drop the assignment Sort headers, use clrbits_le32(), use BIT macros where appropriate Use CONFIG_SYS_CLK_FREQ for counter frequency instead of custom macro]
2023-04-07ARM: renesas: Add R8A779F0 S4 Kconfig entry and PRR IDHai Pham
Add Kconfig entry and PRR ID to support R8A779F0 S4 SoC. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Update commit message]
2023-04-07ARM: rmobile: Turn R-Car V3U into R-Car Gen4Hai Pham
Despite the name, R-Car V3U is the first member of the R-Car Gen4 family [1]. Hence reflect this in related files, select appropriate configuration options and split DT build into its own GEN4 entry. [1] https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/r-car-v3u-best-class-r-car-v3u-asil-d-system-chip-automated-driving Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Deduplicate DTC_FLAGS addition using RCAR_64 symbol Update commit message]
2023-04-07ARM: rmobile: Add R-Car Generation 4 supportHai Pham
This adds R-Car Generation 4 (Gen4) support as Renesas ARM64 SoC. In this version, reusing R-Car Gen3 lowlevel initialize routine [1] and R-Car Gen3 memory map tables [2] . [1] arch/arm/mach-rmobile/lowlevel_init_gen3.S [2] arch/arm/mach-rmobile/memmap-gen3.c Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: - Enable DTO support by default - Sort the Kconfig lists - Select RCAR_64 Kconfig option to pull in all the shared Kconfig options with Gen3, and use where applicable to deduplicate entries. - Fix reference [2] typo in commit message - Drop config options moved to Kconfig, rename rest to CFG_ accordingly to synchronize with upstream changes. Drop removed CONFIG_VERY_BIG_RAM. - Move board size limit to arch/Kconfig - Move GICR_BASE to headers instead of common config]
2023-03-18ARM: rmobile: Split R-Car Gen3 into separate Kconfig from common 64bit optionsMarek Vasut
There are multiple shared Kconfig options between R-Car Gen3 and Gen4. Keep the common options in Kconfig.64 and move the R-Car Gen3 specific options into separate Kconfig.rcar3 . The Kconfig.rcar3 contains SoC and board list, which is limited to R-Car Gen3. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18ARM: rmobile: Introduce CONFIG_RCAR_64 symbolMarek Vasut
Introduce common Kconfig symbol for 64bit R-Car platforms and move common configuration options into it. This is preparatory patch to prevent duplication of Kconfig lists later on, when Gen4 is added. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18ARM: rmobile: Factor out SYS_SOC Kconfig optionMarek Vasut
Pull the SYS_SOC Kconfig option to avoid duplication of this option in Kconfig.{32,64,rza1} . The default value is the same, so just set it in one location. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18ARM: rmobile: Sort R-Car Gen3 Kconfig listsMarek Vasut
Sort the 'imply' and 'select' lists in R-Car Gen3 Kconfig options. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18ARM: rmobile: Convert ifdef in rmobile_get_prr() to IS_ENABLED()Marek Vasut
Switch ifdef in rmobile_get_prr() to IS_ENABLED() macro. The CONFIG_RCAR_GEN3 will never have SPL counterpart, so the IS_ENABLED() macro is the right one here. No functional change, except for improved build test coverage. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18ARM: renesas: Enable DTO support by default on R-Car Gen3Marek Vasut
All R-Car Gen3 defconfigs present in U-Boot do enable DTO support, enable it for all of R-Car Gen3 by default in Kconfig instead, so that no new boards would miss this functionality. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-07rmobile: Drop unused ehci-rmobile driverSimon Glass
This is not used. Drop the driver and Kconfig option. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-07rmobile: Drop CONFIG_SH73A0 and associated codeSimon Glass
This option does not exist, so the code attached to it is not used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-07rcar: Drop timerSimon Glass
Drop this unused driver. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-02clk: renesas: Add and enable CPG reset driverMarek Vasut
Add trivial reset driver extension to the CPG clock driver. The change turns current CPG UCLASS_CLK driver instance into an UCLASS_NOP proxy driver, which in turn binds both generic rcar3_clk UCLASS_CLK clock driver as well as generic rcar_rst UCLASS_RESET reset driver to the CPG DT node. This way, any other drivers which use the 'reset' DT property can now obtain valid reset handle backed by a reset driver. The clock tables have been updated to represent the CPG driver and only implement the generic CPG proxy driver bind call, which binds the clock and reset drivers. The DM_RESET is now enabled for all R-Car Gen3 platforms. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02clk: renesas: r8a7796: Add R8A77961 CPG/MSSR supportHai Pham
Add support for the R-Car M3-W+ (R8A77961) SoC. R-Car M3-W+ is very similar to R-Car M3-W (R8A77960), which allows for both SoCs to share a driver. Based on Linux commit 2ba738d56db4 ("clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support") Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960Hai Pham
Rename CONFIG_CLK_R8A7796 for R-Car M3-W (R8A77960) to CONFIG_CLK_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961), which will use CONFIG_CLK_R8A77961. Based on Linux commit 92d1ebae9abf ("clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960") Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02pinctrl: renesas: r8a7796: Add R8A77961 PFC supportHai Pham
R-Car M3-W+ (R8A77961) is pin compatible with R-Car M3-W (R8A77960), which allows for both SoCs to share a driver. Based on Linux commit 708c69e9eacc ("pinctrl: sh-pfc: r8a7796: Add R8A77961 PFC support") and 74ce7a8044b0 ("pinctrl: renesas: r8a7796: Optimize pinctrl image size for R8A774A1") Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2023-02-02pinctrl: renesas: Synchronize R8A77960 M3-W and R8A77961 M3-W+ PFC tables ↵Marek Vasut
with Linux 6.1.7 Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ PFC tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Note that the Kconfig option name has been updated to match the Linux kernel Kconfig option name, from PINCTRL_PFC_R8A7796 to PINCTRL_PFC_R8A77960 . Also note that a new Kconfig option has been added to enable support for R8A77961 M3-W+ , the Kconfig option name is PINCTRL_PFC_R8A77961 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02pinctrl: renesas: Synchronize R8A7795 H3 PFC tables with Linux 6.1.7Marek Vasut
Synchronize R-Car R8A7795 H3 PFC tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Note that the Kconfig option name has been updated to match the Linux kernel Kconfig option name, from PINCTRL_PFC_R8A7795 to PINCTRL_PFC_R8A77951 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-01-20global: Finish CONFIG -> CFG migrationTom Rini
At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05Convert CONFIG_SH_GPIO_PFC et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SH_GPIO_PFC CONFIG_TMU_TIMER Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05global: Move remaining CONFIG_SYS_* to CFG_SYS_*Tom Rini
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05Remove unused symbolsTom Rini
This commit removes the following unused symbols: CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_SIZE CONFIG_SYS_PAXE_BASE CONFIG_SYS_PCCNT CONFIG_SYS_PCDAT CONFIG_SYS_PCDDR CONFIG_SYS_PCI1_ADDR CONFIG_SYS_PCI2_ADDR CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_SIZE CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_SIZE CONFIG_SYS_PCIE3_ADDR CONFIG_SYS_PCIE4_ADDR CONFIG_SYS_PCIE3_IO_PHYS CONFIG_SYS_PCIE3_IO_VIRT CONFIG_SYS_PCIE4_IO_PHYS CONFIG_SYS_PCIE4_IO_VIRT CONFIG_SYS_PLL_SETTLING_TIME CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_SP_CENA_SIZE CONFIG_SYS_RCAR_I2C0_BASE CONFIG_SYS_RCAR_I2C1_BASE CONFIG_SYS_RCAR_I2C2_BASE CONFIG_SYS_RCAR_I2C3_BASE CONFIG_SYS_SATA CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_SGMII_REFCLK_MHZ CONFIG_SYS_SGMII_LINERATE_MHZ CONFIG_SYS_SGMII_RATESCALE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI1_BASE CONFIG_SYS_SH_SDHI2_BASE CONFIG_SYS_SH_SDHI3_BASE CONFIG_SYS_SPI_ST_ENABLE_WP_PIN CONFIG_SYS_SPI_U_BOOT_SIZE CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT CONFIG_SYS_VCXK_BASE CONFIG_SYS_VCXK_DEFAULT_LINEALIGN CONFIG_SYS_VCXK_DOUBLEBUFFERED CONFIG_SYS_VCXK_ENABLE_DDR CONFIG_SYS_VCXK_ENABLE_PIN CONFIG_SYS_VCXK_ENABLE_PORT CONFIG_SYS_VCXK_INVERT_DDR CONFIG_SYS_VCXK_INVERT_PIN CONFIG_SYS_VCXK_INVERT_PORT CONFIG_SYS_VCXK_REQUEST_DDR CONFIG_SYS_VCXK_REQUEST_PIN CONFIG_SYS_VCXK_REQUEST_PORT CONFIG_SYS_VSC7385_BR_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-08-20arm: Remove kzm9g boardTom Rini
This board is behind on several mandatory DM migrations and is missing OF_CONTROL support that makes other conversions impossible. Remove it. Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Cc: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-20arm: Remove armadillo-800eva boardTom Rini
This board is behind on several mandatory DM migrations and is missing OF_CONTROL support that makes other conversions impossible. Remove it. Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06Migrate CUSTOM_SYS_INIT_SP_ADDR to Kconfig using system-constants.hTom Rini
- Make all users of CUSTOM_SYS_INIT_SP_ADDR reference SYS_INIT_SP_ADDR - Introduce HAS_CUSTOM_SYS_INIT_SP_ADDR to allow for setting the stack pointer directly, otherwise we use the common calculation. - On some platforms that were using the standard calculation but did not set CONFIG_SYS_INIT_RAM_SIZE / CONFIG_SYS_INIT_RAM_ADDR, set them. - On a small number of platforms that were not subtracting GENERATED_GBL_DATA_SIZE do so now via the standard calculation. - CONFIG_SYS_INIT_SP_OFFSET is now widely unused, so remove it from most board config header files. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-02armv8: Fix and simplify branch_if_master/branch_if_slaveAndre Przywara
The branch_if_master macro jumps to a label if the CPU is the "master" core, which we define as having all affinity levels set to 0. To check for this condition, we need to mask off some bits from the MPIDR register, then compare the remaining register value against zero. The implementation of this was slighly broken (it preserved the upper RES0 bits), overly complicated and hard to understand, especially since it lacked comments. The same was true for the very similar branch_if_slave macro. Use a much shorter assembly sequence for those checks, use the same masking for both macros (just negate the final branch), and put some comments on them, to make it clear what the code does. This allows to drop the second temporary register for branch_if_master, so we adjust all call sites as well. Also use the opportunity to remove a misleading comment: the macro works fine on SoCs with multiple clusters. Judging by the commit message, the original problem with the Juno SoC stems from the fact that the master CPU *can* be configured to be from cluster 1, so the assumption that the master CPU has all affinity values set to 0 does not hold there. But this is already mentioned above in a comment, so remove the extra comment. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-29ARM: rmobile: beacon: Enable reference clocks for USB and AVBAdam Ford
Both Ethernet and USB drivers get their reference clocks from the versaclock. Enable that driver and the common clock driver by default. Signed-off-by: Adam Ford <aford173@gmail.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 20:54:20 +0000