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2020-10-05Merge branch 'next'Tom Rini
Bring in the assorted changes that have been staged in the 'next' branch prior to release. Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-05Merge tag 'u-boot-atmel-2021.01-a' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel into next First set of u-boot-atmel features for 2021.01 cycle: This feature set includes a new CPU driver for at91 family, new driver for PIT64B hardware timer, support for new at91 family SoC named sama7g5 which adds: clock support, including conversion of the clock tree to CCF; SoC support in mach-at91, pinctrl and mmc drivers update. The feature set also includes updates for mmc driver and some other minor fixes and features regarding building without the old Atmel PIT and the possibility to read a secondary MAC address from a second i2c EEPROM.
2020-10-02ARM: dts: stm32mp1: DT alignment with Linux kernel v5.9-rc4Patrick Delaunay
DT alignment with Linux kernel v5.9-rc4 for the STM32MP15x soc device tree files and the STMicroelectronics boards device tree files. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-02ARM: dts: stm32: Add missing dm-spl props for SPI NOR on AV96Marek Vasut
The u-boot,dm-spl DT props are missing on AV96, hence the pinmux and flash0 nodes are not included in the reduced SPL DT. This prevents SPI NOR boot from working at all. Fix this by filling them in. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-26arm: rmobile: Use imply for BOARD_EARLY_INIT_FBiju Das
Use "imply" instead of "select" for BOARD_EARLY_INIT_F config option, and then disable it on boards which don't need it. Updated grpeach_defconfig to disable CONFIG_BOARD_EARLY_INIT_F option for RZA1. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26arm: mach-rmobile: Mark the default s_init function as weakBiju Das
Mark the default s_init function as weak, so that SoC's can override it if needed, and it will still be discarded if unused. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26arm: dts: r8a774e1: Import DTS from Linux 5.9-rc4Biju Das
Import R8A774E1 (RZ/G2H) SoC DTSI and headers from upstream Linux kernel 5.9-rc4 commit f4d51dffc6c0 ("Linux 5.9-rc4") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26arm: dts: r8a774b1: Import DTS from Linux 5.9-rc4Biju Das
Import R8A774B1 (RZ/G2N) SoC DTSI and headers from upstream Linux kernel 5.9-rc4 commit f4d51dffc6c0 ("Linux 5.9-rc4") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26arm: dts: r8a774a1: Import DTS from Linux 5.9-rc4Biju Das
Synchronize RZ/G2M SoC DTs with mainline Linux 5.9-rc4 commit f4d51dffc6c0 ("Linux 5.9-rc4") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26arm: rmobile: Identify R8A7796 r1.3 SoCBiju Das
Add support to identify R8A7796 r1.3 SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26ARM: rmobile: Enable RPC on Salvator-X, ULCB, EbisuMarek Vasut
Enable the RPC Hyperflash driver on R8A7795,R8A7796,R8A77965 Salvator-X,ULCB and R8A77990 Ebisu. Note that to make the HF accessible, mainline ATF is mandatory and must be built with RCAR_RPC_HYPERFLASH_LOCKED=0 . Note that this is intended for development and testing convenience only and must be disabled in deployment for platform security reasons. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-09-25ARM: mach-at91: add support for new SoC sama7g5Eugen Hristev
Add support for new SoC sama7g5 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-09-24arm: dts: lx2160a: Add IO rangeWasim Khan
Add IO range property to fix below error on uboot PCI: Failed autoconfig bar 18 Signed-off-by: Wasim Khan <wasim.khan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24armv8: dts: fsl-lx2160a: add gpio0 gpio1 gpio3 DT nodeshui.song
add gpio0 gpio1 gpio3 DT nodes to fsl-lx21600.dtsi Signed-off-by: hui.song <hui.song_1@nxp.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24armv8: lx2160a: fix reset sequenceMeenakshi Aggarwal
Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24arm64: Layerscape: Survive LPI one-way reset workaroundHou Zhiqiang
The workaround of LPI one-way reset issue is broken by the series: https://patchwork.ozlabs.org/project/uboot/list/?series=192398 This patch is to add DT node for GIC RD tables and create corresponding reserved-memory node in kernel DT to fix it. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24fsl-layerscape: enable dwc3 snooping featureRan Wang
Configure DWC3’s cache type to ‘cacheable’ for better performance. Actually related register definition and values are SoC specific, which means this setting is only applicable to Layerscape SoC, not generic for all platforms which have integrated DWC3 IP. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24Merge tag 'xilinx-for-v2021.01' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.01 arm64: - Support for bigger U-Boot images compiled with PIE microblaze: - Extend support for LE/BE systems zynqmp: - Refactor silicon ID detection code with using firmware interface - Add support for saving variables based on bootmode zynqmp-r5: - Fix MPU mapping and defconfig setting. xilinx: - Minor driver changes: names alignment - Enable UBIFS - Minor DT and macros fixes - Fix boot with appended DT - Fix distro boot cmd: - pxe: Add fixing for platforms with manual relocation support clk: - fixed_rate: Add DM flag to support early boot on r5 fpga: - zynqmppl: Use only firmware interface and enable SPL build serial: - uartlite: Enable for ARM systems and support endians mmc: - zynq: Fix indentation net: - gem: Support for multiple phys - emac: Fix 64bit support and enable it for arm64 kconfig: - Setup default values for Xilinx platforms - Fix dependecies for Xilinx drivers - Source board Kconfig only when platform is enabled - Fix FPGA Kconfig entry with SPL - Change some defconfig values bindings: - Add binding doc for vsc8531
2020-09-23xilinx: r5: Fix MPU setting for R5Michal Simek
Map all resource for R5 to operate properly. The patch is done based on the commit 23f7b1a77602 ("armv7R: K3: am654: Enable MPU regions") which also map the whole 4GB at first and then change mapping for DDR. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23fpga: kconfig: Rename SPL_FPGA_SUPPORT to SPL_FPGAMichal Simek
The patch does sed 's/SPL_FPGA_SUPPORT/SPL_FPGA/g' but also fixing Makefile and zynqmp.c to simplify if/endif logic in zynqmp.c. This change is mostly done to be able to use CONFIG_IS_ENABLED macro and obj-$(CONFIG_$(SPL_)FPGA) in Makefile. For them symbols need to be in sync. And removing one line from Topic Miami boards which is not needed because symbol is not enabled via Kconfig. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-23ARM: zynqmp: Fix SPL_DM_SPI dependenciesMichal Simek
Add missing dependencies for DM_SPI_FLASH. Kconfig reports it as: WARNING: unmet direct dependencies detected for SPL_DM_SPI_FLASH Depends on [n]: SPL [=n] && SPL_DM [=n] Selected by [y]: - ARCH_ZYNQMP [=y] && <choice> && SPL_DM_SPI [=y] Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23arm64: zynqmp: Change bl2_plat_get_bl31_params() guardingMichal Simek
It was protected just for SPL_OS_BOOT but this function is only called when SPL_ATF is enabled that's why change macro name. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23arm64: zynqmp: Correct value of shunt resistor for VCCINT and VCC_SOCSaeed Nowshadi
Value of shunt resistor for INA226s that monitor VCCINT and VCC_SOC power rails are incorrect. This patch corrects those values. Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
2020-09-23arm64: zynqmp: Add device tree node for 2nd mux on I2C1 busSaeed Nowshadi
There is 2nd pca9548 mux on I2C1 bus that controls SFP0, SFP1, and QSFP1 ports. Channel 0 and 1 are connected to J287 connector for SFP0 & SFP1, and channel 2 is connected to J288 connector for QSFP1. Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23xilinx: kconfig: Move sourcing of board Kconfig to mach foldersMichal Simek
Do not source xilinx board Kconfig by other boards. These configs should be available only when Xilinx platforms are selected. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-22binman: sunxi: Add help message for missing sunxi ATF BL31Simon Glass
Add a special help message pointing to the relevant README. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22sunxi: Convert 64-bit boards to use binmanSimon Glass
At present 64-bit sunxi boards use the Makefile to create a FIT, using USE_SPL_FIT_GENERATOR. This is deprecated. Update sunxi to use binman instead. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-22arm64: Add support for larger PIE U-BootEdgar E. Iglesias
Linking a U-Boot larger than 1MB fails with PIE enabled: u-boot/arch/arm/cpu/armv8/start.S:71:(.text+0x3c): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `__rel_dyn_end' defined in .bss_start section in u-boot. This extends the supported range by using adrp & add to load symbols early while starting up. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-22arm64: Trap PIE builds early if load address is not 4K alignedEdgar E. Iglesias
PIE requires a 4K aligned load address. If this is not met, trap the startup sequence in a WFI loop rather than running into obscure failures. Tested-by: Michal Simek <michal.simek@xilinx.com> Suggested-by: André Przywara <andre.przywara@arm.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-22arm64: Mention 4K aligned load addresses in the PIE Kconfig helpEdgar E. Iglesias
Mention the requirement of 4K aligned load addresses in the help section for the POSITION_INDEPENDENT option. Suggested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-22ARM: at91: common: guard ATMEL_PIT code by ifdefEugen Hristev
Atmel PIT timer is not available for next products that have another timer hardware block. To be able to use the common at91 code, guard the code that uses PIT by ifdefs. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-09-22board: atmel: common: introduce at91_set_eth1addr for second interfaceEugen Hristev
We already have a function to retrieve the mac address from one EEPROM. For boards with a second Ethernet interface, however, we would require another EEPROM with a second unique MAC address. Introduce at91_set_eth1addr which will look for a second EEPROM and set the 'eth1addr' variable with the obtained MAC address. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-09-21Merge branch '2020-09-14-generic-phy-error-trace' into nextTom Rini
- Add error tracing messages to the generic PHY infrastructure
2020-09-21Merge branch 'master' into nextTom Rini
Merge in v2020.10-rc5
2020-09-18IPQ40xx: Add USB nodesRobert Marko
There are drivers to support built in USB controller and PHY-s now, so lets add the USB nodes to DTSI. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18IPQ40xx: Add reset controller supportRobert Marko
Since we have a driver for the reset controller, lets add the necessary node. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18IPQ40xx: Add SMEM supportRobert Marko
There is already existing driver for SMEM so lets enable it for IPQ40xx as well. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18IPQ40xx: clk: Use dt-bindings instead of hardcodingRobert Marko
Its common to use dt-bindings instead of hard-coding clocks or resets. So lets use the imported Linux GCC bindings on IPQ40xx target. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-17apalis-imx8qm: rename all occurences to apalis-imx8Philippe Schenker
The Toradex product is called apalis-imx8 consisting of SoM with i.MX8QM and i.MX8QP SoCs. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-09-17colibri-imx8qxp: rename all occurences to colibri-imx8xPhilippe Schenker
The Toradex product is called colibri-imx8x consisting of SoM with i.MX8QXP and i.MX8DX SoCs. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-09-17ARM: mx6: ddr: Add support for iMX6UL/ULL/SL/SDLMarek Vasut
This patch adds support for iMX6UL/ULL/SL/SDL MMDC into the DDR calibration code. The difference between MX6DQ and MX6UL/ULL/SL is that the later SoCs have 2 SDQS registers, just like MX6SX, while the MX6DQ/MX6SDL has 8. Fixes: 4f4c128c65 ("ARM: mx6: ddr: Add support for iMX6SX") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eric Nelson <eric@nelint.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-09-17imx8mp: Remove parts MIMX8ML7 and MIMX8ML5 supportPeng Fan
Latest datasheet revE has removed MIMX8ML7D/5D/7C/5C parts, so update u-boot to remove decoding and support for those parts. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-09-17imx8m: clock_imx8mm: add missed returnPeng Fan
Add missed return Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-09-17imx8mq: fix SSCG_PLL_REFCLK_SEL_xPeng Fan
Fix SSCG_PLL_REFCLK_SEL_x, the offset starts from 0, not 16 Reported-by: Coverity 3448860 Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2020-09-17imx8mq: fix FRAC_PLL_REFCLK_SEL_MASKPeng Fan
Coverity reported dead code, however it is FRAC_PLL_REFCLK_SEL_MASK was wrongly set. Reported-by: Coverity 10045172 Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2020-09-17imx7: ccm: correct target interface numPeng Fan
According to i.MX 7Dual Applications Processor Reference Manual, Rev. 1 The target interface CCM root index ranges [0,124], so the number should be 125. Reported-by: Coverity 18045 Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2020-09-16rockchip: make_fit_atf: ignore empty PT_LOAD segmentHeinrich Schuchardt
The linker sometimes creates PT_LOAD segments with length (p_filesz) zero as described in https://man7.org/linux/man-pages/man5/elf.5.html. This leads to build failures. We should ignore empty segments. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Tested-by: Tom Rini <trini@konsulko.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-09-16rockchip: rv1108: Enable grf as pre-reloc nodeKever Yang
The grf node will be used before relocate, enable it in dts. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-09-15Merge tag 'ti-v2021.01-next' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-ti into next - Hyperflash boot for J7200 - Update Main R5FSS lockstep mode - R5F remoteproc support for J7200 - Minor env fixes - Add SPI boot support for am335x-icev2
2020-09-15arm: mach-omap2: am33xx: Add device structure for spiFaiz Abbas
Add platform data and a device structure for the spi device present on am335x-icev2. This requires moving all omap3_spi platform data structures and symbols to an omap3_spi.h so that the board file can access them. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
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