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path: root/arch/riscv/cpu/generic
AgeCommit message (Expand)Author
2023-10-24riscv: Remove common.h usageTom Rini
2023-10-19riscv: remove dram_init_banksize()Heinrich Schuchardt
2023-08-15common: return type board_get_usable_ram_topHeinrich Schuchardt
2023-07-24riscv: define a cache line size for the generic CPUHeinrich Schuchardt
2023-07-12riscv: Rename SiFive CLINT to RISC-V ALINTBin Meng
2022-09-23board_f: Fix types for board_get_usable_ram_top()Pali Rohár
2021-05-19riscv: qemu: Switch to use binman to generate u-boot.itbBin Meng
2021-05-17riscv: Split SiFive CLINT support between SPL and U-Boot properBin Meng
2021-03-27cpu: Rename SPL_CPU_SUPPORT to SPL_CPUSimon Glass
2021-02-15Merge branch '2021-02-02-drop-asm_global_data-when-unused'Tom Rini
2021-02-03riscv: Adjust board_get_usable_ram_top() for 32-bitBin Meng
2021-02-02common: Drop asm/global_data.h from common headerSimon Glass
2020-09-30riscv: Rework riscv timer driver to only support S-modeSean Anderson
2020-05-18common: Drop net.h from common headerSimon Glass
2020-04-23riscv: qemu: Remove the simple-bus driver for the SoC nodeBin Meng
2019-12-02common: Move board_get_usable_ram_top() out of common.hSimon Glass
2019-12-02common: Move enable/disable_interrupts out of common.hSimon Glass
2019-08-26riscv: add SPL supportLukas Auer
2019-08-26riscv: add run mode configuration for SPLLukas Auer
2019-02-27riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systemsAnup Patel
2019-02-27riscv: Rename cpu/qemu to cpu/genericAnup Patel