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Configure DWC3’s cache type to ‘cacheable’ for better
performance. Actually related register definition and values are SoC
specific, which means this setting is only applicable to Layerscape SoC,
not generic for all platforms which have integrated DWC3 IP.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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- fix SPL image generation
- fix incorrect console output
- increase malloc_f and malloc_r space to fix LZMA decompression errors
- increase SPI flash clock
Signed-off-by: Mauro Condarelli <mc5686@mclink.it>
[squashed to one patch, fix commit subject and description]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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The GPIO bank name for banks J and K are not correct when using the
'gpio' command from the console.
The driver derives the bank name from the device tree instance string by
using the instance value and adding 'A': gpio0@xxaddrxx is Bank A,
gpio1@yyaddryy is Bank B and so on.
On the PIC32, there is no Bank I so instances 8 and 9 need to be
incremented as a minimum change.
An alternative (less opaque) implementation would be to use a bank-name
property instead but this would require modifying the driver code too.
Signed-off-by: John Robertson <john.robertson@simiatec.com>
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GPIO state cannot be changed via the device tree (e.g. with gpio-hog) or
using the 'gpio' command from the console.
The root cause is a discrepancy between the driver and the device tree:
the driver code expects an absolute I/O address in the <reg> property,
while the device tree defines the address relative to a declaration in
the parent pinctrl node.
Changing the device tree to fix a driver issue would normally be wrong,
however:
- I have run the first version of U-Boot in which this driver appears
(v2016.03) and the same problem exists, so this is not a regression;
- There is no code that references a parent device tree node that might
suggest the intent of the author was to parse the DT as it exists now;
- The equivalent Linux PIC32 GPIO driver also uses absolute addresses
for the GPIO <reg> property. This change brings the U-Boot DT more
into line with Linux.
Additionally, the data sheet (Microchip ref. 60001361H) shows that the
register set to control a GPIO bank spans 0xE0 bytes, but the device
tree specified size is only 0x48 bytes.
Signed-off-by: John Robertson <john.robertson@simiatec.com>
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Signed-off-by: John Robertson <john.robertson@simiatec.com>
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The PIC32MZ DA Starter Kit does not need the card detect workaround
because the SDCD signal line is connected properly. Disable the
workaround in this case.
Signed-off-by: John Robertson <john.robertson@simiatec.com>
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Add a missing memset to acpi_create_spcr().
The other acpi_create_xxxx() functions perform a memset on their
structures, acpi_create_spcr() does not and as a result the contents of
this table are partly uninitialized (and thus random after every reset).
Fixes: b288cd960072 ("x86: acpi: Generate SPCR table")
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fix the tags format in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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Currently, the calculation for the length of the DSDT table includes any
bytes that are added for alignment, but those bytes are not initialized.
This is because the DSDT length is calculated after a call to
acpi_inc_align(). Split this up into the following sequence:
* acpi_inc()
* Calculate DSDT length
* acpi_align()
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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The term eMMC is used inconsistently within the FSP devicetree
bindings (e-mmc and emmc), especially for "emmc-host-max-speed"
documentation and code disagree.
Change all eMMC instances within the FSP bindings to consistently
use "emmc". The term "emmc" is already used a lot within U-Boot,
while "e-mmc" is only used in the FSP bindings.
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: correct one typo in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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The Toradex product is called apalis-imx8 consisting of SoM with
i.MX8QM and i.MX8QP SoCs.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
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The Toradex product is called colibri-imx8x consisting of SoM with
i.MX8QXP and i.MX8DX SoCs.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
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This patch adds support for iMX6UL/ULL/SL/SDL MMDC into the DDR calibration
code. The difference between MX6DQ and MX6UL/ULL/SL is that the later SoCs
have 2 SDQS registers, just like MX6SX, while the MX6DQ/MX6SDL has 8.
Fixes: 4f4c128c65 ("ARM: mx6: ddr: Add support for iMX6SX")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eric Nelson <eric@nelint.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
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Latest datasheet revE has removed MIMX8ML7D/5D/7C/5C parts, so
update u-boot to remove decoding and support for those parts.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add missed return
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Fix SSCG_PLL_REFCLK_SEL_x, the offset starts from 0, not 16
Reported-by: Coverity 3448860
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Coverity reported dead code, however it is FRAC_PLL_REFCLK_SEL_MASK
was wrongly set.
Reported-by: Coverity 10045172
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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According to i.MX 7Dual Applications Processor Reference Manual, Rev. 1
The target interface CCM root index ranges [0,124], so the number
should be 125.
Reported-by: Coverity 18045
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-10-rc5
The following bugs are fixed:
* unaligned access in br_i32_decode()
* missing restore of global data pointer in UEFI selftest
* missing restore of global data pointer on RISC-V in UEfI subsystem
* efi_var_mem_notify_exit_boot_services() should not be __efi_runtime
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The linker sometimes creates PT_LOAD segments with length (p_filesz) zero
as described in https://man7.org/linux/man-pages/man5/elf.5.html. This
leads to build failures. We should ignore empty segments.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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The grf node will be used before relocate, enable it in dts.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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Function set_gd() is needed in the UEFI sub-system if the global data
pointer is stored in a register.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
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The description for MT8512 has some mistake, so correct it.
Signed-off-by: Mingming Lee <Mingming.Lee@mediatek.com>
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PLL4Q is supplying both FDCAN and LTDC. In case HDMI is in use, the
50 MHz generated from PLL4Q cannot be divided well enough to produce
accurate clock for HDMI pixel clock. Adjust it to generate 74.25 MHz
instead. The PLL4P/PLL4R are generating 99 MHz instead of 100 MHz,
which is in tolerance for the SDMMC.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Gerald Baeza <gerald.baeza@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
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There is no dedicated pull resistor on the AV96 UART4 (console UART)
pin. In case there is no UART adapter installed on the AV96, the line
is floating and can trigger reception of garbage characters, which in
turn can abort U-Boot autoboot. Add default pull up to mitigate this
problem.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
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Remove the unnecessary inversion on the eth_env_set_enetaddr() result which
only make complex the code of setup_mac_address() and display an invalid
value in the associated pr_err.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
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- Mostly DFU fixes and r8152 fixes
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Instead of querying SDM for FPGA configuration status through mailbox
messages, U-Boot now checks System Manager's FPGA Config status register
for FPGA configuration status before resetting bridge.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
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Add g_dnl_get_board_bcd_device_number, the new BCD value is used by uuu to distinguish
if the SPL supports the SDPV.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
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Extend fastboot_set_reboot_flag arguments with reboot reason so that
it could handle different reboot cases in future.
Signed-off-by: Roman Kovalivskyi <roman.kovalivskyi@globallogic.com>
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This function is not actually used in U-Boot. Drop it.
Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Introduce USE_EARLY_BOARD_INIT option and select it by the actual users.
Cc: George McCollister <george.mccollister@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- Update to ABI 3.0
- Fix i2c write in eeprom driver
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Enabled SDIO slot 0 (south bridge) for SD card on
Espressobin board.
Change-Id: I51a2debf9fba276b9c4a2bc6da91328d47f443e3
Signed-off-by: Wilson Ding <dingwei@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/60945
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
[pali: Define cd-gpios and enable CONFIG_DM_REGULATOR_GPIO]
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Andre Heider <a.heider@gmail.com>
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Change active-high to active-low and change DT property name from
reset-gpio to reset-gpios. This format of gpio reset is used by
pci-aardvark driver in Linux kernel.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Tested-by: Andre Heider <a.heider@gmail.com>
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This commit fixes initialization of COMPHY on EspressoBin.
Commit 22f418935be4 ("phy: marvell: a3700: Use comphy_mux on Armada
37xx.") introduced usage of comphy_mux on Armada 37xx comphy driver.
The lanes are defined in comphy_a3700.c as described in functional
specification, that is:
lane 0 is SGMII1 or USB3
lane 1 is PCIe or SGMII0
lane 2 is SATA or USB3
But the DTS for EspressoBin configures PCIe on lane 0 and USB3 on
lane 1, which is wrong in the sense of the specification and doesn't
work with the comphy_mux code, which is 2 years now (the aardvark driver
causes synchronous abort in U-Boot).
It worked till the above mentioned commit, because the code for powering
up PCIe PHY doesn't work with lane number at all, and the code for
powering up USB3 PHY works differently only if USB3 is on lane 2, ie.
the check goes like:
if (lane == 2)
something
else
something else
so it does not differentiate between lanes 0 and 1.
In the future I shall post patches that remove the comphy_a3700 driver
and add comphy driver which uses calls to ATF, like Linux' driver does.
This will have the advantage of same DTS bindings as Linux', but till
this is done, we need this patch.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Pali Rohár <pali@kernel.org>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Andre Heider <a.heider@gmail.com>
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Update the ringacc and udma dt nodes to use the latest RM resource types
similar to the ones used in k3-j721e dt nodes.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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ARC is selecting TIMER which depends on DM but DM is not selected and
doesn't need to be enabled. Fix it by selecting DM for ARC architecture.
Kconfig is showing this missing dependency by:
WARNING: unmet direct dependencies detected for TIMER
Depends on [n]: DM [=n]
Selected by [y]:
- ARC [=y] && <choice>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
For 2020.10
-----------
- mx6: SOCs user selectable
Fix for imx6q_logic
Some DM conversion
- mx7: introduce secondary boot device
Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/720918010
Signed-off-by: Tom Rini <trini@konsulko.com>
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- Add basic Marvell/Cavium OcteonTX/TX2 support (Suneel)
- Infrastructure changes to PCI uclass to support these SoC's (Suneel)
- Add PCI, MMC & watchdog driver drivers for OcteonTX/TX2 (Suneel)
- Increase CONFIG_SYS_MALLOC_F_LEN for qemu-x86 (Stefan)
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https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Fix rk3399 evb sdcard support
- Fix for SPL_LED support
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- Sipeed Maix support S-mode.
- Provide command sbi.
- Use fdtdec_get_addr_size_auto_parent to get fu540 cache base address.
- Fix a compiler error with CONFIG_SPL_SMP=n.
- Fix sifive ram driver 32 compiler warnings.
- Fix kendryte/pll.h redefine nop() warning.
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We have a number of platforms that are a combination of a carrier board
and System-on-Module (SoM) that in turn allows for the board to have
different SoCs on it. In some cases, this is handled via board-specific
Kconfig options. In other cases we make use of
CONFIG_SYS_EXTRA_OPTIONS. This latter case however can lead to invalid
configurations as we will not in turn get options that in Kconfig are
selected by or depend on that setting.
To resolve this, make the SoC option a choice in Kconfig and make boards
depend on what they can support. This change opens us up for further
clean-ups in the cases where a single CONFIG_TARGET_xxx can support
different SoCs and today they do not, or do not cleanly do so.
Reported-by: Matt Porter <mporter@konsulko.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Soeren Moch <smoch@web.de>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Igor Opaniuk <igor.opaniuk@toradex.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Andreas Geisreiter <ageisreiter@dh-electronics.de>
Cc: Ludwig Zenz <lzenz@dh-electronics.de>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Akshay Bhat <akshaybhat@timesys.com>
Cc: Ken Lin <Ken.Lin@advantech.com.tw>
Cc: Ian Ray <ian.ray@ge.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Raffaele RECALCATI <raffaele.recalcati@bticino.it>
Cc: Simone CIANNI <simone.cianni@bticino.it>
Cc: Adam Ford <aford173@gmail.com>
Cc: Marcin Niestroj <m.niestroj@grinn-global.com>
Cc: "Eric Bénard" <eric@eukrea.com>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Jason Liu <jason.hui.liu@nxp.com>
Cc: Ye Li <ye.li@nxp.com>
Cc: Eric Nelson <eric@nelint.com>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Parthiban Nallathambi <parthiban@linumiz.com>
Cc: Marek Vasut <marex@denx.de>
Cc: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Niel Fourie <lusus@denx.de>
Cc: Martyn Welch <martyn.welch@collabora.com>
Cc: Richard Hu <richard.hu@technexion.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Boris Brezillon <bbrezillon@kernel.org>
Cc: Arkadiusz Karas <arkadiusz.karas@somlabs.com>
Cc: Breno Lima <breno.lima@nxp.com>
Cc: Francesco Montefoschi <francesco.montefoschi@udoo.org>
Cc: Silvio Fricke <open-source@softing.de>
Tested-by: Matt Porter <mporter@konsulko.com> [colibri_imx6]
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Marcin Niestroj <m.niestroj@grinn-global.com>
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This patch adds support for all OcteonTX2 96xx/95xx
boards from Marvell.
For 96xx boards, use octeontx_96xx_defconfig and
for 95xx boards, use octeontx_95xx_defconfig.
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
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This patch adds support for all OcteonTX 81xx/83xx
boards from Marvell.
For 81xx boards, use octeontx_81xx_defconfig and
for 83xx boards, use octeontx_83xx_defconfig.
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
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Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
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Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Add 64bit API for clrbits and setbits.
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Enable PCI memory regions in ranges property to be of multiple entry.
This helps to add support for SoC's like OcteonTX/TX2 where every
peripheral is on PCI bus.
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
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Provide a command to display information about the SBI implementation.
The output might look like:
=> sbi
SBI 0.2
OpenSBI
Extensions:
sbi_set_timer
sbi_console_putchar
sbi_console_getchar
sbi_clear_ipi
sbi_send_ipi
sbi_remote_fence_i
sbi_remote_sfence_vma
sbi_remote_sfence_vma_asid
sbi_shutdown
SBI Base Functionality
Timer Extension
IPI Extension
RFENCE Extension
Hart State Management Extension
The command can be used to construct a unit test checking that the
communication with the SEE is working.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
Tested-by: Pragnesh Patel <pragnesh.patel@openfive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
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Building with CONFIG_SPL_SMP=n results in:
arch/riscv/lib/spl.c: In function ‘jump_to_image_no_args’:
arch/riscv/lib/spl.c:33:6:
error: unused variable ‘ret’ [-Werror=unused-variable]
33 | int ret;
| ^~~
Define the variable ret as __maybe_unused.
Fixes: 191636e44898 ("riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL")
Fixes: 8c59f2023cc8 ("riscv: add SPL support")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
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