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2022-06-28Convert CONFIG_SYS_MPC85XX_NO_RESETVEC to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_MPC85XX_NO_RESETVEC Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28siemens: Move CONFIG_FACTORYSET to KconfigTom Rini
Introduce board/siemens/common/Kconfig and have it hold FACTORYSET to start with. Use select for this on the boards that need it. Cc: Anatolij Gustschin <agust@denx.de> Cc: Samuel Egli <samuel.egli@siemens.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28arm: samsung: Migrate a number of symbols to KconfigTom Rini
- In a number of cases, use CONFIG_ARCH_EXYNOS[45] rather than CONFIG_EXYNOS[45] - In other cases, test for CONFIG_ARCH_EXYNOS or CONFIG_ARCH_S5PC1XX - Migrate specific SoC CONFIG values to Kconfig - Use CONFIG_TARGET_x rather than CONFIG_x - Migrate other CONFIG_EXYNOS_x symbols to Kconfig - Reference CONFIG_EXYNOS_RELOCATE_CODE_BASE directly as EXYNOS_RELOCATE_CODE_BASE - Rename CONFIG_S5P_PA_SYSRAM to CONFIG_SMP_PEN_ADDR to match the rest of U-Boot usage. Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28arm: exynos: Remove old pwm backlight driverTom Rini
Remove the unused older exynos pwm backlight driver. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2022-06-28arm: samsung: Remove dead LCD codeTom Rini
Since bb5930d5c97f ("exynos: video: Convert several boards to driver model for video") there have been no callers of any of the exynos_lcd_* family of functions. Remove these from the boards, and then remove unused logo and related code as well. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2022-06-28Convert CONFIG_LBA48 et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_LBA48 CONFIG_SYS_64BIT_LBA Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28xtensa: Switch to using CONFIG_XTENSA for building device treesTom Rini
The only use of CONFIG_XTFPGA was to build all of the in-tree device trees. Switch to using CONFIG_XTENSA instead of a non-Kconfig symbol. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28tpl: Ensure all TPL symbols in Kconfig have some TPL dependencyTom Rini
Tighten up symbol dependencies in a number of places. Ensure that a TPL specific option has at least a direct dependency on TPL. In places where it's clear that we depend on something more specific, use that dependency instead. Reported-by: Pali Rohár <pali@kernel.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28spl: Move SPL_LDSCRIPT defaults to one placeTom Rini
We want to keep all of the default values for SPL_LDSCRIPT in the same place both for overall clarity as well as not polluting unrelated config files. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28PowerPC: Remove some unused USB codeTom Rini
These particular code paths aren't used anymore, remove. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28Convert CONFIG_TEGRA_GPU to KconfigTom Rini
This converts the following to Kconfig: CONFIG_TEGRA_GPU Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28usb: ehci-fsl: Remove non-DM codeTom Rini
The deadline for DM_USB migration has passed and all users have been migrated. Remove now unused code. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28Convert CONFIG_EFLASH_PROTSECTORS to KconfigTom Rini
This converts the following to Kconfig: CONFIG_EFLASH_PROTSECTORS Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28aspeed/ast2600: Fix SPL linker scriptJoel Stanley
The commit 99e2fbcb69f0 ("linker_lists: Rename sections to remove . prefix") changed the name of the linker list sections. As the Aspeed SPL linker wasn't in the tree yet, it missed the change. This updates the SPL linker to match arch/arm/cpu/u-boot-spl.lds which Aspeed was copied from. Fixes: 442a69c14375 ("configs: ast2600: Move SPL bss section to DRAM space") Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-28powerpc: mpc85xx: Set TEXT_BASE addresses to real base valuesPali Rohár
Currently CONFIG_SPL_TEXT_BASE and CONFIG_SYS_TEXT_BASE addresses are manually increased by 0x1000 due to .bootpg section. This section has size of 0x1000 bytes and is manually put by linker script before .text section (and therefore before base address) when CONFIG_SYS_MPC85XX_NO_RESETVEC is set. Due to this fact lot of other config options are manually increased by 0x1000 value to make correct layout. Note that entry point is not on CONFIG_SPL_TEXT_BASE (image+0x1000) but it is really on address CONFIG_SPL_TEXT_BASE-0x1000 (means at the start of the image). Cleanup handling of .bootpg section when CONFIG_SYS_MPC85XX_NO_RESETVEC is set. Put .bootpg code directly into .text section and move text base address to the start of .bootpg code. And finally remove +0x1000 value from lot of config options. With this removal custom PHDRS is not used anymore, so remove it too. After this change entry point would be at CONFIG_SPL_TEXT_BASE and not at address -0x1000 anymore. Tested on P2020 board with SPL and proper U-Boot. Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-27armv8 SHA-256 using ARMv8 Crypto ExtensionsLoic Poulain
This patch adds support for the SHA-256 Secure Hash Algorithm for CPUs that have support for the SHA-256 part of the ARM v8 Crypto Extensions. It greatly improves sha-256 based operations, about 17x faster on iMX8M evk board. ~12ms vs ~208ms for a 20MiB kernel sha-256 verification. asm implementation is a simplified version of the Linux version (from Ard Biesheuvel). Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2022-06-27armv8 SHA-1 using ARMv8 Crypto Extensions:Loic Poulain
This patch adds support for the SHA-1 Secure Hash Algorithm for CPUs that have support for the SHA-1 part of the ARM v8 Crypto Extensions. It greatly improves sha-1 based operations, about 10x faster on iMX8M evk board. ~12ms vs ~165ms for a 20MiB kernel sha-1 verification. asm implementation is a simplified version of the Linux version (from Ard Biesheuvel). Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2022-06-27Merge tag 'xilinx-for-v2022.10' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.10 cpu: - Add driver for microblaze cpu net: - Add support for DM_ETH_PHY to AXI emac and emaclite xilinx: - Switch platforms to DM_ETH_PHY - DT chagnes in ZynqMP and Zynq - Enable support for SquashFS zynqmp: - Add support for KR260 boards - Move BSS from address 0 - Move platform identification from board code to soc driver - Improve zynqmp_psu_init_minimize versal: - Enable loading app at EL1 serial: - Setup default address and clock rates for DEBUG uarts pinctrl: - Add support for tri state and output enable properties relocate-rela: - Clean relocate-rela implementation for ARM64 - Add support for Microblaze microblaze: - Add support for runtime relocation - Rework cache handling (wiring, Kconfig) based on cpuinfo - Remove interrupt support timer: - Extract axi timer driver from Microblaze to generic location
2022-06-24ARM: zynq: Fix size-cells for pl353 driverAmit Kumar Mahapatra
"size-cells" of the nand controller node should be 0 as the "reg" property of the nand device node contains the chip select number and not address information. The patch fixes the below compilation warning arch/arm/dts/zynq-zc770-xm011.dtb: Warning (reg_format): /axi/memory-controller@e000e000/nand-controller@0,0/nand@0:reg: property has invalid length (4 bytes) (#address-cells == 1, #size-cells == 1) Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/6e90665a2dad7fe8ade10b8f57101f8144963791.1655288559.git.michal.simek@amd.com
2022-06-24arm64: zynqmp: Fix usb node drive strength and slew rateAshok Reddy Soma
As per design, all input/rx pins should have fast slew rate and 12mA drive strength. Rest all pins should be slow slew rate and 4mA drive strength. Fix usb nodes as per this and remove setting of slow slew rate for all the usb gorup pins. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/b245c165f05845c1f3ab41a92c82b7ec1538cee4.1655288171.git.michal.simek@amd.com
2022-06-24microblaze: Remove interrupt handlerMichal Simek
The primary purpose for this code was timer. By converting it to CONFIG_TIMER there is no code which uses this implementation that's why remove it. If there is a need to handle interrupts this patch can be reverted in future. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/5f2decc5a30a5678490ebde26d8c6f5a5f873cda.1654684731.git.michal.simek@amd.com
2022-06-24microblaze: Convert axi timer to DM driverMichal Simek
Move axi timer driver from Microblaze to generic location. Origin implementation was irq based with counting down timer. CONFIG_TIMER drivers are designed differently that timer is free running up timer with automatic reload without any interrupt. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Michal Simek <michal.simek@amd.com> Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com
2022-06-24cpu: add CPU driver for microblazeOvidiu Panait
Add a basic CPU driver that retrieves information about the microblaze CPU core. cpu_ops handlers are implemented so that the "cpu" command can work properly: U-Boot-mONStR> cpu list 0: cpu@0 MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000 U-Boot-mONStR> cpu detail 0: cpu@0 MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000 ID = 0, freq = 50 MHz: L1 cache, MMU Note: cpu_ver_lookup[] and family_string_lookup[] arrays were imported from linux. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-14-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: add support for handling PVR dataOvidiu Panait
Add helper code for PVR (Processor Version Register) data handling. It will be used by the UCLASS_CPU driver to populate cpuinfo fields at runtime. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-13-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: cache: introduce flush_dcache_range()Ovidiu Panait
Align microblaze with the other architectures and provide an implementation for flush_dcache_range(). Also, remove the microblaze exception in drivers/core/device.c. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-11-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: cache: introduce cpuinfo structureOvidiu Panait
Introduce a minimal cpuinfo structure to hold cache related info. The instruction/data cache size and cache line size are initialized early in the boot to default Kconfig values. They will be overwritten with data from PVR/dtb if the microblaze UCLASS_CPU driver is enabled. The cpuinfo struct was placed in global_data to allow the microblaze UCLASS_CPU driver to also run before relocation (initialized global data should be read-only before relocation). gd_cpuinfo() helper macro was added to avoid volatile "-Wdiscarded-qualifiers" warnings when using the pointer directly. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-10-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com> (s/bralid/brlid/)
2022-06-24microblaze: cache: introduce flush_cache_all()Ovidiu Panait
All flush_cache() calls in microblaze code are supposed to flush the entire instruction and data caches, so introduce flush_cache_all() helper to handle this. Also, provide implementations for flush_dcache_all() and invalidate_icache_all() so that icache and dcache u-boot commands can work. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-9-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: cache: introduce Kconfig options for icache/dcache sizesOvidiu Panait
Replace XILINX_DCACHE_BYTE_SIZE macro with two Kconfig symbols for instruction and data caches sizes, respectively: CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE Also, get rid of the hardcoded value in icache_disable(). Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-8-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com> (s/bralid/brlid/g)
2022-06-24microblaze: cache: split flush_cache() functionOvidiu Panait
Factor out icache/dcache components from flush_cache() function. Call the newly added __flush_icache()/__flush_dcache() functions inside icache_disable() and dcache_disable(), respectively. There is no need to flush both caches when disabling a particular cache type. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-7-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: cache: improve icache Kconfig optionsOvidiu Panait
Replace CONFIG_ICACHE with a Kconfig option more limited in scope - XILINX_MICROBLAZE0_USE_WIC. It should be enabled if the processor supports the "wic" (Write to Instruction Cache) instruction. It will be used to guard "wic" invocations in microblaze cache code. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-6-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: cache: improve dcache Kconfig optionsOvidiu Panait
Replace CONFIG_DCACHE with a Kconfig option more limited in scope - XILINX_MICROBLAZE0_USE_WDC. It should be enabled if the processor supports the "wdc" (Write to Data Cache) instruction. It will be used to guard "wdc" invocations in microblaze cache code. Also, drop all ifdefs around flush_cache() calls and only keep one CONFIG_IS_ENABLED() guard within flush_cache() itself. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-5-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: cache: replace XILINX_USE_DCACHE -> CONFIG_DCACHEOvidiu Panait
XILINX_USE_DCACHE macro was removed in 7556fa09e0e ("microblaze: Simplify cache handling"), but it was still used in a couple of places. Replace those occurences with CONFIG_DCACHE. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-4-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: start.S: remove unused codeOvidiu Panait
in16/out16 routines seem to not be used anywhere in microblaze code, so remove them. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-3-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: Add support for run time relocationMichal Simek
Microblaze is using NEEDS_MANUAL_RELOC from the beginnging. This is causing issues with function pointer arrays which need to be updated manually after relocation. Building code with -fPIC and linking with -pic will remove this limitation and there is no longer need to run manual update. By default still old option is enabled but by disabling NEEDS_MANUAL_RELOC code will be compiled for full relocation. The patch does couple of things which are connected to each other. - Define STATIC_RELA dependency to call relocate-rela to fill sections. - REMAKE_ELF was already enabled but u-boot file can't be used because sections are empty. relocate-rela will fill them and output file is u-boot.elf which should be used. - Add support for full relocation (u-boot.elf) - Add support for early relocation when u-boot.bin is loaded to different address then CONFIG_SYS_TEXT_BASE - Add rela.dyn and dynsym sections Disabling NEEDS_MANUAL_RELOC U-Boot size increased by 10% of it's original size (550kB to 608kB). Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/a845670b34925859b2e321875f7588a29f6655f9.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Create SYM_ADDR macro to deal with symbolsMichal Simek
Symbol handling depends on compilation flags. Right now manual relocation is used that's why symbols can be referenced just by name and there is no need to find them out. But when position independent code (PIC) is used symbols need to be described differently. That's why having one macro change is easier than changing the whole code. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/d704e9a267c8b536452fb999111dbfbc9d652be5.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Add comment about reset locationMichal Simek
Better to add comment to explain why reset vector points all the time to origin U-Boot location. If reset happens U-Boot should start from it's origin location. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/5ca6341b7487708247fe2948d7e496ea6f7c2e02.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Remove _start symbol handling at U-Boot startMichal Simek
Right now U-Boot runs all the time from the same address where it is loaded but going to full relocation code starting address doesn't need to be fixed and can be simply discovered from reading PC register. That's why use r20 to get PC address and subtract offset from the beginning to get starting address. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/044b727c33dfbe662f68512d0da0775a4805f360.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Remove code around r20 in relocate_code()Michal Simek
r20 is not used that's why remove logic around it. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1b32bab5c050d099b2f6d49bc4896322ed03d788.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Optimize register usage in relocate_codeMichal Simek
There are additional operations which can be done simpler that's why improve logic around relocation address r7 handling and _start symbol. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c8b60f72f1605c2ba6b4b7be1893d7e6ec3d8597.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Change stack protection address to new stack addressMichal Simek
SLR low address is still setup to 0 that's why only high limit should be updated. STACK_SIZE macro is present and could be possible used for low address alignment but it is not done by this patch. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c00cb843df848703b760a65934ed3ce31fafcf19.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Separate code end substractionMichal Simek
Follow up patch will convert symbol handling that's why it is necessary to separate logic around symbols to special instruction. It adds 4B for new instruction but it is worth to do it to have code ready for for full relocation. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/030863fa9a9c1ca0a9b082fe498522da09189fbc.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Enable REMAKE_ELFMichal Simek
Enable u-boot.elf recreation from u-boot.bin to prepare for removing manul relocation. Enable option for big endian configuration but it is not used too much that's why it is completely untested. By supporting this system there is a need to define LITTLE/BIG endian Kconfig options to pass -EL/-EB flags. Full command line for u-boot.elf recreation looks like this: microblazeel-xilinx-linux-gnu-objcopy -I binary -B microblaze \ -O elf32-microblazeel u-boot.bin u-boot-elf.o Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/7e242a519fcd1c693b9103c5599b515af555ca43.1655299267.git.michal.simek@amd.com
2022-06-24mips: Move endianness selection to arch/KconfigMichal Simek
This option will be used by Microblaze that's why move it to generic location to be able to use it. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/ceb39fa615cb5657b66a7b77bab99e86ca7a3346.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Fix typo in exception.cMichal Simek
Trivial fix. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c4ede6dc738c5bd7c518f3bb2c9410b15c102e20.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Remove CONFIG_TEXT_BASE from codeMichal Simek
Use symbol instead macro to find where U-Boot starts. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/d5d4c201bee6171e85b47783d916387d84db0456.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Fix early stack allocationMichal Simek
CONFIG_SYS_INIT_SP_OFFSET macro place stack to TEXT_BASE - SYS_MALLOC_F_LEN but there is no reason to do it now because board_init_f_alloc_reserve() returns exact location where stack should be. That's why stack location is calculated at run time and there is no need to hardcode it via macro. This change will help with placing U-Boot to any address. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/e9aee69646e022fd8a96cbee2d2a07ab81fb6e05.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Fix stack protection behaviorMichal Simek
When U-Boot starts stack protection can be already enabled that's why setup the lowest possible SLR value which is address 0. And the highest possible stack in front of U-Boot. That's why you should never load U-Boot to the beginning of DDR. There must be some space reserved. Code is using this location for early malloc space, early global data and stack. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/86b9748bad12142659804d6381bc6bbf20be44f1.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Switch absolute branches to relativeMichal Simek
There is no reason to use absolute branches and use just relative. This change helps with moving binary to different location and start it from there. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/83a5103b85c1c2220cd3ab4d5365169c6660e40a.1655299267.git.michal.simek@amd.com
2022-06-24arm64: zynqmp: Fix tps544/u3007 node descriptionMichal Simek
u3007 is removed in zynqmp-m-a2197-02-revA board and on zynqmp-m-a2197-03-revA it was renamed to v3022 at address 0x18. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/f477796bcca6fce09168699a0498d792f4a54acf.1655287013.git.michal.simek@amd.com
2022-06-24arm64: zynqmp: Update tps53681 i2c addressMichal Simek
TI manual (https://www.ti.com/lit/gpn/TPS53681) is saying that i2c address is 7bit where c0h is 1100000 which is 0x60. This will fix issues reported by make dtbs that 0xc0 is above 7bit regular i2c address range. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/2f50c1cd258f6b05deb2a6a9af7fa92952f3f8cb.1655287013.git.michal.simek@amd.com
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