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2022-01-05microblaze: branch to base vector address on resetOvidiu Panait
Current code assumes that the vector base address is always at 0x0. However, this value is configurable for MicroBlaze using the CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR Kconfig option. Update the reset routines to branch to this location instead. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/20211130163358.2531677-10-ovidiu.panait@windriver.com Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05microblaze: start.S: add support for configurable vector base addressOvidiu Panait
Current code assumes that the vector base address is always at 0x0. However, this value is configurable for MicroBlaze, so update the __setup_exceptions routine to work with any vector base address. The r4 register is reserved for the vector base address inside __setup_exceptions and the function prologe/epilogue are also updated to save and restore r4. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/20211130163358.2531677-9-ovidiu.panait@windriver.com Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05microblaze: migrate CONFIG_SYS_USR_EXCEP to KconfigOvidiu Panait
Migrate CONFIG_SYS_USR_EXCEP to Kconfig. Also, rename it to XILINX_MICROBLAZE0_USR_EXCEP in order to match the naming convention of microblaze-generic Kconfig options. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/20211130163358.2531677-7-ovidiu.panait@windriver.com Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05microblaze: drop CONFIG_SYS_RESET_ADDRESS macroOvidiu Panait
Microblaze is one the last two users of the CONFIG_SYS_RESET_ADDRESS macro (the other is arch/powerpc/cpu/mpc8xx/cpu.c, but the macro is not defined anywhere in powerpc code, so it should be removed there too). Replace CONFIG_SYS_RESET_ADDRESS usage in start.S with CONFIG_SYS_TEXT_BASE. If the reset address should really be user-configurable, a new Kconfig option could be added. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/20211130163358.2531677-6-ovidiu.panait@windriver.com Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05microblaze: start.S: use stack space as scratch memory for endian offsetOvidiu Panait
To simpify the code, use stack space as scratch memory for endian offset calculation, rather than saving/restoring the first unused MB vector. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/20211130163358.2531677-5-ovidiu.panait@windriver.com Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05microblaze: Kconfig: SPL dependencies fixupOvidiu Panait
Enable SPL_LIBCOMMON_SUPPORT and SPL_LIBGENERIC_SUPPORT if CONFIG_SPL=y, in order to fix the following link failures: common/spl/spl.o: in function `board_init_r': common/spl/spl.c:755: undefined reference to `puts' ... common/spl/spl.o: in function `board_init_r': common/spl/spl.c:756: undefined reference to `hang' common/spl/spl.c:740: undefined reference to `memset' Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/20211130163358.2531677-4-ovidiu.panait@windriver.com Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05microblaze: spl: add board_boot_order() implementationOvidiu Panait
Microblaze has three boot modes defined in microblaze/include/asm/spl.h, but only booting from NOR flash is currently useable. Add a custom board_boot_order() implementation so that RAM and SPI boot modes can also be selected if the corresponding load-image support is present. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/20211130163358.2531677-3-ovidiu.panait@windriver.com Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05microblaze: u-boot.lds: replace __end symbol with _endOvidiu Panait
board_fdt_blob_setup() uses the _end symbol to find the dtb in the non-spl case. In order to allow microblaze builds to compile successfully with CONFIG_OF_SEPARATE, the _end symbol must be defined. Align microblaze with the other architectures and use _end symbol rather than __end to mark the end of the u-boot binary. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/20211130163358.2531677-2-ovidiu.panait@windriver.com Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05arm64: zynqmp: Remove clock-names from GEM in zynqmp-clk-ccf.dtsiMichal Simek
Remove clock-names from GEM nodes from clk-ccf because they should be only present in zynqmp.dtsi. And as is visible both clock-names defined didn't really match. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/d6045d81b3e7e97df0ba3eeacb9f3f75ed7cff18.1637239345.git.michal.simek@xilinx.com
2022-01-05arm64: zynqmp: Add resets to all GEMsMichal Simek
There is a need to get IP out of reset to operate properly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/041362197e8de8e9c696da64429107505bdc0c73.1637239345.git.michal.simek@xilinx.com
2022-01-05arm64: zynqmp: Add u-boot,dm-pre-reloc to dpsub nodeMichal Simek
u-boot,dm-pre-reloc is necessary for DP driver to allocate enough space for framebuffer before relocation. Power domain driver is called when video console is used for example by loading BMP image. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/5e93acee1746913a6e42741e5e797f0b4ab98d44.1637239230.git.michal.simek@xilinx.com
2022-01-05zynqmp: gpio: Add support for zynqmp gpio modepin driverT Karthik Reddy
ZynqMP modepin driver has capability to get/set/check status of modepin gpios. These modepins are accessed using xilinx firmware. In modepin register, [3:0] bits set direction, [7:4] bits read IO, [11:8] bits set/clear IO. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/2d802d98fd56d95d764532a33e844d935e0cebb3.1635505900.git.michal.simek@xilinx.com
2021-11-26sandbox: poweroff in efi_system_reset()Heinrich Schuchardt
efi_system_reset() should exit if called with EFI_RESET_SHUTDOWN. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-11-18arm64: Add missing GD_FLG_SKIP_RELOC handlingMarek Vasut
In case U-Boot enters relocation with GD_FLG_SKIP_RELOC, skip the relocation. The code still has to set up new_gd pointer and new stack pointer. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
2021-11-16Merge branch '2021-11-15-assorted-fixes'Tom Rini
- Rename "tqc" to "tq" and related updates - Assorted minor ARM updates, build updates and documentation updates
2021-11-16Merge tag 'xilinx-for-v2022.01-rc3' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.01-rc3 sdhci: - Fix emmc mini case with missing firmware interface zynqmp: - Restore JTAG interface if required - Allow overriding board name - Add support for DLC21 - Fix one fallthrought statement description - Use config macro instead of name duplication - Save multiboot to variable firmware: - Handle ipi_req errors better - Use local buffer in case user doesn't need it instead of NULL/0 location spi: - gqsi: Fix write issue at low frequencies net: - gem: Disable broadcasts
2021-11-15arm: Fix bad memcpy.S str8w macro argument countPierre-Clément Tosi
Remove the extra (empty) argument passed to str8w, causing the following error: <instantiation>:40:47: error: too many positional arguments str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f ^ u-boot/arch/arm/lib/memcpy.S:240:5: note: while in macro instantiation 17: forward_copy_shift pull=16 push=16 ^ Note: no functional change intended. Fixes: d8834a1323af ("arm: Use optimized memcpy and memset from linux") Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
2021-11-15board: tq: fix spelling of "TQ-Systems"Matthias Schiffer
"TQ-Systems" is written with a dash. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
2021-11-15board: rename "tqc" vendor to "tq"Matthias Schiffer
The subdivision name "TQ Components" hasn't been in use for a long time. Rename the vendor directory to "tq", which also matches our Device Tree vendor prefix. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
2021-11-12Remove CONFIG_SERIAL_MULTITom Rini
This symbol has been functionally dead for a long time. Remove the last and recent re-introductions of setting it, and update the whitelist so it will not be re-introduced again. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-12Convert CONFIG_FSL_LAYERSCAPE to KconfigTom Rini
This converts the following to Kconfig: CONFIG_FSL_LAYERSCAPE Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-11ARM: dts: am335x-chiliboard: add /chosen/tick-timerMarcin Niestroj
Commit 4b2be78ab66c ("time: Fix get_ticks being non-monotonic") has broken boot on chiliboard platform, as it requires '/chosen/tick-timer' in device-tree. This resulted in following panic message: Could not initialize timer (err -19) Provide missing chosen property in device-tree to fix chiliboard support. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2021-11-11Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
- device-tree sync-up with Linux for ls1028a - fixes/update in fsl-ddr driver, fsl-validate, lx2162a, fsl-mc, spintable code, configs, qspi node, pci - enable EFI_SET_TIME support in sl28 - powerpc: Drop -mstring
2021-11-10Merge tag 'u-boot-stm32-20211110' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-stm - DHSOM update: - Remove nWP GPIO hog - Increase SF bus frequency to 50Mhz and enable SFDP - Disable video output for DHSOM - Disable EFI - Enable DFU_MTD support - Create include file for STM32 gpio driver private data - Split board and SOC STM32MP15 configuration - Device tree alignement with v5.15-rc6 for STM32MP15 - Add binman support for STM32MP15x - Normalise newlines for stm32prog - Update OTP shadow registers in SPL
2021-11-10stm32mp15: tidy up #ifdefs in cpu.cPatrick Delaunay
We should avoid #ifdef in C modules and the unused functions are eliminated by the linker. Use the more readable IS_ENABLE() instead. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10stm32mp15: replace CONFIG_TFABOOT when it is possiblePatrick Delaunay
In some part of STM32MP15 support the CONFIG_TFABOOT can be replaced by other config: CONFIG_ARMV7_PSCI and CONFIG_ARM_SMCCC. This patch also simplifies the code in cpu.c, stm32mp1_ram.c and clk_stml32mp1.c as execution of U-Boot in sysram (boot without SPL and without TFA) is not supported: the associated initialization code is present only in SPL. This cleanup patch is a preliminary step to support SPL load of OP-TEE in secure world, with SPL in secure world and U-Boot in no-secure world. Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10stm32mp15: remove configs dependency on CONFIG_TFABOOTPatrick Delaunay
Remove the dependency on CONFIG_TFABOOT in stm32mp Kconfig - always activate the ARCH config: CONFIG_ARCH_SUPPORT_PSCI and CONFIG_CPU_V7_HAS_NONSEC - CONFIG_ARMV7_NONSEC is deactivated in trusted defconfig - the correct sysreset driver is activated in each defconfig: CONFIG_SYSRESET_PSCI or SYSRESET_SYSCON Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10arm: stm32mp: bsec: Update OTP shadow registers in SPLPatrick Delaunay
Currently the upper OTP (after 57) are shadowed in U-Boot proper, when TFABOOT is not used. This choice cause an issue when U-Boot is not executed after SPL, so this BSEC initialization is moved in SPL and no more executed in U-Boot, so it is still executed only one time. After this patch this BSEC initialization is done in FSBL: SPL or TF-A. To force this initialization in all the case, the probe of the BSEC driver is forced in SPL in the arch st32mp function: spl_board_init(). Even if today BSEC driver is already probed in STM32MP15x clock driver clk_stm32mp1.c because get_cpu_type() is called in stm32mp1_get_max_opp_freq() function. Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10ARM: dts: stm32: Drop nWP GPIO hog on DHSOMMarek Vasut
The nWP GPIO hog was used to unlock the SPI NOR write protect when U-Boot used to operate the SPI NOR in 1-1-1 mode. Now that the SPI NOR is operated in 1-1-4 mode, the hog has adverse effects and causes transfer corruption, since the hogged pin is also the IO2 pin. Remove the hogs. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10gpio: stm32: create include file for driver private dataPatrick Delaunay
The stm32 gpio driver private data are not needed in arch include files, they are not used by code except for stm32 gpio and pincontrol drivers, using the same IP; the defines for this IP is moved in a new file "stm32_gpio_priv.h" in driver/gpio. This patch avoids to have duplicated file gpio.h for each SOC in MPU directory mach-stm32mp and in each MCU directory arch-stm32* and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-10arm: dts: stm32mp15: alignment with v5.15-rc6Patrick Delaunay
Device tree alignment with Linux kernel v5.15-rc6 - Set {bitclock,frame}-master phandles on ST DKx - Add coprocessor detach mbox on stm32mp15x-dkx boards - Add coprocessor detach mbox on stm32mp157c-ed1 board Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-10stm32mp: add binman support for STM32MP15xPatrick Delaunay
Use binman to add the stm32image header on SPL binary for basic boot or on U-Boot binary when it is required, i.e. for TF-A boot without FIP support, when CONFIG_STM32MP15x_STM32IMAGE is activated. The "binman" tool is the recommended tool for specific image generation. This patch allows to suppress the config.mk file and it is a preliminary step to manage FIT generation with binman. The init_r parsing of U-Boot device tree to search the binman information is not required for STM32MP15, so the binman library can be removed in U-Boot (CONFIG_BINMAN_FDT is deactivated). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-11-10stm32mp: stm32prog: Normalise newlinesWilliam Grant
The missing trailing newline could confuse check-config.sh if the definition of an option was on the first line of the next file that find(1) happened to return. Signed-off-by: William Grant <wgrant@ubuntu.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-09Merge https://source.denx.de/u-boot/custodians/u-boot-samsungTom Rini
[trini: Migrate CONFIG_EXYNOS7420 as part of merging, so espresso7420 still builds] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-09armv8: layerscape: use memalign() to allocate spintable codeMichael Walle
Don't use efi_allocate_pages(). The allocated memory isn't carved out of the lmb allocations. The memory might then be allocated twice. Particulary, this might happened with the fdt_high/initrd_high feature which will relocate the fdt/ramdisk. This might then overlap with the spin table. Instead use memalign() which allocates on memory on the heap which is correctly carved out by lmb. Please note, that the memory is later reserved in the device tree as well as in the EFI memory map in ft_fixup_cpu() (in arch/arm/cpu/armv8/fsl-layerscape/fdt.c). Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09armv8: fsl-layerscape: rework the dwc3 snooping enable codeMichael Walle
Instead of looking at all USB (host) devices, just search all DWC3 device tree nodes. This will (1) fix a panic if of_match is zero and (2) also apply the fixup if the controller is in peripheral mode. Both happen when the DWC3 USB controller driver is used. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: sl28: sync dtbsMichael Walle
Copy the board device tree files from linux v5.14. On top of the v5.14 dtbs the changes of these two patches are included here which are needed for u-boot: https://lore.kernel.org/linux-devicetree/20210831134013.1625527-7-michael@walle.cc/ https://lore.kernel.org/linux-devicetree/20210831134013.1625527-8-michael@walle.cc/ At the time of this writing the patches were accepted and will be included in 5.15. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: sync the fsl-ls1028a.dtsi with linuxMichael Walle
Now that everything is prepared, copy the fsl-ls1028a.dtsi from the linux kernel v5.14.12. Notable changes: - second watchdog added - the number of chip selects of the SPI controller is now correct and reflects what the hardware offers - the LPUARTs have the correct clock parent - USB controllers are enabled by default, which was already the case before this sync because all board enabled all the USB controller nodes. A linux patch to fix this is pending. - the eSDHC controller changes from big-endian to little-endian, but that property seems to be not used at all. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: disable the PCIe controller by defaultMichael Walle
Disable the PCIe controllers by default, just like in the linux device tree. But there is one catch, for linux they are enabled in-place by the bootloader. Obviously, this doesn't work for the bootloader. Thus we explicitly enable the controllers in the -u-boot.dtsi files. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: move the PCI I/O window to matchMichael Walle
To make the synchronization of the u-boot device tree with the one from linux easier, move the I/O window to the one which is specified in the linux device tree. The actual value shouldn't matter as long as it mapped to the corresponding memory window of the PCIe controller which is a 32GiB window at 80_0000_0000h (first controller) or 88_0000_0000h (second controller). Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: remove num-lanes in the PCIe controller nodesMichael Walle
This property is unused in the layerscape PCIe controller driver and not present in the linux device tree. Remove it to be similarly. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09pci: layerscape: add official ls1028a binding supportMichael Walle
The official bindind of the PCIe controller of the ls1028a has the following compatible string: compatible = "fsl,ls1028a-pcie"; Additionally, the resource names and count are different. Update the driver to support this binding and change the entry in the ls1028a device tree. Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09usb: xhci: fsl: add new compatible fsl,ls1028a-dwc3Michael Walle
The official ls1028a binding of the driver uses the following as compatibles: compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; Change the ls1028a device tree and add this new compatible to the fsl specific xhci driver, otherwise the generic dwc3 driver will be used with the compatibles above. Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de> Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09scsi: ceva: rename the resource name to match the linux kernel oneMichael Walle
The driver will look for a named resource "ecc-addr", but this isn't the official binding. In fact, the official device tree binding documentation doesn't mention any resource names at all. But it is safe to assume that it's the linux ones we have to use if we want to be compatible with the linux device tree. Thus rename "ecc-addr" to "sata-ecc" and convert all the users in u-boot. While at it, also rename "sata-base" to "ahci" although its not used at all. This change doesn't affect the SATA controller on the ZynqMP. Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09serial: lpuart: add new compatible fsl, ls1028a-lpuartMichael Walle
The official ls1028a binding of the driver uses the following as compatibles: compatible = "fsl,ls1028a-lpuart"; Add the missing compatible to the driver and update the device tree. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09spi: fsl_dspi: rename num-cs to spi-num-chipselectsMichael Walle
The official devicetree bindings specifies spi-num-chipselects as the name. Use it. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09spi: fsl_dspi: add new compatible fsl, ls1021a-v1.0-dspiMichael Walle
The official ls1028a binding of the driver uses the following as compatibles: compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; Add the missing compatible to the driver and update the device tree. We can use the fallback "fsl,ls1021a-v1.0-dspi", because the endianness is determined by the little-endian property and not by the compatible string itself. Further, we won't need and specific details on the DMA configuration (which is different on the LS1021A). If it's ever needed, we can later add the more specific "fsl,ls1028a-dspi" compatible to the driver. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09watchdog: sp805_wdt: use correct compatible stringMichael Walle
According to the linux device tree specification the compatible string is: compatible = "arm,sp805", "arm,primecell"; Fix all users in u-boot. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: update the labelsMichael Walle
Update the labels of the nodes to match the kernel ones. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: move the iRC node and its devices into /socMichael Walle
While inserting them into the new location, keep them sorted by the register base offset just like in the linux kernel device tree. While at it fix the indentation. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-21 05:46:49 +0000