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2020-05-11Merge tag 'ti-v2020.07-rc2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Fix boot issues on Nokia RX-51 - Configure AM6 CPSW for 10Mbps in rgmii mode. - Minor changes for J721e
2020-05-11Merge tag 'u-boot-imx-20200511' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX for 2020.07 ---------------- - i.MX NAND and nandbxb for i.MX8M - imx8MM : new beacon devkit - imx8MQ : new pico-imx8MQ - imx8QXP : extend to enable M4, fixes - add thermal support - caches in SPL (missing board) - Fixes Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/685391011
2020-05-11test: dm: update test for open-drain/open-source emulation in gpio-uclassNeil Armstrong
Add tests for testing open-drain/open-source emulation in gpio-uclass. It also adds two test3-gpios configured as GPIO_ACTIVE_LOW. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-11odroid-c2: enable USB host controllerBeniamino Galvani
Enable the second USB controller, which is connected to a hub with 4 ports. The first controller is for the OTG port and is currently not supported. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> [narmstrong: removed useless DWC2_UTMI_WIDTH in meson64.h] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-05-11arm: K3: Increase default SYSFW image size allocationAndrew F. Davis
The memory allocated to store the FIT image containing SYSFW and board configuration data is statically defined to the largest size expected. Some additions to the board configuration data has pushed us slightly over the current defined size on some HS devices, expand to 278000. Signed-off-by: Andrew F. Davis <afd@ti.com>
2020-05-11phy: Use _nodev naming convention if non-device clientsJagan Teki
Clients that are requesting some of uclass API's without a device (with ofnode) usually have _nodev naming convention. - clk_get_by_index_nodev - clk_get_by_name_nodev - reset_get_by_index_nodev - gpio_request_by_name_nodev So, update the same naming convention PHY framework. This doesn't change the existing functionality. Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-10imx8: cpu: check resource owned after sid failPeng Fan
When we create software partition, we still need let parent partition to configure sid, so move the check after sid failed. Acked-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10imx: imx8qm/qxp: check whether m4 partition bootedPeng Fan
Add code to check m4 partition booted or not, we will use this to runtime set device tree file that passed to Linux Kernel. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10imx8: Select boot device dynamicallyYe Li
For fspi build, we will enable both SPL NOR support and SPL SPI support. SPL will dynamically check the resource owner then select corresponding boot device. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10imx: imx8qm/qxp: Recover SPL data section for partition rebootPeng Fan
When doing partition reboot, the boot image won't be reloaded by ROM, it is just CPU reset to boot entry. The SW has to keep the boot image inside the RAM unchanged. It includes both the TEXT section and DATA section. For SPL, the problem is DATA section will be updated at runtime, so in next partition reboot the data is not same as the initial value from cold boot. If any code depends on the initial value, then it will have problem. This patch introduces a mechanism to recover the data section for partition reboot. It adds a new section in image for saving data section. When from cold boot, the data section will be saved to that new section at SPL early phase. When from partition reboot, the data section will be restored from the new section. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10imx: imx8qm/imx8qxp: Power down the resources before SPL jump to u-bootPeng Fan
Make sure that all devices that are powered up by SPL are powered down before entering into the u-boot. Otherwise the subsystem/device will never be powered down by SCFW, due to SPL and u-boot are in different partitions. Benefiting from power domain driver, this patch implements the function "imx8_power_off_pd_devices" to power off all active devices. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10imx: imx8qm/qxp: add get_board_serialPeng Fan
Add get_board_serial support, the info could be got from fuse. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10imx: imx8qm/qxp: Fix issue in get_effective_memsizeYe Li
When Trusty OS allocates the mem region from 0xfe0000000-0xffffffff, the get_effective_memsize does not return correct memory size. There is a check in get_effective_memsize to find the memreg where the u-boot is running, and return the size of that memreg as the result of get_effective_memsize. When using aligned start, the value is 0x80200000 since it is 2MB aligned. Thus the finding of memreg will fail and return the PHYS_SDRAM_1_SIZE because u-boot text base is 0x80020000. This cause u-boot is relocated to the high memory where has been occupied by Trusty OS. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10imx: imx8qm/qxp: reserving DDR memory for M4Peng Fan
The DDR memory from 0x88000000 to 0x8FFFFFFF is assigned to M4 on QM and QXP. The M4 can allocate this memory by two ways, in SCD or u-boot. In this patch, u-boot addes the memory reserve node to DTB to pass the info to kernel, no matter the M4 memory is reserved in SCD or u-boot. So kernel won't access M4 reserved memory. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10nandbcb: read boot search count from fuse for imx8qxpHan Xu
add support for imx8qxp to read boot search count from fuse in nandbcb Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10cmd: nandbcb: Reconstruct the nandbcb tool for all platformsHan Xu
The original nandbcb tool was designed for imx6 only, when trying to leverage it to replace the kobs-ng tool, we found the design is not friendly for supporting all platforms. To support all iMX6/7/8 platforms and for easy further maintain, I reconstruct the structure of the tool. The main changes including: 1. Use platform_data to determine the logic branches rather than simply use SOC name. 2. More data structures as parameter for functions. 3. Global variables to define the FCB/DBBT/FW locations. 4. Implement the kobs-ng default 4 FCB/4 DBBT/2 FW layout. 5. Support Hamming coding/ 40bit BCH/ 62bit BCH coding FCB. 6. Dump and compare all written FCB/DBBT to verify data integrity. The tool has been verified on iMX6Q/DL, 6SX, 7D, 6ULL, iMX8QX, iMX8MM. Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10nandbcb: add nandbcb dump command for i.MX6Alice Guo
Verify/dump boot structures. Signed-off-by: Alice Guo <alice.guo@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10nandbcb: add nandbcb dump command for i.MX8MMAlice Guo
Verify/dump boot structures written to NAND Flash chip. Signed-off-by: Alice Guo <alice.guo@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10nandbcb: support i.MX8MAlice Guo
Tested on i.MX8MM EVK, imx8mm evk uses BCH encoding and randomizer modify macro and print size_t with %zx use CONFIG_IMX8M because it should apply to imx8mq/mm/mn Signed-off-by: Alice Guo <alice.guo@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10nandbcb: fix the issue cannot support gf_14 NAND bootHan Xu
bchtype in FCB should be associated to the gf_13/14 settings in BCH, fix the issue and test on Micron 29F64G08CBABB, it can boot after the change. Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10imx8: Replace SC_R_LAST with SC_R_NONE in DTBLeonard Crestez
We are currently using SC_R_LAST as a marker for imx8 power domain tree nodes without a resource attached. This value is compiled into dtb as part of the linux build and used by uboot. The SC_R_LAST constant changes frequently as SCFW resources are added (by design) and every time we need to update linux and uboot headers together or boot can fail. Fix this by replacing SC_R_LAST usage with a new constant SC_R_NONE defined to be 0xFFF0. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10imx8: power: Add PD device lookup interface to power domain uclassPeng Fan
Add power_domain_lookup_name interface to power domain uclass to find a power domain device by its DTB node name, not using its associated client device. Through this interface, we can operate the power domain devices directly. This is needed for non-DM drivers. Modified from Ye's NXP downstream patch only for legacy imx8 power domain driver, since we have not migrated to use new power domain driver. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10imx: Add support for i.MX8MM Beacon EmbeddedWorks devkit.Adam Ford
Beacon EmbeddedWorks, formerly known as Logic PD, is releasing a devkit based on the i.MX8M Mini SoC consisting of baseboard + SOM. It supports eMMC on the SOM, microSD on the baseboard, various GPIO, the PINCTRL, and UART. Signed-off-by: Adam Ford <aford173@gmail.com>
2020-05-10mtd: nand: support GPMI NAND driver for i.MX8Peng Fan
enable the GPMI NAND driver for i.MX8, i.MX8 use similar controller as i.MX8M - register definition for i.mx8 - DMA structure must be 32bit address Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10mtd: mxs_nand: fix the gf_13/14 definition issueHan Xu
gf_13/14 mask was not set correctly in register definition. Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10mxs_nand: Add support for i.MX8MYe Li
Update the gpmi/apbh_dma/bch drivers and relevant registers for i.MX8M. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10nand: mxs: correct bitflip for erased NAND pagePeng Fan
This patch is a porting of http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/ commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38 " i.MX6QP and i.MX7D BCH module integrated a new feature to detect the bitflip number for erased NAND page. So for these two platform, set the erase threshold to gf/2 and if bitflip detected, GPMI driver will correct the data to all 0xFF. Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q with the one for i.MX6QP. " In this patch, i.MX6UL is added and threshold changed to use ecc_strength. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10imx: cpu: support tmuPeng Fan
Support tmu when print cpu info Signed-off-by: peng Fan <peng.fan@nxp.com>
2020-05-10imx: regs: add more fuse bank structurePeng Fan
Add more fuse bank structure for use. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10imx8mp: Set default SNSR25C for TMU probe1Ye Li
So far u-boot only load SNSR25C for TMU main probe (probe 0). However, kernel enables two probes. So it also needs to set default SNSR25C of TCALIV1 for blank samples. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10imx: load calibration parameters from fuse for i.MX8MPYe Li
i.MX8MP thermal which has two probes and supports temperature range from -40 to 125. The driver still uses default 1p HW calibration at 25C and loads calibration parameters from fuse. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10imx: i.MX8MN: Enable loading TASR and TCALIV from fuseYe Li
Like iMX8MM, iMX8MN also needs SW to load TMU TASR and TCALIV registers value from fuse before enabling TMU calibration. Otherwise the calibration is not exact. Reviewed-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10imx8mm: Load fuse for TMU TCALIV and TASRYe Li
On iMX8MM, the default value of TMU registers TCALIV and TASR need be loaded from fuse. HW won't do this, it expect SW loads them before using TMU. Reviewed-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10fec: Move imx_get_mac_from_fuse declare to imx fileYe Li
imx_get_mac_from_fuse is used to load MAC address from fuse. On imx8mp, we have two different ENET controllers and both need to call this function. So decouple its declare from fec driver. Reviewed-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10imx: add module fuse supportPeng Fan
There are different parts from one SoC. Take i.MX6ULL for example, some part might not have ENET, some might have; some might not have USB, some might have. The information could be got from OCOTP, to make one image support the different parts, we need runtime disable linux kernel dts node and uboot driver probe if the corresponding module not exists in the part. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10ARM: imx: pico-imx8mq: Add support for Technexion Pico-iMX8MQMarek Vasut
Add initial support for Technexion Pico-iMX8MQ SoM on PicoPI carrier board. Currently working is ethernet, serial, eMMC. DT is imported from Linux 5.4.28 ("462afcd6e7ea") . Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2020-05-10Merge branch 'master' of git://git.denx.de/u-bootStefano Babic
2020-05-07cmd: cache: Fix non-cached memory cachabilityPatrice Chotard
If dcache is switched OFF to ON state and if non-cached memory is used, this non-cached memory must be re-declared as uncached to mmu each time dcache is set ON. Introduce noncached_set_region() to set this non-cached region's mmu settings. Let architecture override it by defining it as a weak function. For ARM architecture, noncached_set_region() defines all noncached region as non-cacheable. Issue found on STM32MP1 platform using dwc_eth_qos ethernet driver, when going from dcache OFF to dcache ON state, ethernet driver issued TX timeout errors when performing dhcp or ping. It can be reproduced with the following sequence: dhcp while true ; do ping 192.168.1.300 ; dcache off ; ping 192.168.1.300 ; dcache on ; done Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Cc: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Stephen Warren <swarren@nvidia.com> Reviewed-by: Marek Vasut <marex@denx.de>
2020-05-07arm: juno: enable USBAndre Przywara
The Juno board features a standard compliant EHCI/OHCI USB host controller pair, which we can just enable. The platform data is taken from the device tree. This allows to use USB mass storage (the only storage on a Juno r0) for loading. At least on my board USB seems a bit flaky, I need two "usb reset" sequences after the "usb start" to detect an USB hard drive. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-07arm: juno: Use PSCI based resetAndre Przywara
So far the Juno board wasn't implementing reset. Let's just use the already existing PSCI_RESET based method to avoid any extra code. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-07arm: juno: Enable OF_CONTROLAndre Przywara
The Arm Juno board was still somewhat stuck in "hardcoded land", even though there are stable DTs around, and one happens to actually be on the memory mapped NOR flash. Enable the configuration options to let the board use OF_CONTROL, and add a routine to find the address of the DTB partition in NOR flash, to use that for U-Boot's own purposes. This can also passed on via $fdtcontroladdr to any kernel or EFI application, removing the need to actually load a device tree. Since the existing "afs" command and its flash routines require flash_init() to be called before being usable, and this is done much later in the boot process, we introduce a stripped-down partition finder routine in vexpress64.c, to scan the NOR flash partitions for the DT partition. This location is then used for U-Boot to find and probe devices. The name of the partition can be configured, if needed, but defaults to "board.dtb", which is used by Linaro's firmware image provided. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-05Merge git://git.denx.de/u-boot-usbTom Rini
- MediaTek USB host support
2020-05-05Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini
- Add DM model for P1010RDB - Add I2C DM Model support for P1010RDB, T1042RDB, T2080, T4240RDB, MPC8548CDS, T1024RDB, P4080, P3041DS, P2041RDB, P2020RDB, P1020RDB, P5040DS - Fix reference to READM.qe_firmware
2020-05-04Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini
- Support 64-bit U-Boot as the payload for coreboot x86
2020-05-04Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- 2 MVEBU related fixes
2020-05-04Merge tag 'u-boot-imx-20200502' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX for 2020.07 ---------------- - imxrt: fix LCD clock, fix doc - new board: Coral Dev - imx8: enable Cache in SPL. SNVS, update SCFW API - imx8MM: fix reset, 8MQ quand and QuadLite, CPU speed grading - MX6ULL : is_imx6ull to include i.MX6ULZ - Net: add config to enable TXC delay Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/682033914
2020-05-04Merge tag 'u-boot-rockchip-20200501' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - dts clean up to use -u-boot for px30, rk3399 boards - dts sycn from upstream kernel for rk3328, rk3399 - add rockchip rng driver - new board support: rk3328-roc-cc, rk3399-roc-pc,Nanopi M4 2GB
2020-05-04x86: coreboot: Allow building an SPL imageSimon Glass
Make a few adjustments to allow us to build an SPL image for coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-04x86: Update SPL for corebootSimon Glass
At present SPL only works on bare-metal builds. With a few tweaks it can be used for coreboot also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-04x86: Move work-around out of cpu_jump_to_64bit_uboot()Simon Glass
At present this function copies U-Boot from the last 1MB of ROM. This is not the right way to do it. Instead, the binman symbol should provide the location. But in any case the code should live in the caller, spl_board_load_image(), so that the 64-bit jump function can be used elsewhere. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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