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2013-11-01m68k: convert makefiles to Kbuild styleMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Jason Jin <Jason.jin@freescale.com>
2013-10-24fsl/mpc85xx: define common serdes_clock_to_string functionValentin Longchamp
This allows to share some common code for the boards that use a corenet base SoC. Two different versions of the function are available in fsl_corenet_serdes.c and fsl_corenet2_serdes.c files. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix t1040qds.c] Acked-by: York Sun <yorksun@freescale.com>
2013-10-24powerpc/c29xpcie: add DDR ECC on off config settingPo Liu
c29xpcie REV_A board DDR ECC chip has bad impedance in hardware, force that kind of board to be DDR ECC off when booting. Other version board config ECC on/off by hwconfig=fsl_ddr:ecc=on in uboot enviroment. Signed-off-by: Po Liu <Po.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
2013-10-16boards/c29xpcie: Update TLB and LAW size for IFC NAND, CPLDPrabhakar Kushwaha
NAND,CPLD AMASK register is programmed for 64K size. so Update TLB & LAW size accordingly. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-10-16powerpc/p1010rdb: add p1010rdb-pb support with updating p1010rdb-paShengzhou Liu
- Rename old P1010RDB board as P1010RDB-PA. - Add support for new P1010RDB-PB board. - Some optimization. For more details, see board/freescale/p1010rdb/README. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix conflicts in boards.cfg] Acked-by: York Sun <yorksun@freescale.com>
2013-10-16board/p1010rdb: add pin mux and sdhc support in any bootShengzhou Liu
Since pins multiplexing, SDHC shares signals with IFC, with this patch: To enable SDHC in case of NOR/NAND/SPI boot a) For temporary use case in runtime without reboot system run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC. b) For long-term use case set 'esdhc' in hwconfig and save it. To enable IFC in case of SD boot a) For temporary use case in runtime without reboot system run 'mux ifc' in u-boot to validate IFC with invalidating SDHC. b) For long-term use case set 'ifc' in hwconfig and save it. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2013-10-16powerpc/eeprom: update MAX_NUM_PORTS to adapt non-256-bytes EEPROMShengzhou Liu
Some boards use System EEPROM with 128-bytes instead of 256-bytes. Since we regard 256-bytes EEPROM as standard EEPROM with default value for MAX_NUM_PORTS. For those non-256-bytes EEPROM, we can redefine MAX_NUM_PORTS in board-specific file to override the default MAX_NUM_PORTS. This patch doesn't impact on previous existing boards. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2013-10-16powerpc/p1010rdb: remove unused cpld_showShengzhou Liu
Function cpld_show() was for debug and not called, so clean it. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2013-10-16powerpc/t1040qds: Add T1040QDS boardPrabhakar Kushwaha
T1040QDS is a high-performance computing evaluation, development and test platform supporting the T1040 QorIQ Power Architecture™ processor. T1040QDS board Overview ----------------------- - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration - RegEx Pattern Matching Acceleration - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Integrated 8-port Gigabit Ethernet switch - Four 1 Gbps Ethernet controllers - SERDES Connections, 8 lanes supporting: — PCI Express: supporting Gen 1 and Gen 2; — SGMII — QSGMII — SATA 2.0 — Aurora debug with dedicated connectors - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and Interleaving -IFC/Local Bus - NAND flash: 8-bit, async, up to 2GB. - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB - GASIC: Simple (minimal) target within Qixis FPGA - PromJET rapid memory download support - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - QIXIS System Logic FPGA - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - Video - DIU supports video at up to 1280x1024x32bpp - USB - Supports two USB 2.0 ports with integrated PHYs — Two type A ports with 5V@1.5A per port. — Second port can be converted to OTG mini-AB - SDHC - SDHC port connects directly to an adapter card slot, featuring: - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC — Supporting eMMC memory devices - SPI - On-board support of 3 different devices and sizes - Other IO - Two Serial ports - ProfiBus port - Four I2C ports Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: fix conflict in boards.cfg] Acked-by-by: York Sun <yorksun@freescale.com>
2013-10-16powerpc: Fix CamelCase warnings in DDR related codePriyanka Jain
Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h has various parameters with embedded acronyms capitalized that trigger the CamelCase warning in checkpatch.pl Convert those variable names to smallcase naming convention and modify all files which are using these structures with modified structures. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
2013-10-16powerpc/B4860: enable PBL tool for B4860Shaohui Xie
Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a pbl boot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2013-10-16powerpc/t4240: updated rcw_cfg to align with default hardware configurationShaohui Xie
Default configuration has been changed, the most important one is DDR ref_clock which is changed from 66.67MHz to 133.33MHz. so the ratio need to change from 24x to 12x to keep the DDR frequency. There are also some other optimise to align with default configuration. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2013-10-16powerpc: p1_p2_rdb_pc: add TPL for p1_p2_rdb_pc nand bootYing Zhang
Enable TPL for p1_p2_rdb_pc nand boot. Signed-off-by: Ying Zhang <b40530@freescale.com>
2013-10-16powerpc : p1_p2_rdb_pc : Enable p1_p2_rdb_pc to start from eSPI with SPLYing Zhang
Enable p1_p2_rdb_pc to start from eSPI with SPL. Signed-off-by: Ying Zhang <b40530@freescale.com>
2013-10-16powerpc: p1_p2_rdb_pc: Enable p1_p2_rdb_pc to boot from SD Card with SPLYing Zhang
Enable p1_p2_rdb_pc to start from eSDHC with SPL. Signed-off-by: Ying Zhang <b40530@freescale.com>
2013-10-16SGMII:fix PHY addresses for QSGMII Riser Card working in SGMII modeZhao Qiang
Fix PHY addresses for QSGMII Riser Card working in SGMII mode on board P3041/P5020/P4080/P5040/B4860. QSGMII Riser Card can work in SGMII mode, but having the different PHY addresses. So the following steps should be done: 1. Confirm whether QSGMII Riser Card is used. 2. If yes, set the proper PHY address. Generally, the function is_qsgmii_riser_card() is for step 1, and set_sgmii_phy() for step 2. However, there are still some special situations, take P5040 and B4860 as examples, the PHY addresses need to be changed when serdes protocol is changed, so it is necessary to confirm the protocol before setting PHY addresses. Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-16Corenet/p5040/SGMII:fix the problem for SGMII5/6Zhao Qiang
SGMII5/6 and SGMII7/8 are not on the same slot on P5040 according to the serdes protocol. So it is not proper to organize SGMII5/6 and SGMII7/8 on one bus and SGMII5/6 can't work. So a new bus SUPER_HYDRA_FM3_SGMII_MDIO is added for SGMII5/6 Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-16powerpc/c29xpcie: modify DDR parameter to make DDR more stablePo Liu
DDR parameters clk_adjust were changed. This can make the DDR run more stable. The new value were gotten by the DDR testing tool. Signed-off-by: Po Liu <Po.Liu@freescale.com>
2013-10-14Coding Style cleanup: remove trailing empty linesWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14Coding Style cleanup: replace leading SPACEs by TABsWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Drop changes for PEP 4 following python tools] Signed-off-by: Tom Rini <trini@ti.com>
2013-10-14Coding Style cleanup: remove trailing white spaceWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-02Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
2013-09-27mx35pdk: Fix error handling in board_late_init()Fabio Estevam
If smc911x_initialize() fails we should return the error immediately. While at it, also check the error from cpu_eth_init(). Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
2013-09-27mx28evk: Propagate the error if cpu_eth_init() failsFabio Estevam
If cpu_eth_init() fails we should return the error immediately. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-09-20mx28evk: Fix checkpatch warningFabio Estevam
Fix the following checkpatch warning: $ ./tools/checkpatch.pl -F board/freescale/mx28evk/mx28evk.c CHECK: Alignment should match open parenthesis #109: FILE: freescale/mx28evk/mx28evk.c:109: + writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, + &clkctrl_regs->hw_clkctrl_enet); Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-09-20mx6slevk: Add Ethernet supportFabio Estevam
mx6slevk has a SMSC8720 connected in RMII mode. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-09-20mx6qsabreauto: Return error if cpu_eth_init() failsFabio Estevam
Currently board_eth_init() always return 0, but we should propagate the error when cpu_eth_init() fails. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-09-20mx6sabresd: Return error if cpu_eth_init() failsFabio Estevam
Currently board_eth_init() always return 0, but we should propagate the error when cpu_eth_init() fails. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-09-20mx6sabresd: Reset counter to prevent error messageFabio Estevam
If a HDMI cable is not connected, the following message is seen on boot: CPU: Freescale i.MX6Q rev1.1 at 792 MHz Reset cause: POR Board: MX6-SabreSD DRAM: 1 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 No panel detected: default to HDMI unsupported panel HDMI Reset the 'i' variable to fix the 'unsupported panel' message. This follows the same idea of commit 47ac53d7ae (imx: nitrogen6x/mx6qsabrelite: Fix bug in board_video_skip). Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-09-20mx6sabresd: Avoid hang when HDMI cable is not connectedFabio Estevam
Since commit d9b894603 (mx6sabresd: Add LVDS splash screen support) the following hang happens if the HDMI cable is not connected or the 'panel' variable is not set: U-Boot 2013.10-rc2-12978-g47ac53d-dirty (Sep 11 2013 - 15:07:38) CPU: Freescale i.MX6Q rev1.2 at 792 MHz Reset cause: POR Board: MX6-SabreSD DRAM: 1 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 ... Provide a check to 'dev->detect' in order to prevent the hang. Reported-by: Pardeep Kumar Singla <b45784@freescale.com> Suggested-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-09-20Cosmetic: Fix a number of typos, no functional changes.Robert P. J. Day
Fix various misspellings of things like "environment", "kernel", "default" and "volatile", and throw in a couple grammar fixes. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2013-09-13Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic
Conflicts: MAINTAINERS boards.cfg Signed-off-by: Stefano Babic <sbabic@denx.de>
2013-09-10mx6sabresd: Add LVDS splash screen supportFabio Estevam
mx6sabresd boards can be connected to a Hannstar XGA LVDS panel. Add support for displaying U-boot splashscreen on it. By default, HDMI splash is selected. In order to use splash via LVDS, do the following in the U-boot prompt: setenv panel Hannstar-XGA save and reboot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-09-10ARM: mxs: Receive r0 and r1 passed from BootROMMarek Vasut
Make sure value in register r0 and r1 is preserved and passed to the board_init_ll() and mxs_common_spl_init() where it can be processed further. The value in r0 can be configured during the BootStream generation to arbitary value, r1 contains pointer to return value from CALL'd function. This patch also clears the value in r0 before returning to BootROM to make sure the BootROM is not confused by this value. Finally, this patch cleans up some comments in the start.S file. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
2013-09-09SPL: P1022DS: switch to new multibus/multiadapter supportYing Zhang
- Added section "u_boot_list" in arch/powerpc/cpu/mpc85xx/u-boot-spl.lds - Use the function i2c_init_all instead of i2c_init Signed-off-by: Ying Zhang <b40530@freescale.com>
2013-08-20powerpc/p1010rdb: fix calculating ddr_freq_mhzShengzhou Liu
There was a bug for calculating ddr_freq_mhz, it should be divided by 1000000 rather than 0x1000000. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
2013-08-20powerpc/t4240: add QSGMII interface supportShaohui Xie
Also some fix for QSGMII. 1. fix QSGMII configure of Serdes2. 2. fix PHY address of QSGMII MAC9 & MAC10 for each FMAN. 3. fix dtb for QSGMII interface. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
2013-08-20powerpc/t4240: fix lanes routing for QSGMII protocolsShaohui Xie
When using QSGMII protocols, the first lane and third lane on each slot need to be swapped. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
2013-08-20powerpc/common/vsc3316: remove const from vsc3316_config parameter defineShaohui Xie
Since the parameters need to be modified according to different Serdes protocols at runtime, the const will block this. Also remove const from arrays define used by vsc3316_config. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
2013-08-20SPDX-License-Identifier: clean up license headerYork Sun
This patch cleans up license header in these files: board/freescale/p1022ds/spl.c drivers/mmc/fsl_esdhc_spl.c drivers/mtd/spi/fsl_espi_spl.c Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-20powerpc: Fix CamelCase checkpatch warningsPrabhakar Kushwaha
85xx, 86xx PowerPC folders have code variables with CamelCase naming conventions. because of this code checkpatch script generates "WARNING: Avoid CamelCase". Convert variables name to normal naming convention and modify board, driver files with updated the new structure. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
2013-08-20powerpc: p1022ds: add TPL for p1022ds nand bootYing Zhang
TPL is introduced in the patch "NAND: TPL : introduce the TPL based on the SPL", here enable TPL for p1022ds nand boot. Signed-off-by: Ying Zhang <b40530@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
2013-08-20powerpc : p1022ds : Enable p1022ds to start from eSPI with SPLYing Zhang
Enable p1022ds to start from eSPI with SPL. Signed-off-by: Ying Zhang <b40530@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
2013-08-20powerpc: p1022ds: Enable P1022DS to boot from SD Card with SPLYing Zhang
Enable p1022ds to start from eSDHC with SPL. Signed-off-by: Ying Zhang <b40530@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
2013-08-18Merge branch 'master' of git://88.191.163.10/u-boot-armTom Rini
Fixup an easy conflict over adding the clk_get prototype and USB_OTG defines for am33xx having moved. Conflicts: arch/arm/include/asm/arch-am33xx/hardware.h Signed-off-by: Tom Rini <trini@ti.com>
2013-08-14powerpc/c29xpcie: add readme document for c29xpciePo Liu
Signed-off-by: Po Liu <Po.Liu@freescale.com>
2013-08-12powerpc/mpc85xx: Cleanup license header in source filesYork Sun
Fix the license header introduced by the following patches Add TWR-P10xx board support Add T4240EMU target IDT8T49N222A configuration code Add C29x SoC support Add support for C29XPCIE board Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09powerpc/c29xpcie: add support for C29XPCIE boardMingkai Hu
C29XPCIE board is a series of Freescale PCIe add-in cards to perform as public key crypto accelerator or secure key management module. It includes C293PCIE board, C293PCIE board and C291PCIE board. - 512KB platform SRAM in addition to 512K L2 Cache/SRAM - 512MB soldered DDR3 32bit memory - CPLD System Logic - 64MB x16 NOR flash and 4GB x8 NAND flash - 16MB SPI flash Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Singed-off-by: Po Liu <Po.Liu@freescale.com> [yorksun: Fixup include/configs/C29XPCIE.h] Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09board/b4860qds: Add support for configuring SerDes1 RefclksShaveta Leekha
1) Add support in B4860 board files for using IDT driver where IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer that generate different refclks for SerDes modules, used this driver for reconfiguring SerDes1 Refclks(based on SerDes1 protocols) for CPRI to work. CPRI works on 122.88MHz and default refclks coming on board are not suitable for it 2) Move SerDes1 refclk1 source selection from eth_b4860qds.c file to b4860qds board file, as SerDes1 Refclk1 would come from PHY MUX in case of certain protocols, that have been checked here. This change would make on board SGMIIs to work 3) Add I2C addresses for IDT8T49N222A devices in board/include file 4) Add define for PCA-I2C bus multiplexer, on which IDT devices exist Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
2013-08-09board/freescale/common: IDT8T49N222A configuration codeShaveta Leekha
Add code for configuring IDT8T49N222A device for various output refclks - The IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer with alarm and monitoring functions suitable for networking and communications applications. It is able to generate wide range of output frequencies. - In B4860QDS, it has been used to generate different refclks to SerDes modules - Programming of these devices are performed by I2C interface. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
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