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2023-10-31board: nuvuton: arbel: Fix incorrect ram sizeJim Liu
1. Fix incorrect ram size of 4GB dram with ECC enabled 2. Fix wrong place to set dram bank size - The dram bank size should be set in dram_init_banksize - Dram_init should not access gd->bd because the board info struct is not reserved yet. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> [trini: Rework slightly] Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-30Kconfig: Remove all default n/no optionsMichal Simek
Similar change was done by commit b4c2c151b14b ("Kconfig: Remove all default n/no options") and again sync is required. default n/no doesn't need to be specified. It is default option anyway. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # tegra Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Angelo Dureghello <angelo@kernel-space.org>
2023-10-27board: synquacer: Update the flash image layoutIlias Apalodimas
The SynQuacer Developerbox, in EFI mode, supports A/B capsule updates and single image ones. The flash layout in the latter case is outdated, update it with the new offsets and images Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Tested-By: Masahisa Kojima <masahisa.kojima@linaro.org>
2023-10-27board: siemens: iot2050: Fix M.2 detectionJan Kiszka
The "simpler" the logic, the higher the probability to not test and get things wrong, again: The absence of a "-PG2" suffix is not sufficient to derive that we are on PG1. There is also "IOT2050-ADVANCED-M2". Finally fix that by exactly matching against the two PG1 device names. While changing this, we can also drop the not really needed check for !board_is_sr1 in board_is_m2 and call the boards by their names ("board_is_pg1"). Reported-and-tested-by: Bao Cheng Su <baocheng.su@siemens.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2023-10-26arm: mvebu: turris_mox: Extend to support RIPE Atlas ProbeMarek Behún
Extend Turris Mox board code to support CZ.NIC's RIPE Atlas Probe. Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2023-10-24riscv: Remove common.h usageTom Rini
We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-10-24microblaze: Remove common.h usageTom Rini
We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Michal Simek <michal.simek@amd.com>
2023-10-24arc: Remove common.h usageTom Rini
We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
2023-10-24Merge tag 'u-boot-rockchip-20231024' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-rockchip - Add Board: rk3588 NanoPC-T6, Orange Pi 5, Orange Pi 5 Plus; - clk driver fix for rk3568 and rk3588; - rkmtd cmd support for rockchip nand device; - dts update and sync from linux;
2023-10-24Merge tag 'u-boot-imx-20231024' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20231024 ------------------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/18211 - Fixes for MC2432 Eeprom - i.MX93 ADC - Secondary boot mode on i.MX8M
2023-10-24board: rockchip: Add Xunlong Orange Pi 5 PlusJonas Karlman
Xunlong Orange Pi 5 Plus is a single-board computer based on the Rockchip RK3588 SoC. The board provides abundant interfaces, including two HDMI output ports, one HDMI input port, two 2.5G Ethernet ports, M.2 M-Key slot, M.2 E-Key slot, two USB 3.0, two USB 2.0, and two Type-C. Features tested on a Orange Pi 5 Plus 4GB v1.2: - SD-card boot - eMMC boot - SPI Flash boot - PCIe/NVMe - USB 2.0 host - Ethernet Device tree is imported from linux v6.7-rockchip-dts64-1 tag. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24board: rockchip: Add Xunlong Orange Pi 5Jonas Karlman
Xunlong Orange Pi 5 is a single-board computer based on the Rockchip RK3588S SoC. The board provides abundant interfaces, HDMI output, GPIO interface, M.2 PCIe2.0, Type-C, Gigabit LAN port, 2*USB2.0, 1*USB3.0, etc. Features tested on a Orange Pi 5 4GB v1.2: - SD-card boot - SPI Flash boot - PCIe/NVMe - USB 2.0 host - Ethernet Device tree is imported from linux v6.7-rockchip-dts64-1 tag. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-23ae350: Update defconfig listTom Rini
Update the list of defconfigs, this was missed with the last pull request of the u-boot-riscv tree. Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-23Merge tag 'u-boot-at91-2024.01-b' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-at91 Second set of u-boot-at91 features for the 2024.01 cycle This feature set a new board named Conclusive KSTR sama5d27 with some small prerequisites patches.
2023-10-23Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
This is mostly about support for the Allwinner R528/T113s SoC, which is reportedly the same die as the Allwinner D1, but with the two Arm Cortex-A7 cores activated instead of the RISC-V one. Using sunxi code outside of arch/arm proved to be difficult, so apart from enabling this Arm SoC, the patches also prepare for more refactoring to get the D1 nicely supported some day: - We get rid of some Kconfig (hard-)coded GPIO pins, responsible for enabling regulators. - The GPIO code is moved out of arch/arm, into drivers/gpio. - Some definitions are moved out of header files under asm/arch. - Some T113s/D1 specific definitions are guarded by a generic Kconfig symbol (CONFIG_SUNXI_GEN_NCAT2). - The DRAM controller initialisation code is located under drivers/ram. - The base SoC .dtsi files are shared (under arch/riscv, as in Linux). Of course there are also the usual new SoC specific patches, like clock and pinmux descriptions, alongside a rework of the pinctrl code, since Allwinner changed the GPIO register layout, for the first time since sunxi's inception. On top of this the PSCI code sees some update, to provide SMP services for R528/T113s boards. Many thanks to Sam for providing this code and staying strong through the review cycles. The final patch enables support for one popular board, I hope to see more DTs and defconfigs contributed in the future! Many thanks to all the various contributors, testers and reviewers, that series was a real team effort!
2023-10-23board: Add support for Conclusive KSTR-SAMA5D27Artur Rojek
Introduce support for Conclusive KSTR-SAMA5D27 Single Board Computer. Co-developed-by: Jakub Klama <jakub@conclusive.pl> Signed-off-by: Jakub Klama <jakub@conclusive.pl> Co-developed-by: Marcin Jabrzyk <marcin@conclusive.pl> Signed-off-by: Marcin Jabrzyk <marcin@conclusive.pl> Signed-off-by: Artur Rojek <artur@conclusive.pl>
2023-10-23board: rockchip: add FriendlyElec NanoPC-T6 rk3588 boardJohn Clark
The NanoPC-T6 is a Rockchip RK3588 based SBC by FriendlyElec. There are four variants depending on the DRAM size: 4G/32GB eMMC, 8G/64GB eMMC, 16G/16MB SPI NOR, and 16G/256GB eMMC/16MB SPI NOR Specifications: CPU: Rockchip RK3588, 4x Cortex-A76 (up to 2.4GHz) + 4x Cortex-A55 (up to 1.8GHz) GPU: Mali-G610 MP4 VPU: 8K@60fps H.265 and VP9 decoder, 8K@30fps H.264 decoder, 4K@60fps AV1 decoder, 8K@30fps H.264 and H.265 encoder NPU: 6TOPs, supports INT4/INT8/INT16/FP16 RAM: 64-bit 4GB/8GB/16GB LPDDR4X at 2133MHz eMMC: 0GB/32GB/64GB/256GB HS400 MicroSD Slot: MicroSD SDR104 PCIe 3.0: M.2 M-Key x1, PCIe 3.0 x4 for NVMe SSDs up to 2,500 MB/s Ethernet: PCIe 2.5G 2x Ethernet (RTL8125BG) PCIe 2.1: M.2 E-Key x1, PCIe 2.1 x1 and USB2.0 Host, supports M.2 WiFi and Bluetooth 4G Module: MiniPCIe x1, MicroSIM Card Slot x1 Audio Out: 3.5mm jack for stereo headphone output Audio In: 2.0mm PH-2A connector for analog microphone input Video Input: standard HDMI input port, up to 4Kp60 2x 4-lane MIPI-CSI, compatible with MIPI V1.2 Video Output: 2x standard HDMI output ports compatible with HDMI2.1, HDMI2.0, and HDMI1.4 2x 4-lane MIPI-DSI, compatible with MIPI DPHY 2.0 or CPHY 1.1 USB-A: USB 3.0, Type A USB-C: Full function USB Type‑C port, DP display up to 4Kp60, USB 3.0 40-pin 2.54mm header connector: up to 2x SPIs, 6x UARTs, 1x I2Cs, 8x PWMs, 2x I2Ss, 28x GPIOs Debug UART: 3 Pin 2.54mm header, 3V level, 1500000bps Onboard IR receiver: 38KHz carrier frequency RTC Battery: 2 Pin 1.27/1.25mm RTC battery connector for low power RTC IC HYM8563TS 5V Fan connector Working Temperature: 0C to 70C Power: 5.5*2.1mm DC Jack, 12VDC input Dimensions: 110x80x1.6mm (without case) / 86x114.5x30mm (with case) Kernel commits: 893c17716d0c ("arm64: dts: rockchip: Add NanoPC T6") a721e28dfad2 ("arm64: dts: rockchip: Add NanoPC T6 PCIe Ethernet support") ac76b786cc37 ("arm64: dts: rockchip: Add NanoPC T6 PCIe e-key support") Signed-off-by: John Clark <inindev@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-22sunxi: R528: add SMHC2 pin pull ups supportOkhunjon Sobirjonov
Add support for eMMC (SMHC2) pin pull ups for R528 boards. The D1 and T113s (and even R329) SoCs do not support 8-bit eMMC anymore, so it's just four data pins to cover here. Signed-off-by: Okhunjon Sobirjonov <Okhunjon.Sobirjonov@Mec-electronics.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: adjust commit message] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22pinctrl: sunxi: remove GPIO_EXTRA_HEADERAndre Przywara
U-Boot's generic GPIO_EXTRA_HEADER is a convenience symbol to allow code to more easily include platform specific GPIO headers. This should not be needed in a DM world anymore, since the generic GPIO framework handles that nicely. For Allwinner boards we still need to deal with non-DM GPIO in the SPL, but this should become the exception, not the rule. Make this more obvious by removing the definition of GPIO_EXTRA_HEADER, and just force every legacy user of platform specific GPIO to include the new sunxi_gpio.h header explicitly. Everyone doing so should feel ashamed and should find a way to avoid it from now on. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Samuel Holland <samuel@sholland.org>
2023-10-22sunxi: remove CONFIG_MACPWRAndre Przywara
The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables the power for the Ethernet "MAC" (mostly PHY, really). In the DT this is described with the phy-supply property in the MAC DT node, pointing to a (GPIO controlled) regulator. Since we need Ethernet only in U-Boot proper, and use a DM driver there, we should use the DT instead of hardcoding this. Add code to the sun8i_emac and sunxi_emac drivers to check the DT for that regulator and enable it, at probe time. Then drop the current code from board.c, which was doing that job before. This allows us to remove the MACPWR Kconfig definition and the respective values from the defconfigs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Sam Edwards <CFSworks@gmail.com>
2023-10-22sunxi: remove CONFIG_SATAPWRAndre Przywara
The CONFIG_SATAPWR Kconfig symbol was used to point to a GPIO that enables the power for a SATA harddisk. In the DT this is described with the target-supply property in the AHCI DT node, pointing to a (GPIO controlled) regulator. Since we need SATA only in U-Boot proper, and use a DM driver for AHCI there, we should use the DT instead of hardcoding this. Add code to the sunxi AHCI driver to check the DT for that regulator and enable it, at probe time. Then drop the current code from board.c, which was doing that job before. This allows us to remove the SATAPWR Kconfig definition and the respective values from the defconfigs. We also select the generic fixed regulator driver, which handles those GPIO controlled regulators. Please note that the OrangePi Plus is a bit special here, it's a H3 board without native SATA, but with a USB-to-SATA bridge. The DT models the SATA power via a VBUS supply regulator, which we don't parse yet in the USB PHY driver. Use the hardcoded CONFIG_USB3_VBUS_PIN for that board meanwhile. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
2023-10-19riscv: spl: andes: Move the DTB in front of kernelRandolph
Originally, u-boot SPL will place the DTB directly after the kernel, but the size of the kernel does not include the BSS section, This means that u-boot SPL places the DTB in the kernel BSS section causing the DTB to be cleared by the kernel BSS initialisation. Moving the DTB in front of the kernel can avoid this error. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-17spl: mmc: Introduce proper layering for spl_mmc_get_uboot_raw_sector()Marek Vasut
Introduce two new weak functions, arch_spl_mmc_get_uboot_raw_sector() and board_spl_mmc_get_uboot_raw_sector(), each of which can be overridden at a matching level, that is arch/ and board/ , in addition to the existing weak function spl_mmc_get_uboot_raw_sector(). This way, architecture code can define a default architecture specific implementation of arch_spl_mmc_get_uboot_raw_sector(), while the board code can override that using board_spl_mmc_get_uboot_raw_sector() which takes precedence over the architecture code. In some sort of unlikely special case where code has to take precedence over board code too, the spl_mmc_get_uboot_raw_sector() is still left out to be a weak function, but it should be unlikely that this is ever needed to be overridden. Signed-off-by: Marek Vasut <marex@denx.de>
2023-10-17Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-shTom Rini
- RZ/G2L part 1, except for two serial port patches which I had to drop as they broke R2Dplus, they will come later via subsequent PR.
2023-10-17board: rzg2l: Add RZ/G2L SMARC EVK boardPaul Barker
The Renesas RZ/G2L SMARC Evaluation Board Kit consists of the RZ/G2L System-on-Module (SOM) based on the R9A07G044L2 SoC, and a common SMARC carrier board. The ARM TrustedFirmware code for the Renesas RZ/G2L SoC family passes a devicetree blob to the bootloader as an argument in the same was previous R-Car gen3/gen4 SoCs. This blob contains a compatible string which can be used to identify the particular SoC we are running on and this is used to select the appropriate device tree to load. The configuration renesas_rzg2l_smarc_defconfig is added to support building for this target. In the future this defconfig will be extended to support other SoCs and evaluation boards from the RZ/G2L family. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-16Merge tag 'u-boot-imx-20231016' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20231016 ------------------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/18168 - Imrovement MX93 - Toradex: fixes - Convert to DM (serial, watchdog) for some boards - HAB improvements for Secure Boot - DTO overlay for DHCOM - USB fixes, Mass storage for MX28 - Cleanup some code - Phytec MX8M : EEProm detection, fixes - Gateworks Boards improvements
2023-10-16Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- dns325: Enable 2nd harddrive (Peter & Stefan) - marvell: cn9310-crb: Misc fixes to SPI / pincntrl in DTS (Chris) - kirkwood: Add support for ZyXEL NSA325 board (Tony) - sata_mv: Add bootstd hook to enable sata_bootdev (Tony) - x240/AC5/AC5X: Disable SMBIOS (Chris) - Revert "arm: mvebu: x240: Use i2c-gpio instead of built in controller" (Chris) - DS116/N2350: Enable bootstd (Tony) - clearfog: Support multiple DDR sizes (Josua)
2023-10-16imx93_evk: defconfig: enable clock driverSébastien Szymanski
Add clocks nodes in u-boot.dtsi file. Remove init_uart_clk() call. Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2023-10-16arm64: dts: imx8mp: Add DT overlay describing i.MX8MP DHCOM SoM rev.100Marek Vasut
The current imx8mp-dhcom-som.dtsi describes production rev.200 SoM, add DT overlay which reinstates rev.100 SoM description to permit prototype rev.100 SoMs to be used until they get phased out. Signed-off-by: Marek Vasut <marex@denx.de>
2023-10-16arm64: dts: imx8mp: Switch to DT overlays for i.MX8MP DHCOM SoMMarek Vasut
Add DT overlays to support additional DH i.MX8MP DHCOM SoM 660-100 population options with 1x or 2x RMII PHY mounted on PDK2 or PDK3 carrier boards. Use SPL DTO support to apply matching SoM specific DTO to cater for the SoM differences. Remove ad-hoc patching of control DT from fdtdec_board_setup(). Signed-off-by: Marek Vasut <marex@denx.de>
2023-10-16cmd: Convert existing long help messages to the new macroTom Rini
- Generally we just drop the #ifdef CONFIG_SYS_LONGHELP and endif lines and use U_BOOT_LONGHELP to declare the same variable name as before - In a few places, either rename the variable to follow convention or introduce the variable as it was being done inline before. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-16eeprom: starfive: add 'mac raw' commandHeinrich Schuchardt
Add a sub-command to print a hexdump of the EEPROM content. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-10-16eeprom: starfive: raw dump if unsupported data versionHeinrich Schuchardt
If the data version field of the EEPROM is not supported, provide a hexdump of the data. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-10-16eeprom: starfive: re-implement mac commandHeinrich Schuchardt
The different implementations of the mac command have board or vendor specific sub-commands. Add the command definition specific to the VisionFive 2 board. Don't call cmd_usage() directly but return CMD_RET_USAGE instead. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-10-16eeprom: SiFive Unmatched: re-implement mac commandHeinrich Schuchardt
The different implementations of the mac command have board or vendor specific sub-commands. Add the command definition specific to the SiFive HiFive Unmatched board. Don't call cmd_usage() directly but return CMD_RET_USAGE instead. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-10-16freescale: fix long help handling in mac commandHeinrich Schuchardt
CONFIG_SYS_LONGHELP=n we want to reduce the size of the U-Boot binary. The long text should be reduced to and empty string in this case. There is not need to call cmd_usage() directly. It is sufficient to return CMD_RET_USAGE. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-10-16cmd: move mac commandHeinrich Schuchardt
Board specific implementations of the 'mac' command differ concerning the supported sub-commands. Move the Freescale specific mac command definition to the board code. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-10-16arm: mvebu: clearfog: support 512MB memory size from tlv eepromJosua Mayer
Handle 2GBit memory size value "2" from tlv eeprom on ddr initialisation, to support SoMs with 512MB ddr memory. Signed-off-by: Josua Mayer <josua@solid-run.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-10-16arm: mvebu: clearfog: read number of ddr channels from tlv dataJosua Mayer
Extend the existing tlv vendor extension used for ram size by one byte to also store the number of ddr channels. The length of the tlv entry can indicate whether the new information is present. If not default to single channel. Signed-off-by: Josua Mayer <josua@solid-run.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-10-16board: phytec: phycore_imx8mp: Add 4000MTS RAM timings based on PCB revTeresa Remmet
Starting with PCB revision 3 we can safely make use of higher RAM frequency again. Make use of the EEPROM detection to determine the revision and use the updated RAM timings for new SoMs. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Yannic Moog <y.moog@phytec.de> Tested-by: Yannic Moog <y.moog@phytec.de>
2023-10-16board: phytec: phycore-imx8mp: Add EEPROM detection initialisationTeresa Remmet
Add EEPROM detection initialisation for phyCORE-i.MX8MM and print SoM information during boot when successful. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Yannic Moog <y.moog@phytec.de> Tested-by: Yannic Moog <y.moog@phytec.de>
2023-10-16board: phytec: common: phytec_som_detection: Add helper for PCB revisionTeresa Remmet
Add helper function to read out the PCB revision of a PHYTEC SoM. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Yannic Moog <y.moog@phytec.de> Tested-by: Yannic Moog <y.moog@phytec.de>
2023-10-16board: phytec: phycore_imx8mp: Update 2GB RAM TimingsTeresa Remmet
Due to PCB layout constraints in PCB revisions until including 1549.2, a RAM frequency of 2 GHz can cause rare instabilities. Set the RAM frequency to 1.5 GHz to achieve a stable system under all conditions. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Yannic Moog <y.moog@phytec.de> Tested-by: Yannic Moog <y.moog@phytec.de>
2023-10-16board: phytec: common: Add imx8m specific EEPROM detection supportTeresa Remmet
Add imx8m specific detection part. Which includes checking the EEPROM data for article number options. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Yannic Moog <y.moog@phytec.de> Tested-by: Yannic Moog <y.moog@phytec.de>
2023-10-16board: phytec: Add common PHYTEC SoM detectionTeresa Remmet
Recent shipped PHYTEC SoMs come with an i2c EEPROM containing information about the hardware such as board revision and variant. This can be used for RAM detection and loading device tree overlays during kernel start. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Yannic Moog <y.moog@phytec.de> Tested-by: Yannic Moog <y.moog@phytec.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-10-16arm: kirkwood: Add support for ZyXEL NSA325 boardTony Dinh
ZyXEL NSA325 specifications: Marvell Kirkwood 88F6282 SoC 1.6 GHz CPU 1x GBE LAN port (Marvell MV88E1318) 512 MB RAM 128 MB Eon NAND, SLC I2C 1x USB 3.0 (on PCIe bus) 2x USB 2.0 2x SATA (hot swap slots) Serial console Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-10-16kirkwood: dns325: Enable 2nd harddriveStefan Roese
The 2nd HD is not enabled in U-Boot on the D-Link DNS325. This patch sets the responsible GPIO to high, enabling the drive. Suggested-by: Peter Granilla Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tony Dinh <mibodhi@gmail.com>
2023-10-16smegw01: Remove misuse of CONFIG_ENV_IS_NOWHEREEduard Strehlau
When using a list of writeable variables, the initial values come from the built-in default environment since commit 5ab81058364b ("env: Complete generic support for writable list"). Remove unnecessary misuse of CONFIG_ENV_IS_NOWHERE as default environment. Based on the fix done by commit b16fd7f75f6d ("imx6q: acc: Remove misuse of env is nowhere driver"). Signed-off-by: Eduard Strehlau <eduard@lionizers.com> Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-10-16toradex: colibri_imx7: Enable nand/emmc detection and set boot variantHiago De Franco
Add detection of eMMC vs NAND devices on the Colibri iMX7 board. A GPIO is configured to detect the presence of an on-board resistor that is configured differently based on the flash memory used. Depending on the detection result, the 'variant' environment variable is set to '-emmc' or cleared, indicating the type of storage device. This enhancement improves variant detection during system initialization through USB recovery mode, where U-Boot is loaded directly to RAM. This allows variant detection for an accurate device tree selection. Signed-off-by: Hiago De Franco <hiago.franco@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-10-16board: toradex: verdin-imx8mm: set fixed LPDDR4 refresh rate as per errata ↵Andrejs Cainikovs
ERR050805 Update lpddr4 configuration and training using updated spreadsheet and tools from NXP using data from previous spreadsheet and verified toward datasheet: - MX8M_Mini_LPDDR4_RPA_v22.xlsx - mscale_ddr_tool_v3.31_setup.exe The most relevant update is related to errata ERR050805: "DRAM: Controller automatic derating logic may not work when the LPDDR4 memory temperature is above 85 °C at initialization" Other relevant fixes: - DRAMTMG7 register: corrected calculation of T_CKPDX parameter (equal to tCKCKEH for LPDDR4) - RANKCTL register: corrected calculations for ODTLon and ODTLoff to follow the JEDEC specification - ADDRMAP7 register: added support for 17-row devices As per errata ERR050805: An issue exists with the automatic derating logic of the DDR controller that only samples the LPDDR4 MR4 register when the Temperature Update Flag (TUF) field (MR4[7] ) is 1’b1. If the LPDDR4 memory is initialized and starts operation above 85 °C (MR4[2:0] > 3’b011), the MR4 Temperature Update Flag (TUF) will not be set. The DDR Controller will therefore not automatically adjust the memory refresh rate or de-rate memory timings based on the LPDDR4 memory temperature. This may cause the controller incorrectly setting the refresh period, potentially cause the LPDDR4 memory losing data contents and lead to possible data integrity issues above 85 °C. Errata provides three possible workaround options, while option 2 is the most reasonable: Disable the automatic derating logic of the DDR controller and apply fixed x2 refresh rate (0.5x refresh). This option is suitable for designs that are expected to boot at or above 85 °C and memory’s MR4[2:0] (Refresh Rate) DOES NOT report the following conditions: 3b101: 0.25x refresh, no de-rating 3b110: 0.25x refresh, with de-rating 3b111: SDRAM High temperature operating limit exceeded [1]: https://www.nxp.com/docs/en/errata/IMX8MM_0N87W.pdf Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
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