Age | Commit message (Collapse) | Author |
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Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
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Signed-off-by: Heiko Schocher <hs@denx.de>
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Signed-off-by: Heiko Schocher <hs@denx.de>
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Signed-off-by: Heiko Schocher <hs@denx.de>
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The TK885D board uses a TQM885D module from TQ, this port adds an
own configuration file and adds a last_stage_init() method to
configure the two PHYs, depending on the phy_auto_nego environment
variable.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
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Clear possible errors in MCSR resulting from data-eye-search.
If not done, then we could get an interrupt later on when
exceptions are enabled.
Signed-off-by: Stefan Roese <sr@denx.de>
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Rework Lime support for lwmon5 using new video driver
Signed-off-by: Anatolij Gustschin <agust@denx.de>
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Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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This is MPC8360E based board with:
- 256MB fixed SDRAM;
- 8MB Intel Strata NOR flash;
- StMICRO 64MiB NAND flash;
- two 10/100/1000 ethernet ports connected via Broadcom
BCM5481 PHYs;
- two 10/100 ethernet ports connected via National
DP83848 PHYs;
- one PCI and one miniPCI slots;
- four serial ports (two NS16550-compatible, two UCCs);
- four USB ports working through MPC8360E "FHCI" USB controller;
- Fujitsu MB86277 graphics controller;
- Analog to Digital Converter/Touchscreen controller, AD7843
connected to SPI.
Features not supported in this patch are:
- StMICRO 64MiB NAND flash (patch sent);
- MINT framebuffer initialization (patch is pending);
- Fetching production information from the EEPROM via I2C;
- FHCI USB;
- Two slow UCCs used as RS-485 UARTs.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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vxWorks expects in
TLB 0 a entry for the Machine Check interrupt
TLB 1 a entry for the RAM
TLB 2 a entry for the EBC
TLB 3 a entry for the boot flash
After changing the baudrate to 9600 I had no problems to boot the
vxWorks image as distributed by WindRiver (Revision 2.0/1 from
June 18, 2007)
Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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Add support for Instituto Atlantico's ATUM8548 board
Signed-off-by: robert lazarski <robertlazarski@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Add support for Instituto Atlantico's ATUM8548 board
Signed-off-by: robert lazarski <robertlazarski@gmail.com>
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Add support for Wind River's SBC8548 reference board.
Signed-off by: Joe Hamman <joe.hamman@embeddedspecialties.com>
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Add support for Wind River's SBC8548 reference board.
Signed-off by: Joe Hamman <joe.hamman@embeddedspecialties.com>
Signed-off by: Andy Fleming <afleming@freescale.com>
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To use UART1 on the MPC8568E-MDS, QE pario pins PC[0:3] should
be set up appropriately.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
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In order to use GETH1 and GETH2 on the MPC8568E-MDS, we should reset
UCCs.
p.s Similar code exists in the Linux kernel board file (for capability
reasons with older U-Boots), but should be removed some day.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
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The old macros made it difficult to know what WIMGE and perm bits
were set for a TLB entry. Actually use the bit masks for these items
since they are only a single bit.
Also moved the macros into mmu.h out of e500.h since they aren't specific
to e500.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
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Assumes the presence of the aliases node in the DTS to
locate the pci and serial nodes for fixups.
Use consistent fdtaddr and fdtfile in environment variables.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
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Turn off DEBUG.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
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Conflicts:
board/tqm5200/tqm5200.c
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This patch removes the FPGA subsystem configuration through
the CONFIG_FPGA bitmask configuration option.
See README for the new options:
CONFIG_FPGA,
CONFIG_FPGA_<vendor>,
CONFIG_FPGA_<family>
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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This patch configures the LWMON5 port to use d-cache as init-ram and
the unused GPT0_COMP6 as POST WORD storage.
Signed-off-by: Stefan Roese <sr@denx.de>
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Some operating systems rely on assigned PCI interrupts.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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This patch updates the PLB/PCI divider when running at
400MHz CPU frequency from 4 to 3 which results in 44MHz PCI sync clock.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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..in board pci.c files
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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need to rm it from pci code, too!
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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convert to using simpler mpc85xx style fdt update code; streamline by
eliminating macros OF_SOC, OF_CPU, etc. which allows us to rm
the old school FLAT_TREE code from 83xx (since the sbc8349 was just
converted over to using libfdt).
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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This adds libfdt support code for the Wind River sbc8349 board.
Parallel of commit 3fde9e8b22cfbd7af489214758f9839a206576cb for
the other Freescale 83xx boards.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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ECC code is now shared for all 83xx boards, so remove board specific one.
See commit daab8c67d2defef73dc26ab07f0c3afd1b05d019 for reference.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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mpc8360emds.c: In function ‘ft_board_setup’:
mpc8360emds.c:335: warning: assignment discards qualifiers from pointer target type
mpc8360emds.c:345: warning: assignment discards qualifiers from pointer target type
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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rename to fdt_path_offset
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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u-boot itself uses GMII mode on the 8360. Fix up UCC phy-connection-type
properties in the device tree so the PHY gets configured for internal delay on
RX only by the OS, as prescribed by mpc8360 rev. 2.1 pb mds erratum #2.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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The MPC837xEMDS board support:
* DDR2 400MHz hardcoded and SPD init
* Local bus NOR Flash
* I2C, UART, MII and RTC
* eTSEC RGMII
* PCI host
Signed-off-by: Dave Liu <daveliu@freescale.com>
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Despite user manual, BCSR9.7 is negated (high) on HRST, so
UART2 is disabled. Fix that and configure QE pins properly.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
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On Katmai the complete auto-calibration somehow doesn't seem to
produce the best results, meaning optimal values for RQFD/RFFD.
This was discovered by GDA using a high bandwidth scope,
analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
so now on Katmai "only" RFFD is auto-calibrated.
This patch also adds RDCC calibration as mentioned on page 7 of
the AMCC PowerPC440SP/SPe DDR2 application note:
"DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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