u-boot.git - U-Boot bootloader

Age	Commit message (Collapse)	Author
2024-04-22	configs: Resync with savedefconfig	Tom Rini
	Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2024-03-01	riscv: mbv: Enable SPL and binman	Michal Simek
	Enable SPL and binman to generate u-boot.img (machine mode) and u-boot.itb (supervisor mode). DTB is placed at fixed address to ensure that it is 8 byte aligned which is not ensured when dtb is attached behind SPL binary that's why SPL and U-Boot are taking DTB from the same address. Also align addresses for both defconfigs. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/85506bce5580d448f095f267d029e3932c5e9990.1707911544.git.michal.simek@amd.com
2024-03-01	riscv: mbv: Switch to OF_SEPARATE with fixed address	Michal Simek
	Hardcode DTB address to specific address. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/a5ad3c8d21be311254dd950e4e322d13cacdc176.1707911544.git.michal.simek@amd.com
2024-03-01	riscv: mbv: Enable REMAKE_ELF by default	Michal Simek
	Create also u-boot.elf out of u-boot ELF. It is better to align it with other Xilinx SOC where u-boot.elf also exists and tools like bootgen works only with files with .elf extension. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/50bc5a360c37accd0eee1eecfd291b145a29acd0.1707911544.git.michal.simek@amd.com
2024-03-01	riscv: mbv: Align addresses with default DT	Michal Simek
	Better to align everything with memory map described in DT to avoid mistakes. Execute both modes form the same address to make address map more understandable. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/be54c668d5626ccd702507a86c2a95d1eaefc690.1707911544.git.michal.simek@amd.com
2023-12-18	riscv: Add support for AMD/Xilinx MicroBlaze V	Michal Simek
	MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. It is hardware compatible with classic MicroBlaze processor. The patch contains initial wiring and configuration for initial HW design with memory, cpu, interrupt controller, timers and uartlite console (interrupt controller is listed but U-Boot is not using it). Provided DT is just describing one configuration and should be taken only as example. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>