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path: root/drivers/clk
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2019-10-08ARM: at91: Rename sama5_sfr.h to at91_sfr.hTudor Ambarus
The Special Function Registers (SFR) are present in sam9x5 and sam9x60 too, rename sama5_sfr to at91_sfr.h. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-09-11rockchip: clk: rk3399: remove clk_enable()Kever Yang
There is no real driver for clk enable/disable now, and we actually don't need it now, remove it so that not waste CPU cycles and code size. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11rockchip: clk: rk3368: remove clk_enable()Kever Yang
There is no real driver for clk enable/disable now, and we actually don't need it now, remove it so that not waste CPU cycles and code size. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11rockchip: clk: rk3328: remove clk_enable()Kever Yang
There is no real driver for clk enable/disable now, and we actually don't need it now, remove it so that not waste CPU cycles and code size. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11rockchip: clk: rk3288: remove clk_enable()Kever Yang
There is no real driver for clk enable/disable now, and we actually don't need it now, remove it so that not waste CPU cycles and code size. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-05clk: aspeed: Add support for SD clockEddie James
Add code to enable the SD clock on the ast2500 SoC. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Eddie James <eajames@linux.ibm.com>
2019-08-29Merge tag 'u-boot-amlogic-20190828' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - add missing g12b clock driver compatible, fixing odroid-n2 usb support
2019-08-28clk: meson-g12b: add compatibleMark Kettenis
The G12B clock controller is almost identical to the G12A and so far the differences don't matter. Adding the G12B compatible makes USB work on the Odroid-N2. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-08-27stm32mp1: clk: use gd to store frequency informationPatrick Delaunay
Use existing gd structure to store frequency information which can be used in drivers or arch without new request. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: clk: remove debug tracesPatrick Delaunay
Remove many debug trace. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-26Kconfig: Varios: Fix more SPL, TPL dependenciesAdam Ford
Several options are presenting themselves on a various boards where the options are clearly not used. (ie, SPL/TPL options when SPL or TPL are not defined) This patch is not attempting to be a complete list of items, but more like low hanging fruit. In some instances, I wasn't sure of DM was required, so I simply made them SPL or TPL. This patch attempts to reduce some of the menuconfig noise by defining dependencies so they don't appear when not used. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-08-24Merge tag 'u-boot-rockchip-20190823' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - remove rk3288 fennec board - remove SPL raw image support for Rockchip SoCs - add common misc_init_r() for ethaddr from cpuid - enable USB HOST support for rk3328 - unify code for finding a valid gpt in part driver
2019-08-23rockchip: clk: rk3328: add clk_enable ops for HCLK_HOST0Kever Yang
Required to successfully probe the ehci generic driver Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-22clk: imx: add i.MX8MM clk driverPeng Fan
Add i.MX8MM clk driver support. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22clk: imx: add i.MX8M composite clk supportPeng Fan
Import i.MX8M composite clk from Linux Kernel 5.3.0-rc2 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22clk: imx: add pll14xx driverPeng Fan
Add pll14xx driver for i.MX8MM usage, modifed from Linux Kernel 5.3.0-rc1 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22clk: imx: expose CCF entry for allPeng Fan
Expose CCF entry, then we could avoid expand the SoC support list Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22sandbox: clk: add clk enable/disable test codePeng Fan
Since we added clk enable_count and prograte clk child enabling operation to clk parent, so add a new function sandbox_clk_enable_count to get enable_count for test usage. And add test code to get the enable_count after we enable/disable the device clk. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22clk: prograte clk enable/disable to parentPeng Fan
On i.MX8MM, thinking such as clk path OSC->PLL->PLL GATE->CCM ROOT->CCGR GATE->Device Only enabling CCGR GATE is not enough, we also need to enable PLL GATE to make sure the clk path work. So when enabling CCGR GATE, we could prograte to enabling PLL GATE to make life easier. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22clk: introduce enable_countPeng Fan
As what Linux Kernel 5.3.0 provides when enable/disable clk, there is an enable_count in clk_core_disable/enable. Introduce enable_count to track the clk enable/disable count when clk_enable/disable for CCF. And Initialize enable_count to 0 when register the clk. And clk tree dump with enable_count will be supported, it will be easy for us to check the clk status with enable_count Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-12clk: add support for clk_is_match()Sekhar Nori
Add support for clk_is_match() which is required to know if two clock pointers point to the same exact physical clock. Also add a unit test for the new API. Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-09clk: renesas: Add R8A77980 V3H clock tablesMarek Vasut
Import R8A77980 V3H clock tables from Linux 5.2.7 , commit 5697a9d3d55f. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-08-07clk: MediaTek: add hifsys entry for MT7623 SoC.Ryder Lee
This adds high speed interface subsystem - hifsys (i.e. PCIe and USB) for MT7623 SoC and enables its reset controller. The control block is shared with ethsys and accordingly rename the related defines. Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
2019-08-02Merge https://gitlab.denx.de/u-boot/custodians/u-boot-clkTom Rini
- Port more CCF code to work with i.MX8 devices.
2019-07-31clk: meson: remove duplicate logicHeinrich Schuchardt
First thing we check in meson_clk_set_rate_by_id() is current_rate == rate. There is not need to check it again. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-07-31clk: sandbox: add composite clkPeng Fan
Add composite clk to sandbox driver Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31clk: gate: support sandboxPeng Fan
Introduce io_gate_val for sandbox clk gate test usage Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31clk: add composite clk supportPeng Fan
Import clk composite clk support from Linux Kernel 5.1-rc5 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31dm: clk: ignore default settings when node not validPeng Fan
When the device not binded with a node, we need ignore the parents and rate settings. Cc: Simon Glass <sjg@chromium.org> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31clk: imx: gate2 add set ratePeng Fan
Add set rate for imx clk-gate2 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31clk: imx: import clk heplersPeng Fan
Import some clk helpers from Linux Kernel for i.MX8MM usage Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31clk: fixed_rate: export clk_fixed_ratePeng Fan
Export the structure for others to use. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31clk: divider set rate supporrtPeng Fan
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31clk: add clk-gate supportPeng Fan
Import clk-gate support from Linux Kernel 5.1-rc5 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31clk: mux: add set parent supportPeng Fan
Add set parent support for clk mux Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31clk: use clk_dev_bindedPeng Fan
Preparing to support composite clk. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31clk: introduce clk_dev_bindedPeng Fan
When support Clock Common Framework, U-Boot use dev for clk tree information, there is no clk->parent. When support composite clk, it contains mux/gate/divider, but the mux/gate/divider is not binded with device. So we could not use dev_get_uclass_priv to get the correct clk_mux/gate/divider. So add clk_dev_binded to let choose the correct method. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-29Merge tag 'u-boot-rockchip-20190729' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Clean up and migrate to use common rockchip spl board file - Clean up and migrate to use common rockchip board file - Increase rk3288 CONFIG_SYS_BOOTM_LEN to 16MB
2019-07-29rockchip: rk3188: init CPU freq in clock driverKever Yang
Init CPU frquency in clock driver instead of in SPL board file, this will help for use common board file later. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-27Merge tag 'u-boot-imx-20190719' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20190719 - CCF for i.MX6 - nandbcb command to write SPL into NAND - Switch to DM (i.MX28) - Boards: Toradex, engicam, DH - Fixes for i.MX8 - Fixes for i.MX7ULP Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/561147504
2019-07-24clk: initialize clk->data when using default xlateSekhar Nori
Right now when using clk_of_xlate_default(), clk->data remains un-initialized because clk_get_bulk() does not initialize memory on allocation of clock structure. This can cause problems when data is used to match if two clocks pointers are exactly the same underlying clocks, for example. Fix it by initializing clk->data to 0. Suggested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-07-23Merge tag 'u-boot-stm32-20190723' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - add rtc driver for stm32mp1 - add remoteproc driver for stm32mp1 - use kernel qspi compatible string for stm32
2019-07-22clk: stm32mp1: Add RTC clock entryPatrick Delaunay
Add RTCAPB and RTC clock support. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-21Merge tag 'rockchip-for-v2019.07' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - rk3399 lpddr4 support - rk3399-rock960 board support improvement - Eliminate pyelftools dependency by make_fit_atf.py - clean up rockchip dts to use -u-boot.dtsi - use ARM arch/generic timer instead of rk_timer - clean up Kconfig options for board support
2019-07-21clk: rockchip: rk3399: Set 400MHz ddr clockJagan Teki
Add support for setting 400MHz ddr clock. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21clk: rockchip: rk3399: Set 50MHz ddr clockJagan Teki
Add support for setting 50MHz ddr clock. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19clk: sandbox: Add sandbox test code for Common Clock Framework [CCF]Lukasz Majewski
This patch provides code to implement the CCF clock tree in sandbox. It uses all the introduced primitives; some generic ones are reused, some sandbox specific were developed. In that way (after introducing the real CCF tree in sandbox) the recently added to clk-uclass.c: clk_get_by_id() and clk_get_parent_rate() are tested in their natural work environment. Usage (sandbox_defconfig and sandbox_flattree_defconfig): ./u-boot --fdt arch/sandbox/dts/test.dtb --command "ut dm clk_ccf" Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19clk: sandbox: Adjust clk-mux.c to emulate reading divider value from HWLukasz Majewski
The generic mux clock code for CCF requires reading the clock multiplexer value from HW registers. As sandbox by design has readl() as no-op it was necessary to provide this value in the other way. The new field in the mux structure (accessible only when sandbox is run) has been introduced for this purpose. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19clk: sandbox: Adjust clk-divider to emulate reading its value from HWLukasz Majewski
The generic divider clock code for CCF requires reading the divider value from HW registers. As sandbox by design has readl() as no-op it was necessary to provide this value in the other way. The new field in the divider structure (accessible only when sandbox is run) has been introduced for this purpose. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19dm: clk: Extend clk_get_parent_rate() to support CLK_GET_RATE_NOCACHE flagLukasz Majewski
If the CLK_GET_RATE_NOCACHE flag is set - the clk_get_parent_rate() provides recalculated clock value without considering the cache setting. This may be necessary for some clocks tightly coupled with power domains (i.e. imx8), and prevents from reading invalid cached values. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
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