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2018-03-05clk: renesas: Add R8A77965 M3N entriesMarek Vasut
Add entries for the R8A77965 M3N SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-02-24rockchip: clk: rk3399: handle set_rate/get_rate for PLL_PPLLPhilipp Tomsich
The device-tree node for the PMU clk controller assigns to its parent (i.e. PLL_PPLL) even though this clock currently is set up statically by an init-function. In order to avoid unexpected failures, a simple implementation of set_rate (which accepts requests, but notifies the caller of the preset frequency in its return value) and get_rate (which always returns the preset frequency) are added. Note that this is required for the RK808 PMIC to probe successfully on the RK3399-Q7, following the support for the assigned-clocks property. References: commit f4fcba5c5baa ("clk: implement clk_set_defaults()") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2018-02-24rockchip: clk: rk3368: handle clk_enable requests for GMACPhilipp Tomsich
Since commit ba1f96672522 ("net: designware: add clock support"), the designware GMAC driver enables all referenced clocks. While this is a no-op for the RK3368 during boot-up (reset behaviour has all the clock gates open anyway), we still need to handle the clock-ids passed in the enable op of the clock-driver and return a success. This change extends the RK3368 clk driver to: (a) provide a enable op (b) signals success to the caller when the clocks for the GMAC are enabled (no actual action is necessary as the gates are open after reset) References: commit ba1f96672522 ("net: designware: add clock support") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2018-02-24rockchip: clk: rk3399: handle clk_enable requests for GMACPhilipp Tomsich
Since commit ba1f96672522 ("net: designware: add clock support"), the designware GMAC driver enables all referenced clocks. While this is a no-op for the RK3399 during boot-up (reset behaviour has all the clock gates open anyway), we still need to handle the clock-ids passed in the enable op of the clock-driver and return a success. This change extends the enable-op of the rk3399 clk driver to signal success to the caller when the clocks for the GMAC are enabled. References: commit ba1f96672522 ("net: designware: add clock support") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2018-02-16clk: rmobile: Assure SD-IF clock are configured correctlyMarek Vasut
The SD driver calls clk_set_rate() before clk_enable(), yet clk_set_rate() implementation in the clock driver does not set the SD-IF divider. Fix it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-29clk: clk_stm32: Add .set_rate callbackPatrice Chotard
Since 'commit f4fcba5c5baa ("clk: implement clk_set_defaults()")' STM32F4 family board can't boot. Above patch calls clk_set_rate() for all nodes with assigned-clock-rates property. Clock driver for STM32F family doesn't implement .set_rate callback which make clk_set_defaults() exit on error and prevent board to boot. Fixes: f4fcba5c5baa ("clk: implement clk_set_defaults()") Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-28Merge git://git.denx.de/u-boot-rockchipTom Rini
2018-01-28rockchip: clk: guard set_parent implementations against OF_PLATDATAPhilipp Tomsich
The set_parent implementations do not make sense when OF_PLATDATA is enabled. We guard these against OF_PLATDATA and don't populate the set_parent-op when this is the case. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28clk: rockchip: clk_rk3368: Implement "assign-clock-parent"David Wu
Implement the setting parent for gmac clock, and add internal pll div set for mac clk. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28clk: rockchip: clk_rk3288: Implement "assign-clock-parent" and ↵David Wu
"assign-clock-rate" The RK3288 CRU-node assigns rates to a number of clocks that are not implemented in the RK3288 clock-driver (but which have been sufficiently initialised from rkclk_init()): for these clocks, we implement the gmac clock set parent, but simply ignore the others' set_rate() operation and return 0 to signal success. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28clk: rockchip: Add rk322x gamc clock supportDavid Wu
Assuming mac_clk is fed by an external clock, set clk_rmii_src clock select control register from IO for rgmii interface. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28clk: rockchip: Add rk3328 gamc clock supportDavid Wu
The rk3328 soc has two gmac controllers, one is gmac2io, the other is gmac2phy. We use the gmac2io rgmii interface for 1000M phy here. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28rockchip: clk: rk3399: accept all assigned-clocks from the 'cru'-nodePhilipp Tomsich
The RK3399 CRU-node assigns rates to a number of clocks that are not implemented in the RK3399 clock-driver (but which have been sufficiently initialised from rkclk_init()): for these clocks, we simply ignore the set_rate() operation and return 0 to signal success. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address.
2018-01-28clk: implement clk_set_defaults()Philipp Tomsich
Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-28rockchip: clk: rk3399: implement set_parent() operationPhilipp Tomsich
This implements the (newly added) set_parent() operation for the RK3399 with a focus on allowing the RGMII clock parent to be configured via the assigned-clock-parents property of the GMAC node. This implementation supports only the GMAC (in fact only the RGMII clock parent) and allows to set this clock's parent either to the internal SCLK_GMAC or to an external clock input (identifiable by it providing a 'clock-output-name' of "gmac_clkin"). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address.
2018-01-28clk: refactor clk_get_by_index() into clk_get_by_indexed_prop()Philipp Tomsich
The logic in clk_get_by_index() may be useful for other properties than 'clocks': e.g. 'assigned-clocks' and 'assigned-clock-parents' follows the same model. This commit refactors clk_get_by_index() by introducing an internal function clk_get_by_indexed_prop() that allows to specify the name of the property to process. The original clk_get_by_index() call is simply directed through this helper function with the property name fixed to "clocks". Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address.
2018-01-28clk: add clk_set_parent()Philipp Tomsich
Clocks may support multiple parents: this change introduces an optional operation on the clk-uclass to set a clock's parent. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address.
2018-01-28clk: clk_stm32f: Fix PLLSAICFGR_PLLSAIP_4 divider valuePatrice Chotard
PLLSAIP divider uses 2 bits (bits 16 and 17) into RCC_PLLSAICFGR register, available combination are : 00: PLLSAIP = 2 01: PLLSAIP = 4 10: PLLSAIP = 6 11: PLLSAIP = 8 Previously, the divider value was incorrectly set to 6. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-28clk: clk_stm32f: Move SYSCFG clock setup into configure_clocks()Patrice Chotard
Move SYSCFG clock setup into configure_clocks() instead of calling clock_setup() from board file. As this clock is only needed in case of ethernet enabled and as both stm32f4 and stm32f7 are using the Designware ethernet IP, we use CONFIG_ETH_DESIGNWARE to only enable this clock if needed. Move the RMII setup from board_early_init_f() to board_init() to insure that RMII bit is set only when clock driver is initialized. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-28clk: clk_stm32f: Remove STMMAC clock setupPatrice Chotard
Thanks to 'commit ba1f96672522 ("net: designware: add clock support")' we don't need anymore to setup the STMMAC clock in board. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2018-01-28clk: stm32: retrieve external oscillator frequency from DTPatrice Chotard
All current STM32F4 supported boards uses a 8MHz external oscillator. All current STM32F7 supported boards uses a 25MHz external oscillator. In order to introduce the new stm32f429-evaluation board which uses a 25MHz external oscillator without creating a dedicated struct stm32_clk_info for this board, retrieve the external oscillator frequency from DT and set pll_m accordingly to obtain 1MHz for the VCO. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-27Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-shTom Rini
2018-01-26Merge git://git.denx.de/u-boot-spiTom Rini
2018-01-24clk: renesas: Import R8A7794 E2 clock tablesMarek Vasut
Import clock tables for R8A7794 E2 SoC from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Import R8A7792 V2H clock tablesMarek Vasut
Import clock tables for R8A7792 V2H SoC from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Import R8A7791/R8A7793 M2 clock tablesMarek Vasut
Import clock tables for R8A7791 M2W and R8A7793 M2N SoC from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Import R8A7790 H2 clock tablesMarek Vasut
Import clock tables for R8A7790 H2 SoC from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Add Gen2 clock coreMarek Vasut
Add common clock code for Renesas RCar Gen2 platforms. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Add DIV6P1 clock typeMarek Vasut
Add macros for the DIV6P1 clock type, which is used on Gen2 and optionally also on Gen3. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Split out code shared between Gen2 and Gen3Marek Vasut
Pull code which is common for RCar Gen2 and RCar Gen3 into separate source file. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Make clock tables Kconfig configurableMarek Vasut
Add Kconfig entries for each SoC clock table, so they can be compiled in or out at build time. This can reduce the size of the binary if desired. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Split SMSTPCR and RMSTPCR tablesMarek Vasut
The Gen2 requires setting RMSTPCR before booting, while on Gen3 this is thus far always zero. Split the tables so the RMSTPCR can be set too. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Pull Gen3 specific bits into separate headerMarek Vasut
Extract the macros specific to Gen3 clock into a separate header. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Make PLL configurations per-SoCMarek Vasut
Not all SoCs have the same PLL configuration options, so make those PLL configuraion tables per-SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Make clk_ids per-driverMarek Vasut
Not all drivers use the same IDs, so make those IDs per-driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Split RCar Gen3 driverMarek Vasut
Split the massive driver into smaller per-SoC drivers and pull the common code into a separate file. This would allow configuring out unnecessary clock drivers once the Kconfig changes are in and also allow adding more clock tables easily. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24wait_bit: use wait_for_bit_le32 and remove wait_for_bitÁlvaro Fernández Rojas
wait_for_bit callers use the 32 bit LE version Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-21clk: Makefile: Sort entries alphabeticallyMario Six
The Makefile entries in the clk driver directory were not alphabetically sorted. Correct this. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-21clk: Remove superfluous gd declarationsMario Six
The clk uclass was converted to support a live device tree recently, hence the global data pointer declarations are no longer needed. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-21clk: clk_fixed_rate: Fix style violationMario Six
Fix a mis-indented function call in clk_fixed_rate.c Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-21clk: clk-uclass: Fix style violationsMario Six
checkpatch.pl complains that the clk_ops structures used in clk-uclass.c ought to be const, so we mark them as const. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-19ARC: HSDK: CGU: Add 'Hz' when printing clock frequencyEugeniy Paltsev
Add 'Hz' when printing clock frequency in error messages. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-19ARC: HSDK: CGU: Use plat data instead of priv dataEugeniy Paltsev
Correctly allocate hsdk_cgu_clk private data structure using priv_auto_alloc_size instead of platdata_auto_alloc_size. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-19ARC: HSDK: CGU: Update AXI, TUN, ARC clock optionsEugeniy Paltsev
Update default AXI, TUN, ARC clock set options: instead of changing only IDIV divider settings adjust also domain PLL settings. Add support of TUN_ROM and TUN_PWM clocks (subclocks of TUNN_PLL) Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-10board: stm32f429-disco: switch to DM STM32 clock driverPatrice Chotard
Use available DM clk_stm32f.c driver instead of dedicated mach-stm32/stm32f4/clock.c. Migrate periph_clock defines from stm32_periph.h directly in CLK driver. These periph_clock defines will be removed when STMMAC, TIMER2 and SYSCFG drivers will support DM CLK. Enable also CLK flag. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-09rockchip: clk: bind reset driverElaine Zhang
Bind rockchip reset to clock-controller with rockchip_reset_bind(). Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-12-13Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-shTom Rini
2017-12-11ARC: clk: introduce HSDK CGU clock driverEugeniy Paltsev
Synopsys HSDK clock controller generates and supplies clocks to various controllers and peripherals within the SoC. Each clock has assigned identifier and client device tree nodes can use this identifier to specify the clock which they consume. All available clocks are defined as preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device tree sources. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-12-09clk: rmobile: Add R8A77995 D3 clock tablesMarek Vasut
Add clock tables for R8A77995 D3 SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-12-09clk: rmobile: Add R8A77970 V3M clock tablesMarek Vasut
Add clock tables for R8A77970 V3M SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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