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The phy used in the 8 bit instance has been changed to the phy used in 4
bit instance on AM62 SoC. This implies the phy configuration required for
both the instances of mmc are similar. Therefore, add a new compatible
for AM62 SoC using the driver data of am64 4 bit instance.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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Read the strobe select value from the device tree property ti,strobe-sel,
required for HS400 speed mode
Fixes: a20008eabd95 ("mmc: am654_sdhci: Add Support for configuring PHY in J721e")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Link: https://lore.kernel.org/r/20210525093826.10390-2-a-govindraju@ti.com
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Add support for the controller present on the AM642 SoC.
There are instances:
sdhci0: 8bit bus width, max 400 MBps
sdhci1: 4bit bus width, max 100 MBps
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
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Use the generic sdhci_set_control_reg() instead of duplicating
in platform driver.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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According to the AM654x Data Manual[1], the setup timing in lower speed
modes can only be met if the controller uses a falling edge data launch.
To ensure this, the HIGH_SPEED_ENA (HOST_CONTROL[2]) bit should be
cleared in default speed, SD high speed, MMC high speed, SDR12 and SDR25
speed modes.
Use the sdhci writeb callback to implement this condition.
[1] http://www.ti.com/lit/gpn/am6546 Section 5.10.5.16.1
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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With the new SW tuning App note[1], a custom tuning algorithm is
required for eMMC HS200, HS400 and SD card UHS modes. The algorithm
involves running through the 32 possible input tap delay values and
sending the appropriate tuning command (CMD19/21) for each of them
to get a fail or pass result for each of the values. Typically, the
range will have a small contiguous failing window. Considering the
tuning range as a circular buffer, the algorithm then sets a final
tuned value directly opposite to the failing window.
[1] https://www.ti.com/lit/pdf/spract9
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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Add support for writing new clock buffer select property for both
the am654x and j721e 4 bit IPs
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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DLL need only be enabled for speed modes and clock frequencies at or
above 50 MHz. For speed modes that don't enable the DLL, we need to
configure a static input delay value. This involves reading an optional
itap-del-sel-* value from the device tree and configuring it for the
appropriate speed mode.
Therefore, move all dll configurations to their own functions and gate it
with 50 MHz speed and a minimum mode. If both these conditions are not
satisfied then configure delay chain modes.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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Add Support for AM65x PG2.0. Use the SoC bus framework to fixup
the platform data and do DLL calibration if the revision is 1.0
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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Not all controllers need calibration for the PHY DLL. Add a DLL_CALIB
flag to indicate the same.
Also move the write of trm_icp and driver strength to the set_clock()
function to match the kernel configuration flow.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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Convert the flags field defines to use the BIT() macro.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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There are some speed modes that work without switching the dll on.
Unconditionally switch off the DLL before setting clock frequency to
support this case. The software will automatically enable DLL for speed
modes that require it. This also means the dll_on priv data member is no
longer required.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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This name is far too long. Rename it to remove the 'data' bits. This makes
it consistent with the platdata->plat rename.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Rename this to be consistent with the change from 'platdata'.
Signed-off-by: Simon Glass <sjg@chromium.org>
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We use 'priv' for private data but often use 'platdata' for platform data.
We can't really use 'pdata' since that is ambiguous (it could mean private
or platform data).
Rename some of the latter variables to end with 'plat' for consistency.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.
Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
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The hardcoded array size leads to array overflows with changes in
speed modes enum in mmc core. Use MMC_MODES_END for otap_del_sel
array declaration to fix this.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Move this uncommon header out of the common header.
Signed-off-by: Simon Glass <sjg@chromium.org>
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The 4 bit MMC controllers have an internal debounce for the SDCD line
with a debounce delay of 1 second. Therefore, after clocks to the IP are
enabled, software has to wait for this time before it can power on the
controller.
Add a deferred_probe() callback which polls on sdcd for a maximum of 2 seconds
before switching on power to the controller or (in the case of no card)
returning a ENOMEDIUM. This pushes the 1 second wait time to when the
card is actually needed rather than at every probe() making sure that
users who don't insert an SD card in the slot don't have to wait such a
long time.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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With the latest RIOT, there is a different otap delay value for each
speed mode. Add a new binding with every supported speed mode. Also
disable a given speed mode in the host caps if its corresponding
otap-del-sel is not present.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.
Move the compatibility features into a separate header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
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At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
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Add Support for writing to PHY registers for J721e. There are number of
differences between the J721e 8 bit PHY, J721e 4 bit PHY and AM654 PHY.
Create a driver_data structure with an ops and flags field and use the
flags field to indicate these differences. The differences are as
follows:
1. The J721e 4 bit instance PHY does not have a DLL. Introduce a
DLL_PRESENT flag to make sure that DLL related registers are accessed
only where they are present. Also add a separate set_ios_post()
callback.
2. The J721e 8 bit instance is not muxed with anything else inside the
SoC and hence the IOMUX_ENABLE filed does not exist. Add a flag which is
used to indicate the presence of this field.
3. The register field used to select DLL frequency is 3 bit wide in
J721e as compared to 2 bits in AM65x. Add another flag that
distinguishes these fields.
4. The strobe select field is 8 bit wide as compared to 4 bit wide for
AM65x. Add yet another flag to indicate this difference. Strobe select
is used only for HS400 speed mode, support for which has not been added
in AM65x.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Get clk_xin by name instead of by index to avoid having to put clocks in
the same order in all devices.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Power-domain is enabled by default in device_probe. am654 mmc driver
is enabling power-domain again in probe. As the second call is
redundant, drop power_domain_on from probe.
Tested-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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The j721e 4 bit instances don't have a hard DLL and therefore don't need
any DLL related configurations. Split the compatibles into an 8 bit and a
4 bit one. Add a private flags field which can be used to check if the
DLL is present and don't register the set_ios_post callback for the 4 bit
compatible instances.
Also update the compatibles in k3-j721e-main.dtsi to avoid breaking boot
with the new compatibles.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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We would like to use the driver even without power domains being
specified for cases such as during early boot when the required power
domains have already gotten enabled by the SoC's boot ROM and such
explicit initialization is not needed and possible.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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Add a platform specific set_control_reg() callback to help switch to
UHS speed modes.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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Add support in the driver for handling phy specific registers.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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The host controller works perfectly well without having to add any
quirks. Remove them.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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Sync the sdhci0 node from kernel. This changes the compatible that is
required to be there in the driver. Change the same for the SD card node
which is not yet supported in kernel. This also syncs the main_pmx0 node
as a side effect.
Also change the name of the driver to match the compatible in kernel.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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