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2022-10-23mtd: spi-nor-core: Fix index value for SCCR dwordsTakahiro Kuwano
Array index for SCCR 22th DWORD should be 21. Fixes: bebdc237507c ("mtd: spi-nor: Parse SFDP SCCR Map") Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23mtd: spi-nor-core: Rework s25hx_t_post_bfpt_fixup() for flash's internal ↵Takahiro Kuwano
address mode The flash's internal address mode is tracked by nor->add_mode_nbytes and it is set to 3 in BFPT parse. SEMPER multi-die package parts (>1Gb) are 3- or 4-byte address mode by default, depending on model number. We need to make sure that 4-byte address mode is used for multi-die package parts. For single-die package parts (<=1Gb), registers can be accessed by 3-byte address. Read, program, and erase use the 4B opcodes that always take 4-byte address regardless of flash's internal address mode. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23mtd: spi-nor-core: Rework spansion_read/write_any_reg() to use addr_mode_nbytesTakahiro Kuwano
Read/Write Any Register commands take 3- or 4- byte address depending on flash's internal address mode. The nor->addr_width tracks number of address bytes used in read/program/erase ops that can be 4 (with 4B opcodes) regardless of flash's internal address mode. The nor->addr_mode_nbytes tracks flash's internal address mode so replace nor->addr_width by that. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23mtd: spi-nor-core: Track flash's internal address modeTakahiro Kuwano
The nor->addr_width tracks number of address bytes used in read/program/erase ops and eventually set to 4 for >16MB chips, regardless of flash's internal address mode. For Infineon SEMPER flash's, we use Read/Write Any Register commands for configuration and status check. These commands take 3- or 4-byte address depending on flash's internal address mode. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23mtd: spi-nor-core: Default to addr_width of 3 for configurable widthsTakahiro Kuwano
JESD216D-01 mentions that "defaults to 3-Byte mode; enters 4-Byte mode on command." Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23mtd: spi-nor-ids: Add s28hl512t, s28hl01gt, and s28hs01gt IDsTakahiro Kuwano
Add flash info table entries for s28hl512gt, s28hl01gt, and s28hs01gt. These devices have the same functionality as s28hs512t. In spi-nor-core, use device ID byte to detect S28 family instead of device name. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23mtd: spi-nor-core: Rename configuration macro for S28 supportTakahiro Kuwano
Change configuration macro name to support all other devices in SEMPER S28 family. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23mtd: spi-nor-core: Rename s28hs512t prefixTakahiro Kuwano
Change prefix to support all other devices in SEMPER S28 family. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-09mtd: mxs_nand: Support EDO mode for imx8mn architectureMichael Trimarchi
Add support for imx8mn architecture in order to run the NAND in fast edo mode. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-10-09mtd: mxs_nand: get the clock with the right nameDario Binacchi
Rename the gpmi_apb_bch clock name to gpmi_bch_apb, as you can find in the device tree. Fixes: commit a59691280daca ("MXS_NAND: Add clock support for iMX8") Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2022-10-09mtd: mxs_nand: don't get the gpmi_apbh_dma clockDario Binacchi
This clock name is not present in any U-boot and Linux kernel device tree. Fixes: commit a59691280daca ("MXS_NAND: Add clock support for iMX8") Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2022-10-08mtd: nand: Fix SPL build after migration of CONFIG_SYS_NAND_SELF_INIT to KconfigRoger Quadros
This fixes the below build error if nand.c is included in an SPL build. /work/u-boot/drivers/mtd/nand/raw/nand.c: In function ‘nand_init_chip’: /work/u-boot/drivers/mtd/nand/raw/nand.c:82:28: error: ‘nand_chip’ undeclared (first use in this function) 82 | struct nand_chip *nand = &nand_chip[i]; | ^~~~~~~~~ /work/u-boot/drivers/mtd/nand/raw/nand.c:82:28: note: each undeclared identifier is reported only once for each function it appears in /work/u-boot/drivers/mtd/nand/raw/nand.c:84:20: error: ‘base_address’ undeclared (first use in this function); did you mean ‘base_addr’? 84 | ulong base_addr = base_address[i]; | ^~~~~~~~~~~~ | base_addr Fixes: 068c41f1cc77 ("Finish conversion CONFIG_SYS_NAND_SELF_INIT to Kconfig") Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-10-06mtd: nand: pxa3xx: simplify ECC hardware parametersChris Packham
Replace the if/else chain in pxa_ecc_init() with a lookup table. This makes the code more concise and hopefully easier to follow. Remove the unused ecc_layout tables and replace it with a single dummy one (the pxa3xx driver has never used this but the mtd subsystem expects it to be provided). Tested on an Allied Telesis x530 switch with Micron MT29F2G08ABAEAWP NAND Flash. Signed-off-by: Chris Packham <judge.packham@gmail.com>
2022-09-29dm: core: Drop ofnode_is_available()Simon Glass
This function is also available as ofnode_is_enabled(), so use that instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-19Merge branch 'master' into nextTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-09-18cyclic: Use schedule() instead of WATCHDOG_RESET()Stefan Roese
Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
2022-09-13mtd: spi-nor-ids: Add Winbond W25Q512JVQ IDChin-Ting Kuo
Add ID for Winbond W25Q512JVQ device which is supported on AST2600 EVB by default. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2022-09-13mtd: spi-nor: Use spi-mem dirmap APIChin-Ting Kuo
This adds support for the dirmap API to the spi-nor subsystem, as introduced in Linux commit df5c21002cf4 ("mtd: spi-nor: use spi-mem dirmap API"). This patch is synchronize from the following patch https://patchwork.ozlabs.org/project/uboot/patch/20210205043924.149504-4-seanga2@gmail.com/ The corresponding Linux kernel SHA1 is df5c21002cf4. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Signed-off-by: Sean Anderson <seanga2@gmail.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
2022-09-02renesas: Fix RPC-IF compatible valuesGeert Uytterhoeven
The compatible values used for device nodes representing Renesas Reduced Pin Count Interfaces were based on preliminary versions of the Device Tree Bindings. Correct them in both DTSi files and drivers, to match the final DT Bindings. Note that there are no DT bindings for RPC-IF on RZ/A1 yet, hence the most logical SoC-specific value is used, without specifying a family-specific value. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-08-22mtd: rawnand: fsl_elbc: Fix reading address pointer from DTPali Rohár
During compilation gcc throws warning: drivers/mtd/nand/raw/fsl_elbc_nand.c: In function ‘fsl_elbc_nand_probe’: drivers/mtd/nand/raw/fsl_elbc_nand.c:841:31: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] return fsl_elbc_chip_init(0, (void *)dev_read_addr(dev), dev); ^ Fix it by using dev_read_addr_ptr() function which returns pointer instead of dev_read_addr() which returns integer type. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-08-22mtd: rawnand: fsl_elbc: Remove NAND_NO_SUBPAGE_WRITE flagPali Rohár
Subpage write support for freescale eLBC NAND controller driver is implemented in U-Boot and was fixes in the commit d3963721d93f ("nand: Sync with Linux v4.1"). So remove NAND_NO_SUBPAGE_WRITE flag from the fsl_elbc_nand.c driver. This partially revert commit cb04c7723429 ("nand/fsl: add NAND_NO_SUBPAGE_WRITE to eLBC and IFC drivers"), only eLBC driver part. With this change U-Boot with default settings can read from NAND UBIFS image created on Linux with Linux default settings. Prior this change U-Boot was unable to read from NAND UBIFS images created with Linux default settings due to differnet UBI geometry. Linux kernel fsl_elbc_nand.c driver also does not set NAND_NO_SUBPAGE_WRITE flag and has implemented subpage write support. Fixes: cb04c7723429 ("nand/fsl: add NAND_NO_SUBPAGE_WRITE to eLBC and IFC drivers") Fixes: d3963721d93f ("nand: Sync with Linux v4.1") Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-By: Michael Trimarchi<michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-08-22mtd: nand: samsung: Retrieve ECC requirements from extendedMichael Trimarchi
Upstream linux commit 8fc82d456e40a0. On some nand controllers with hw-ecc the controller code wants to know the ecc strength and size and having these as 0, 0 is not accepted. Specifying these in devicetree is possible but undesirable as the nand may be different in different production runs of the same board, so it is better to get this info from the nand id where possible. This commit adds code to read the ecc strength and size from the nand for Samsung extended-id nands. This code is based on the info for the 5th id byte in the datasheets for the following Samsung nands: K9GAG08U0E, K9GAG08U0F, K9GAG08X0D, K9GBG08U0A, K9GBG08U0B. These all use these bits in the exact same way. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-08-22mtd: nand: Rename nand_get_flash_type() into nand_detect()Michael Trimarchi
Upstream linux commit 7bb427990ee364. Rename the function to match this new behavior. NOTE: fix nand_detect/nand_get_flash_type parameters in mxs_nand_spl. This code seems never executed by any board as alternative for nand detect Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-08-22mtd: nand: change return type of nand_get_flash_type() to intMichael Trimarchi
Upstream linux commit 4722c0e958e636. The returned "type" is never used in nand_scan_ident() and spl code Make nand_get_flash_type() simply return an integer value in order to avoid unnecessary ERR_PTR/PTR_ERR dance. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-08-22mtd: nand: Rename the nand_manufacturers structMichael Trimarchi
Upstream linux commit 8cfb9ab68f9070. Drop the 's' at the end of nand_manufacturers since the struct is actually describing a single manufacturer, not a manufacturer table. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-08-10common: Drop display_options.h from common headerSimon Glass
Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-08-04Convert CONFIG_SYS_FLASH_QUIET_TEST to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_FLASH_QUIET_TEST Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-04Convert CONFIG_SYS_MAX_FLASH_SECT to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_MAX_FLASH_SECT Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-04Audit <flash.h> inclusionTom Rini
A large number of files include <flash.h> as it used to be how various SPI flash related functions were found, or for other reasons entirely. In order to migrate some further CONFIG symbols to Kconfig we need to not include flash.h in cases where we don't have a NOR flash of some sort enabled. Furthermore, in cases where we are in common code and it doesn't make sense to try and further refactor the code itself in to new files we need to guard this inclusion. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-04flash: Remove pic32_flash.cTom Rini
As the only pic32 platform does not enable flash, this is dead code. Remove it. Cc: Purna Chandra Mandal <purna.mandal@microchip.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-04Convert CONFIG_SYS_FLASH_ERASE_TOUT et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_FLASH_ERASE_TOUT CONFIG_SYS_FLASH_LOCK_TOUT CONFIG_SYS_FLASH_UNLOCK_TOUT CONFIG_SYS_FLASH_WRITE_TOUT In practice, for two m68k platforms we move to hard-coding with a comment the timeout values, rather than try and make convoluted Kconfig logic. We add options for the write and erase options to the pic32 flash driver, as this driver does make use of them. Everywhere else these are unreferenced values. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-04Convert CONFIG_SYS_FLASH_CHECKSUM to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_FLASH_CHECKSUM Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-04Convert CONFIG_SYS_FLASH_EMPTY_INFO to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_FLASH_EMPTY_INFO Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-29arm: mvebu: Fix compatible string for nand controllerPali Rohár
Linux kernel uses compatible string "marvell,armada370-nand-controller" for nand controllers on Armada 370/XP/38x. U-Boot currently uses mix of "marvell,armada370-nand" and "marvell,mvebu-pxa3xx-nand". So unify it and use just Linux kernel compatible string. Signed-off-by: Pali Rohár <pali@kernel.org> Acked-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-22mtd: decommission the NAND museumMichael Trimarchi
Upstream linux commit f7025a43a9da26. The MTD subsystem has its own small museum of ancient NANDs in a form of the CONFIG_MTD_NAND_MUSEUM_IDS configuration option. The museum contains stone age NANDs with 256 bytes pages, as well as iron age NANDs with 512 bytes per page and up to 8MiB page size. It is with great sorrow that I inform you that the museum is being decommissioned. The MTD subsystem is out of budget for Kconfig options and already has too many of them, and there is a general kernel trend to simplify the configuration menu. We remove the stone age exhibits along with closing the museum REMARK Don't apply this part from upstream: Some of the iron age ones are transferred to the regular NAND depot. Namely, only those which have unique device IDs are transferred, and the ones which have conflicting device IDs are removed. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-07-22mtd: nand: toshiba: Retrieve ECC requirements from extended IDMichael Trimarchi
Upstream linux commit fb3bff5b407e58. This patch enables support to read the ECC strength and size from the NAND flash using Toshiba Memory SLC NAND extended-ID. This patch is based on the information of the 6th ID byte of the Toshiba Memory SLC NAND. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-07-22mtd: nand: Move Macronix specific initialization in nand_macronix.cMichael Trimarchi
Upstream linux commit 3b5206f4be9b65. Move Macronix specific initialization logic into nand_macronix.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-07-22mtd: nand: Move AMD/Spansion specific init/detection logic in nand_amd.cMichael Trimarchi
Upstream linux commit 229204da53b31d. Move AMD/Spansion specific initialization/detection logic into nand_amd.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-07-22mtd: nand: Move Micron specific init logic in nand_micron.cMichael Trimarchi
Upstream linux commit 10d4e75c36f6c1. Move Micron specific initialization logic into nand_micron.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-07-22mtd: nand: Move Toshiba specific init/detection logic in nand_toshiba.cMichael Trimarchi
Upstream linux commit 9b2d61f80b060c. Move Toshiba specific initialization and detection logic into nand_toshiba.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-07-22mtd: nand: Move Hynix specific init/detection logic in nand_hynix.cMichael Trimarchi
Upstream linux commit 01389b6bd2f4f7. Move Hynix specific initialization and detection logic into nand_hynix.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-07-22mtd: nand: Move Samsung specific init/detection logic in nand_samsung.cMichael Trimarchi
Upstream linux commit c51d0ac59f2420. Move Samsung specific initialization and detection logic into nand_samsung.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-07-22mtd: nand: Export symbol nand_decode_ext_idMichael Trimarchi
In preparation of moving specific nand support that are not jedec or onfi Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-07-22mtd: nand: Fix MediaTek MT7621 SoC buildMichael Trimarchi
nand_get_flash_type was reworked in commit 1ca6f9483e9ab5. This change break the Mediatek MT721. Fix it adjust the function call parameters +include/linux/mtd/rawnand.h:32:62: note: expected 'struct nand_chip *' but argument is of type 'struct mtd_info *' + 32 | struct nand_flash_dev *nand_get_flash_type(struct nand_chip *chip, + | ~~~~~~~~~~~~~~~~~~^~~~ +drivers/mtd/nand/raw/mt7621_nand.c:1189:48: error: passing argument 2 of 'nand_get_flash_type' from incompatible pointer type [-Werror=incompatible-pointer-types] + | ^~~~ + | | + | struct nand_chip * +include/linux/mtd/rawnand.h:33:49: note: expected 'int *' but argument is of type 'struct nand_chip *' + 33 | int *maf_id, int *dev_id, Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-07-22mtd: nand: Get rid of mtd variable in function callsMichael Trimarchi
chip points to mtd. Passing chip is enough to have a reference to mtd when is necessary Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-07-22mtd: nand: Add manufacturer specific initialization/detection stepsMichael Trimarchi
Upstream linux commit abbe26d144ec22. A lot of NANDs are implementing generic features in a non-generic way, or are providing advanced auto-detection logic where the NAND ID bytes meaning changes with the NAND generation. Providing this vendor specific initialization step will allow us to get rid of full-id entries in the nand_ids table or all the vendor specific cases added over the time in the generic NAND ID decoding logic. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-07-22mtd: nand: Store nand ID in struct nand_chipMichael Trimarchi
Upstream linux commit 7f501f0a72036d. Store the NAND ID in struct nand_chip to avoid passing id_data and id_len as function parameters. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-07-22mtd: nand: Get rid of busw parameterMichael Trimarchi
Upstream linux commit 29a198a1592d83. Auto-detection functions are passed a busw parameter to retrieve the actual NAND bus width and eventually set the correct value in chip->options. Rework the nand_get_flash_type() function to get rid of this extra parameter and let detection code directly set the NAND_BUSWIDTH_16 flag in chip->options if needed. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-07-20ubifs: Use U-Boot assert() from <log.h> in UBI/UBIFS codePali Rohár
U-Boot already provides assert function, so it use also in ubi and ubifs code. Signed-off-by: Pali Rohár <pali@kernel.org>
2022-07-19Merge https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
To quote Andre: One prominent feature is the restructering of the clock driver, which allows to end up with one actual driver for all variants, although we still only compile in support for one SoC. Also contained are some initial SPI fixes, which should fix some problems, and enable SPI flash support for the F1C100s SoC. Those patches revealed more problems, I will queue fixes later on, but for now it should at least still work. Apart from some smaller fixes (for instance for NAND operation), there is also preparation for the upcoming Allwinner D1 support, in form of the USB PHY driver. There are more driver support patches to come. The gitlab CI completed successfully, including the build test for all 160 sunxi boards. I also boot tested on a few boards, but didn't have time for more elaborate tests this time.
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