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2016-11-23powerpc: P1023: Remove macro CONFIG_P1023York Sun
Replace CONFIG_P1023 with ARCH_P1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-21driver: net: ldpaa_eth: Fix missing bracket issuePriyanka Jain
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-17Merge tag 'signed-efi-next' of git://github.com/agraf/u-bootTom Rini
Patch queue for efi - 2016-11-17 Highlights this time around: - x86 efi_loader support - hello world efi test case - network device name is now representative - terminal output reports modes correctly - fix psci reset for ls1043/ls1046 - fix efi_add_runtime_mmio definition for x86 - efi_loader support for ls2080
2016-11-17ls2080: Exit dpaa only right before exiting U-BootAlexander Graf
On ls2080 we have a separate network fabric component which we need to shut down before we enter Linux (or any other OS). Along with that also comes configuration of the fabric using a description file. Today we always stop and configure the fabric in the boot script and (again) exit it on device tree generation. This works ok for the normal booti case, but with bootefi the payload we're running may still want to access the network. So let's add a new fsl_mc command that defers configuration and stopping the hardware to when we actually exit U-Boot, so that we can still use the fabric from an EFI payload. For existing boot scripts, nothing should change with this patch. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> [agraf: Fix x86 build]
2016-11-15net: zynq_gem: Correct SGMII enable bit settingSiva Durga Prasad Paladugu
Correct the SGMII enable bit position to 27 instead of 31. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-11-15net: zynq_gem: Modify the nwcfg bit definitionsSiva Durga Prasad Paladugu
Modify the nwcfg bit definitions to have 32-bit by removing the extra nibble. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-11-07net: mvgbe: Fix build error with CONFIG_PHYLIBChris Packham
Commit 5a49f17481bb ("net: mii: Use spatch to update miiphy_register") updated the mvgbe implementation of smi_reg_read/smi_reg_write. Prior to that change mvgbe_phy_read and mvgbe_phy_write where used as wrappers to satisfy the phylib APIs. Because these functions weren't updated in that commit build errors where triggered when CONFIG_PHYLIB was enabled. Fix these build errors by removing mvgbe_phy_read and mvgbe_phy_write and using smi_reg_read/smi_reg_write directly. Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-11-07net: phy: micrel: center FLP burst timing at 16msAsh Charles
Like [1], reset the FLP burst timing for the KSZ9031 to the 16ms specified by the IEEE802.3 standard from the chip's default of 8ms. For more details, see the "Auto-Negotiation Timing" section of the KSZ9031RNX datasheet. [1] https://patchwork.kernel.org/patch/6558371/ Signed-off-by: Ash Charles <ash.charles@savoirfairelinux.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-11-07net: add driver for Synopsys Ethernet QoS deviceStephen Warren
This driver supports the Synopsys Designware Ethernet QoS (Quality of Service) a/k/a eqos IP block, which is a different design than the HW supported by the existing designware.c driver. The IP supports many options for bus type, clocking/reset structure, and feature list. This driver currently supports the specific configuration used in NVIDIA's Tegra186 chip, but should be extensible to other combinations quite easily, as explained in the source. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> # V1 Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-10-31Fix spelling of "resetting".Vagrant Cascadian
Cover-Letter: Fixes several spelling errors for the words "resetting", "extended", "occur", and "multiple". Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-28Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: common/Kconfig configs/dms-ba16_defconfig
2016-10-26net: Kconfig: Add FEC_MXC entryJagan Teki
Added kconfig for FEC_MXC driver. Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-24Fix codying style broken by recent libfdt syncMasahiro Yamada
Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-10-23Remove some merge markersSimon Glass
These two files have patch merge markers in them, within comments or strings. Remove then, so that a search for merge markers does not show up matches in these files. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-10-13Merge git://git.denx.de/u-boot-fdtTom Rini
2016-10-13libfdt: Sync fdt_for_each_subnode() with upstreamSimon Glass
The signature for this macro has changed. Bring in the upstream version and adjust U-Boot's usages to suit. Signed-off-by: Simon Glass <sjg@chromium.org> Update to drivers/power/pmic/palmas.c: Signed-off-by: Keerthy <j-keerthy@ti.com> Change-Id: I6cc9021339bfe686f9df21d61a1095ca2b3776e8
2016-10-13libfdt: Bring in upstream stringlist functionsSimon Glass
These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org>
2016-10-13rtl8169: fix cache misalignment message on transmit.Peter Chubb
The call to flush cache on the transmit buffer was misplaced (for very short packets) and asked to flush less than a cacheline. Move the flush cache call to after a short packet has been padded to minimum length (so the padding is flushed too), and round the size up to a cacheline. Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-10-13net: mvneta: fix typo in commentChris Packham
Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-10-13net: mv88e61xx: Add support for fixed linksChris Packham
On some boards these switches are wired directly into a SERDES interface on another Ethernet MAC. Add the ability to specify these kinds of boards using CONFIG_MV88E61XX_FIXED_PORTS which defines a bit mask of these fixed ports. Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-10-13net: Add support for mv88e609x switchesChris Packham
The Marvell Link Street mv88e60xx is a series of FastEthernet switch chips, some of which also support Gigabit ports. It is similar to the mv88e61xx series which support Gigabit on all ports. The main difference is the number of ports. Which affects the PORT_COUNT define and the size of the mask passed to mv88e61xx_port_set_vlan(). Other than that it's just a matter of adding the appropriate chip IDs. Signed-off-by: Chris Packham <judge.packham@gmail.com> Cc: Joshua Scott <joshua.scott@alliedtelesis.co.nz> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-10-13driver: net: cpsw: add support for RGMII id mode support and RMII clock ↵Mugunthan V N
source selection cpsw driver supports only selection of phy mode in control module but control module has more setting like RGMII ID mode selection, RMII clock source selection. So ported to cpsw-phy-sel driver from kernel to u-boot. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-10-13drivers: net: phy: atheros: add separate config for AR8031Mugunthan V N
In the current driver implementation, config() callback is common for AR8035 and AR8031 phy. In config() callback, driver tries to configure MMD Access Control Register and MMD Access Address Data Register unconditionally for both phy versions which leads to auto negotiation failure in AM335x EVMsk second port which uses AR8031 Giga bit RGMII phy. Fixing this by adding separate config for AR8031 phy. Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-10-13phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXIDAndrea Merello
This adds support for internal delay on RX and TX on RGMII interface for the AR8035 phy. This is basically the same Linux driver do. Tested on a Zynq Zturn board (for which u-boot support in is my tree; first patch waiting ML approval) Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-10-06Various, accumulated typos collected from around the tree.Robert P. J. Day
Fix various misspellings of: * deprecated * partition * preceding,preceded * preparation * its versus it's * export * existing * scenario * redundant * remaining * value * architecture Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Stefan Roese <sr@denx.de>
2016-10-01net, macb: fix misaligned cache operation warningHeiko Schocher
when using tftp on the smartweb board, it prints a lot of CACHE: Misaligned operation at range [23b2e000, 23b2e100] warnings ... fixed them. Signed-off-by: Heiko Schocher <hs@denx.de>
2016-09-27net: mvneta: Add support for Armada 3700 SoCStefan Roese
This patch adds support for the Armada 3700 SoC to the Marvell mvneta network driver. Not like A380, in Armada3700, there are two layers of decode windows for GBE: First layer is: GbE Address window that resides inside the GBE unit, Second layer is: Fabric address window which is located in the NIC400 (South Fabric). To simplify the address decode configuration for Armada3700, we bypass the first layer of GBE decode window by setting the first window to 4GB. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-09-27net: mvneta: Make driver 64bit safeStefan Roese
The mvneta driver is also used on the ARMv8 64bit Armada 3700 SoC. This patch fixes the compilation warnings seen on this 64bit platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-09-27net: mvneta: Round up top tx buffer boundaries for dcache opsStefan Roese
check_cache_range() warns that the top boundaries are not properly aligned when flushing or invalidating the buffers and make these operations fail. This gets rid of the warnings: CACHE: Misaligned operation at range ... Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-09-26Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-26armv8: ls1046a: Convert CONFIG_LS1046A to Kconfig option ARCH_LS1046AYork Sun
Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Mingkai Hu <mingkai.hu@nxp.com> CC: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-09-23treewide: replace #include <asm-generic/errno.h> with <linux/errno.h>Masahiro Yamada
Now, include/linux/errno.h is a wrapper of <asm-generic/errno.h>. Replace all include directives for <asm-generic/errno.h> with <linux/errno.h>. <asm-generic/...> is supposed to be included from <asm/...> when arch-headers fall back into generic implementation. Generally, they should not be directly included from .c files. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Add drivers/usb/host/xhci-rockchip.c] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-23treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-21net: pch_gbe: Make 64 bit safePaul Burton
The pch_gbe driver previously casted pointers to & from unsigned 32 bit integers in many locations. This breaks the driver on 64 bit systems, producing streams of compiler warnings about mismatched pointer & integer sizes and then failing to keep track of addresses correctly at runtime. Fix the driver for 64 bit systems by using unsigned longs in place of the previously used 32 bit integers. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-09-21net: pch_gbe: Use dm_pci_map_bar to discover MMIO basePaul Burton
Reading the PCI BAR & converting the result to a physical address is not safe across all architectures. For example on MIPS the virtual:physical mapping is not 1:1, so we cannot directly make use of the physical address. Use the more generic BAR-mapping function dm_pci_map_bar to discover the MMIO base address, which should work across architectures. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-09-21net: emaclite: Enable driver for MIPSZubair Lutfullah Kakakhel
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-09-21net: emaclite: use __raw_readl/writel instead of weird defineZubair Lutfullah Kakakhel
out_be32 and in_be32 are actually #defined to little endian writel/readl in arch/microblaze. Just use __raw_writel/readl instead. That is also what is used in the Linux kernel driver for this IP block Tested on MIPSfpga. Can tftp a kernel. Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-09-21net: emaclite: Use ioremap_nocacheZubair Lutfullah Kakakhel
Virtual to physical mapping isn't necessarily 1:1 for all architectures Using ioremap_nocache allows for the arch code to translate the physical address to a virtual address. Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-09-14net: fm: fix spi flash probe for using driver modelQianyu Gong
The current code would always use the speed and mode set by CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE. But if using SPI driver model it should get the values from DT. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-06meson: odroid-c2: enable Ethernet support through the device treeBeniamino Galvani
Remove the device definition from board file, update the driver with the new compatible property and update config with necessary options. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-22net: davinci_emac: Restore the internal MDIO accessors return valueskarl beldan
The spatch series converting legacy drivers from miiphy_register to mdio_register changed the return convention of the davinci_emac internal MDIO accessors, making the internal code relying on it misbehaving: no mdiodev get registered and U-Boot crashes when using net cmds in the context of the old legacy net API. ATM davinci_emac_initialize and cpu_eth_init don't return a proper value in that case but fixing them would not avoid the crash. This change is just a follow-up to the spatch pass, the MDIO accessors of the mdiodev introduced by the spatch pass retain their proper values. Signed-off-by: Karl Beldan <karl.beldan+oss@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-08-22net/fm: Remove unused code of FMan QMIHou Zhiqiang
The QMan is not used in FMan IM mode, so no QMI enqueue or QMI dequeue are performed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-08-22net: davinci_emac: Invalidate only the received portion of a bufferkarl beldan
ATM when receiving a packet the whole buffer is invalidated, this change optimizes this behaviour. Signed-off-by: Karl Beldan <karl.beldan+oss@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
2016-08-22net: davinci_emac: Round up top tx buffer boundaries for dcache opskarl beldan
check_cache_range() warns that the top boundaries are not properly aligned when flushing or invalidating the buffers and make these operations fail. This gets rid of the remaining warnings: CACHE: Misaligned operation at range Signed-off-by: Karl Beldan <karl.beldan+oss@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
2016-08-22net: davinci_emac: Remove useless dcache ops on descriptorskarl beldan
ATM the rx and tx descriptors are handled as cached memory while they lie in a dedicated RAM of the SoCs, which is an uncached area. Removing the said dcache ops, while optimizing the logic and clarifying the code, also gets rid of most of the check_cache_range() incurred warnings: CACHE: Misaligned operation at range Signed-off-by: Karl Beldan <karl.beldan+oss@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-08-15net: mii: Changes not made by spatchJoe Hershberger
If the functions passed to the registration function are not in the same C file (extern) then spatch will not handle the dependent changes. Make those changes manually. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> For the 4xx related files: Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-08-15net: mii: Fix changes made by spatchJoe Hershberger
Some of the changes were a bit too complex. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-08-15net: mii: Use spatch to update miiphy_registerJoe Hershberger
Run scripts/coccinelle/net/mdio_register.cocci on the U-Boot code base. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-08-15net/ethoc: implement MDIO bus and support phylibMax Filippov
Implement MDIO bus read/write functions, initialize the bus and scan for the PHY when phylib is enabled. Limit PHY speeds to 10/100 Mbps. Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-08-15net/ethoc: support private memory configurationsMax Filippov
The ethoc device can be configured to have a private memory region instead of having access to the main memory. In that case egress packets must be copied into that memory for transmission and pointers to that memory need to be passed to net_process_received_packet or returned from the recv callback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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