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path: root/drivers/spi
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2023-09-24common: Drop linux/printk.h from common headerSimon Glass
This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-09-21spi: zynqmp_qspi: Workaround for small data cache issueVenkatesh Yadav Abbarapu
Cache related issues are seen with small sized data reads. Due to this, proper data is not read. Also some times sf probe fails randomly. To workaround this issue, invalidate dcache after read DMA is triggered. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20230915031759.28889-3-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-09-21spi: zynqmp_qspi: Change flush cache to invalidate cacheAshok Reddy Soma
Before DMA read, ideally cache should be invalidated, so that data from memory will be updated to cache after DMA is completed. But flush_dcache_range is being used which is incorrect. Change flush_dcache_range to invalidate_dcache_range. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20230915031759.28889-2-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-09-14spi: Remove unused NEEDS_MANUAL_RELOC code bitsMarek Vasut
The last user of the NEEDS_MANUAL_RELOC has been removed in commit 26af162ac8f8 ("arch: m68k: Implement relocation") Remove now unused NEEDS_MANUAL_RELOC code. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-08-03spi: mtk_spim: clear IRQ enable bitsWeijie Gao
In u-boot we don't use IRQ. Instead, we poll busy bit in SPI_STATUS. However these IRQ enable bits may be set in previous boot stage (BootROM). If we leave these bits not cleared, although u-boot has disabled IRQ and nothing will happen, the linux kernel may encounter panic during initializing the spim driver due to IRQ event happens before IRQ handler is properly setup. This patch clear IRQ bits to prevent this from happening. Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-08-03spi: mtk_spim: get spi clk rate only onceWeijie Gao
We don't really need to switch clk rate during operating SPIM controller. Get clk rate only once at driver probing. Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-21cadence_qspi: Enable flash reset for Versal NET platformAshok Reddy Soma
Enable flash reset functionality for Versal NET platform. In cadence_qspi.c there is weak function defined for reset, hence remove the check for config, so that it will work for Versal and Versal NET platforms. Add register defines in Versal NET hardware.h for mini U-Boot flash reset. Add read_delay initialization for Versal NET also. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230614120452.21019-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21spi: zynq_qspi: Add missing prototype for zynq_qspi_mem_exec_opAlgapally Santosh Sagar
Add missing prototype to fix the sparse warning, warning: no previous prototype for 'zynq_qspi_mem_exec_op' [-Wmissing-prototypes]. Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230614090359.10809-4-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21spi: xilinx_spi: Add missing prototype for xilinx_qspi_mem_exec_opAlgapally Santosh Sagar
Add missing prototype to fix the below sparse warning warning: no previous prototype for 'xilinx_qspi_mem_exec_op' [-Wmissing-prototypes] Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230614090359.10809-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-13spi: npcm_pspi: use ACTIVE_LOW flag for cs gpio and set default max_hzJim Liu
If cs gpio is requested with ACTIVE_HIGH flag, it will be pulled low(i.e. active). This is not what we expected. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: soft_spi: Support the recommended soft spi propertiesFabio Estevam
According to Documentation/devicetree/bindings/spi/spi-gpio.yaml from Linux, the recommended spio-gpio properties are: sck-gpios, miso-gpios and mosi-gpios. gpio-sck, gpio-mosi and gpio-miso are considered deprecated. Currently, U-Boot only supports the deprecated properties. Allow the soft_spi driver to support both the new and old properties. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: synquacer: remove SPI_TX_BYTE handlingMasahisa Kojima
Current code expects that SPI_TX_BYTE is single bit mode but it is wrong. It indicates byte program mode, not single bit mode. If SPI_TX_DUAL, SPI_TX_QUAD and SPI_TX_OCTAL bits are not set, the default transfer bus width is single bit. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: bcmbca-hsspi: Add driver for newer HSSPI controllerWilliam Zhang
The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI controller that add the capability to allow the driver to control chip select explicitly. Driver can control and keep cs low between the transfers natively. Hence the dummy cs workaround or prepend mode found in the bcm63xx-hsspi driver are no longer needed and this new driver is much cleaner. Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zhang@broadcom.com Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: bcm63xx-hsspi: Add prepend mode supportWilliam Zhang
Due to the controller limitation to keep the chip select low during the bus idle time between the transfer, a dummy cs workaround was used when this driver was first upstreamed to the u-boot based on linux kernel driver. It basically picks the dummy cs as !actual_cs so typically dummy cs is 1 when most of the case only cs 0 is used in the board design. Then invert the polarity of both cs and tell the controller to start the transfers using dummy cs. Assuming both cs are active low before the inversion, effectively this keeps dummy cs high and actual cs low during the transfer and workaround the issue. This workaround requires that dummy cs 1 pin to is set to SPI chip selection function in the pinmux when the transfer clock is above 25MHz. The old chips likely have default pinmux set to chip select on the dummy cs pin so it works but this is not case for the new Broadband BCA chips and this workaround stop working. This is specifically an issue to support SPI NAND and SPI NOR flash because these flash devices can typically run at or above 100MHz. This patch utilizes the prepend feature of the controller to combine the multiple transfers in the same message to a single transfer when possible. This way there is no need to keep clock low between transfers and solve the issue without any pinmux requirement. Multiple transfers within a SPI message may be combined into one transfer if the following are all true: * One or more half duplex write transfer in single bit mode * Optional full duplex read/write at the end * No delay and cs_change between transfers Most of the SPI device meets this requirements such as SPI NOR, SPI NAND flash, Broadcom SPI voice card and etc. So this change switches to the prepend mode as the default mode. For any SPI message that does not meet the above requirement, we switch to original dummy cs mode but limit the clock rate to the safe 25MHz. Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-12-william.zhang@broadcom.com Signed-off-by: William Zhang <william.zhang@broadcom.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: bcm63xx-hsspi: Add new compatible string supportWilliam Zhang
New compatible string brcm,bcmbca-hsspi-v1.0 is introduced based on dts document brcm,bcm63xx-hsspi.yaml. Add it to the driver to support this new binding. Port from linux patch: Link: https://lore.kernel.org/r/20230207065826.285013-6-william.zhang@broadcom.com Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: bcm63xx-hsspi: Fix multi-bit mode settingWilliam Zhang
Currently the driver always sets the controller to dual data bit mode for both tx and rx data in the profile mode control register even for single data bit transfer. Luckily the opcode is set correctly according to SPI transfer data bit width so it does not actually cause issues. This change fixes the problem by setting tx and rx data bit mode field correctly according to the actual SPI transfer tx and rx data bit width. Fixes: 29cc4368ad4b ("dm: spi: add BCM63xx HSSPI driver") Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-11-william.zhang@broadcom.com Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: bcm63xx-hsspi: Make driver depend on BCMBCA archWilliam Zhang
ARCH_BCMBCA was introduced to cover individual Broadcom broadband SoC for common features and IP blocks. Use this config instead of each chip config as the Kconfig dependency for Broadcom HSSPI driver. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: pl022: Add chip-select gpio supportLukas Funke
Add support for an optional external chip-select gpio. Signed-off-by: Lukas Funke <lukas.funke@weidmueller.com> Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: pl022: Remove platform data headerStefan Herbrechtsmeier
Remove the platform data header because its content is only used by the driver. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: pl022: Rename flush into pl022_spi_flushStefan Herbrechtsmeier
Rename the flush function into pl022_spi_flush to avoid conflicting types with previous declaration of the function in stdio.h header. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: pl022: Align compatible property with device tree bindingLukas Funke
Align the compatible property with the kernel device tree binding [1] by removing the '-spi' suffix. [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/spi/spi-pl022.yaml Signed-off-by: Lukas Funke <lukas.funke@weidmueller.com> Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-06-20drivers: spi: omap3_spi: Initialize mode for all channelsJulien Panis
At first SPI transfers, multiple chip selects can be enabled simultaneously. This is due to chip select polarity, which is not properly initialized for all channels. This patch fixes the issue. Signed-off-by: Julien Panis <jpanis@baylibre.com>
2023-06-12Merge tag 'xilinx-for-v2023.10-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2023.10-rc1 global: - Use proper U-Boot project name Fix sparse warnings in zynqmp-clk, zynqmp handoff, board cmd: - Cover incorrect 0 length entries Versal NET: - Add bootmode logic - Support SPP production version - Add loadpdi command ZynqMP: - Clear pmufw node command ID handling - Change power domain behavior around zynqmp_pmufw_node() - Fix zynqmp cmd return values and pmufw command - Fix R5 tcm init and modes mmc: - Sync Versal NET emmc DT binding pcie: - Add support for ZynqMP PCIe root port video: - Add support for ZynqMP DP tools: - Fix debug message in relocate-rela
2023-06-12Merge tag v2023.07-rc4 into nextTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-06-12global: Use proper project name U-BootMichal Simek
Use proper project name in comments, Kconfig, readmes. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Qu Wenruo <wqu@suse.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/0dbdf0432405c1c38ffca55703b6737a48219e79.1684307818.git.michal.simek@amd.com
2023-06-10mtd: spi: renesas: Add 4 bytes address mode supportCong Dang
This patch adds 4-byte address mode support. Because traditional access based on FIFO/shift register, it's complex to specify information like opcode, address length, dummy bytes etc to flash. Replace the traditional access by spi-mem layer which is essential to make 4-byte address mode support possible. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-06-10mtd: spi: renesas: Add R-Car Gen4 supportHai Pham
Support RPC SPI on R-Car Gen4 R8A779F0 S4 and R8A779G0 V4H SoCs. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Squash S4 and V4H patches, fix brackets around STRTIM2]
2023-06-10mtd: spi: renesas: Enable SPI_FLASH_SFDP_SUPPORTHai Pham
Enable support for parsing and auto discovery of parameters for SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP) tables as per JESD216 standard. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Make SFDP the default unconditionally
2023-06-10mtd: spi: renesas: Extract strobe delay setting code into separate functionHai Pham
Move strobe delay setting code into extra function and reflect the latest setting in datasheet (R-Car Gen3 v2.20, R-Car V3U v0.50). i.e. STRTIM[2:0] should be set to 110 (RCar M3-W) or 111 (Other products) This is also a preparation for new R-Car Gen4 SoC which has 4-bits STRTIM Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Fix for RZ/A1
2023-05-18spi: rockchip_sfc: Use linux rockchip,sfc-no-dma propJonas Karlman
Use the same prop as linux to control the use of fifo or dma mode. Also add a u-boot,spl-sfc-no-dma prop to control the same in SPL. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-15Revert "spi: zynq_qspi: Use dummy buswidth in dummy byte calculation"Stefan Herbrechtsmeier
This reverts commit e09784728689de7949d4cdd559a9590e0bfcc702. The commit wrongly divides the dummy bytes by dummy bus width to calculate the dummy bytes. The framework already converts the dummy cycles to the number of bytes and the controller use the SPI flash command to determine the dummy cycles via the address width. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230427065355.7413-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-05-09Merge tag 'u-boot-rockchip-20230509' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-rockchip - Rockchip NFC driver update and dev addr pointer api update; - use standard dr_mode for usb driver; - rock pi boards dts update; - Add rk3566 Anbernic boards; - Misc fixes for drivers;
2023-05-07Merge branch 'for-2023.07-2' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-mpc8xx This pull request adds misc fixes for cssi boards and activates CPM relocation in order to enable the use of SCC4 in QMC (QUICC Multi-Channel) mode.
2023-05-06drivers: use devfdt_get_addr_ptr when cast to pointerJohan Jonker
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_ptr instead of the devfdt_get_addr function in the various files in the drivers directory that cast to a pointer. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06drivers: use devfdt_get_addr_index_ptr when cast to pointerJohan Jonker
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_index_ptr instead of the devfdt_get_addr_index function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06drivers: use devfdt_get_addr_size_index_ptr when cast to pointerJohan Jonker
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_size_index_ptr instead of the devfdt_get_addr_size_index function in the various files in the drivers directory that cast to a pointer. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06drivers: use dev_read_addr_ptr when cast to pointerJohan Jonker
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use dev_read_addr_ptr instead of the dev_read_addr function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06spi: spi-aspeed-smc: use devfdt_get_addr_index_ptrJohan Jonker
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_index_ptr and devfdt_get_addr_size_index_ptr function in the spi-aspeed-smc.c file. Also fix dev_dbg to be able to handle both sizes. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2023-05-06rockchip: spi: rk_spi: use base variable with uintptr_t sizeJohan Jonker
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use a base variable with uintptr_t size in the rk_spi.c file. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-05spi, mpc8xx: Take parameter RAM relocation into accountChristophe Leroy
Instead of inhibiting parameter RAM relocation, take it into account. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2023-05-04powerpc: mpc8xx: CPM parameter RAM can be anywhereChristophe Leroy
With relocation, CPM parameter RAM can be anywhere in the dual port RAM, so don't split dual port RAM. Remove dparam and dparam16 members of struct comm_proc PROFF_XXX become offsets from the start of dual port RAM, then they are now consistant with the offsets in RPBASE registers. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2023-05-01Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spiTom Rini
- cadence-quadspi fixes (Apurva Nandan, Dhruva Gole) - CHIP_ERASE optimization (Marek Vasut) - fixups for s25fs512s (Takahiro Kuwano)
2023-04-29Merge branch 'for-2023.07' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-mpc8xx This pull request adds support for the last CPU board from CS GROUP France (previously CSSI). That CPU board called CMPCPRO has a mpc8321E CPU (Family PQII PRO hence its name) and can be plugged in place of the CMPC885 board. In order to support that new board, the following changes are included in this series: - Make the mpc8xx watchdog driver more generic for reusing it with mpc83xx - Fix various small problems on mpc83xx platform - Add a GPIO Driver for QE GPIOs - Add support for mpc832x into mpc83xx SPI driver - Refactor existing board code that will be shared with new board - Add the new board
2023-04-26spi: cadence-quadspi: Reset CMD_CTRL Reg on cmd r/w completionDhruva Gole
If one leaves the CQSPI_REG_CMDCTRL in an unclean state this may cause issues in future command reads. This issue came to light when some flash reads in STIG mode were coming back dirty. Co-developed-by: Apurva Nandan <a-nandan@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Signed-off-by: Dhruva Gole <d-gole@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2023-04-26spi: cadence-quadspi: Use STIG mode for all ops with small payloadApurva Nandan
OSPI controller supports all types of op variants in STIG mode, only limitation being that the data payload should be less than 8 bytes when not using memory banks. STIG mode is more stable for operations that send small data payload and is more efficient than using DMA for few bytes of memory accesses. It overcomes the limitation of minimum 4 bytes read from flash into RAM seen in DAC mode. Use STIG mode for all read and write operations that require data input/output of less than 8 bytes from the flash, and thereby support all four phases, cmd/address/dummy/data, through OSPI STIG. Also, remove the reorder address chunk in apb_command_write since we now setup ADDR BIT field that does the same job in a cleaner way. Signed-off-by: Apurva Nandan <a-nandan@ti.com> Signed-off-by: Dhruva Gole <d-gole@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2023-04-26spi: cadence-quadspi: Fix check condition for DTR opsApurva Nandan
buswidth and dtr fields in spi_mem_op are only valid when the corresponding spi_mem_op phase has a non-zero length. For example, SPI NAND core doesn't set buswidth when using SPI_MEM_OP_NO_ADDR phase. Fix the dtr checks in set_protocol() to ignore empty spi_mem_op phases, as checking for dtr field in empty phase will result in false negatives. Signed-off-by: Apurva Nandan <a-nandan@ti.com> Signed-off-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-04-25spi: synquacer: Silence uninitialized variable warningsIlias Apalodimas
When building with clang, the compiler compains with drivers/spi/spi-synquacer.c:212:11: warning: variable 'bus_width' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized] else if (priv->mode & SPI_TX_OCTAL) ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/spi/spi-synquacer.c:276:11: note: uninitialized use occurs here val |= ((bus_width >> 1) << BUS_WIDTH); ^~~~~~~~~ drivers/spi/spi-synquacer.c:212:7: note: remove the 'if' if its condition is always true else if (priv->mode & SPI_TX_OCTAL) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/spi/spi-synquacer.c:189:25: note: initialize the variable 'bus_width' to silence this warning So initialize bus_width to 1 and add a warning if none of the configured modes matches Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-04-25spi: npcm-fiu: add regulator feature and remove set clockJim Liu
NPCM7xx/NPCM8xx default is boot from flash. removed set clock feature due to reliability and security. the clock will set by bootblock or tip. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-04-25spi: f-ospi: Add missing spi_mem_default_supports_op() helperKunihiko Hayashi
The .supports_op() callback function returns true by default after performing driver-specific checks. Therefore the driver cannot apply the buswidth in devicetree. Call spi_mem_default_supports_op() helper to handle the buswidth in devicetree. Fixes: 358f803ae21c ("spi: Add Socionext F_OSPI SPI flash controller driver") Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-04-25spi: spi-mem: perform odd len check only while writing dataDhruva Gole
in spi_mem_dtr_supports_op we have a check for allowing only even number of bytes to be r/w. Odd bytes writing can be a concern while writing data to a flash for example because 8 DTR mode doesn't support it. However, reading ODD Bytes even though may not be physically possible we can still allow for it because it will not have serious implications on any critical registers being overwritten since they are just reads. Cc: Vaishnav Achath <vaishnav.a@ti.com> Cc: Pratyush Yadav <pratyush@kernel.org> Cc: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Nikhil M Jain <n-jain1@ti.com> Signed-off-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
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