aboutsummaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)Author
2020-02-05sandbox: pmic: Correct i2c pmic emulator platdata methodSimon Glass
This currently reads the uclass's private data in the ofdata_to_platdata method which is not allowed, since the uclass has not read it from the device tree. This happens in the probe method. Fix it by adding a probe() method and moving the code there. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: core: Drop uclass_find_next_free_req_seq() conditionsSimon Glass
These conditions are not needed and just reduce build coverage. Drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: core: Add a way to iterate through children, probing eachSimon Glass
It is sometimes useful to process all children, making sure they are probed first. Add functions to help with this and a macro to make it more convenient. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: core: Add a way to read platdata for all child devicesSimon Glass
When generating ACPI tables we need to make sure that all devices have read their platform data, so that they can generate the tables correctly. Rather than adding this code in ACPI, create a core function to handle it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: core: Add ofnode_get_chosen_prop()Simon Glass
Add a function to read a property from the chosen node, providing access to its length. Update ofnode_get_chosen_string() to make use of it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: core: Reimplement ofnode_read_size()Simon Glass
Now that we have ofnode_read_prop() we can rewrite this function using that one, reducing the amount of duplicated code. Update ofnode_read_size() and move it up next to the other similar functions. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: core: Add ofnode_read_prop()Simon Glass
Add a new function to read a property that supports reading the length as well. Reimplement ofnode_read_string() using it and fix its comment. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: core: Rename ofnode_get_chosen_prop()Simon Glass
This function is actually intended to read a string rather than a property. All of its current callers use it that way. Also there is no way to return the length of the property from this function. Rename it to better indicate its purpose, using ofnode_read as the prefix since this matches most other functions. Also add some tests which are missing for these functions. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: core: Use const device for the dev_read_...() interfaceSimon Glass
These functions do not modify the device so should use a const pointer to it. Update the code accordingly. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: core: Use const device for the devfdt...() interfaceSimon Glass
These functions do not modify the device so should use a const pointer to it. Update the code accordingly. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: pci: Update a few more interfaces for const udevice *Simon Glass
Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: pci: Update the PCI read_config() method to const dev *Simon Glass
At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: core: Use const where possible in device.hSimon Glass
Update this header file to use const devices where possible, to permit callers to also use const. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
- Bug fixes on ls1012a, ls1021a, ls1028ardb platforms Integrate fspi for ls1028a, add DM-I2C support, update secure boot header offset
2020-02-05Merge tag 'rpi-next-2020.04' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi - DFU support file operations lager then the default max size - add dfu support to dwc2 for bcm2835 - enable DFU for RPi4 - Fix RPi4 memory map to include the genet device - add driver for the genet ethernet device - enable network support in RPi4 config
2020-02-04Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini
- Various minor fixes for x86 - Switch to ACPI mode on Intel edison - Support run-time configuration for NS16550 driver - Update coreboot and slimbootloader serial drivers to use NS16550 run-time configuration - ICH SPI driver fixes to hardware sequencing erase case - Move ITSS from Apollo Lake to a more generic location - Intel GPIO driver bug fixes - Move to vs2017-win2016 platform build host for Azure pipelines
2020-02-04i2c: mxc_i2c: add DM_FLAG_PRE_RELOC flagBiwen Li
This adds DM_FLAG_PRE_RELOC flag to probe i2c driver before relocation Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-02-04rtc: pcf8563: Add driver model supportBiwen Li
Add support of driver model of pcf8563 Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-02-04gpio: intel_gpio: Fix register/bit offsets intel_gpio_get_value()Wolfgang Wallner
Fix the following in intel_gpio_get_value(): * The value of the register is contained in the variable 'reg', not in 'mode'. The variable 'mode' contains only the configuration whether the gpio is currently an input or an output. * The correct bitmasks for the input and output value are PAD_CFG0_RX_STATE and PAD_CFG0_TX_STATE. Use them instead of the currently used PAD_CFG0_RX_STATE_BIT and PAD_CFG0_TX_STATE_BIT. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04gpio: intel_gpio: Clear tx state bit when setting outputWolfgang Wallner
Add missing 'PAD_CFG0_TX_STATE' to the clear mask for pcr_clrsetbits32(). Otherwise this bit cannot be cleared again after it has been set once. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04gpio: intel_gpio: Pass pinctrl device to pcr_clrsetbits32()Wolfgang Wallner
The function pcr_clrsetbits32() expects a device with a P2SB parent device. In intel_gpio_direction_output() and intel_gpio_set_value() the device 'dev' is passed to pcr_clrsetbits32(), which is a gpio-controller with a device 'pinctrl' as parent. This does not match the expectations of pcr_clrsetbits32(). But the 'pinctrl' device has a P2SB as parent. Pass the 'pinctrl' device instead of the 'dev' device to pcr_clrsetbits32(). Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04watchdog: omap_wdt: Fix WDT coding styleMarek Vasut
Fix obvious coding style problems, no functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Suniel Mahesh <sunil.m@techveda.org> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04watchdog: omap_wdt: Fix WDT reloadingMarek Vasut
The watchdog timer value was never updated in the hardware by this driver, so the watchdog triggered on some random stale value that was left in the hardware. The TI SPRUH37C says, quote: 20.4.3.9 Modifying Timer Count/Load Values and Prescaler Setting ... After a write access, the load register value and prescaler ratio registers are updated immediately, but new values are considered only after the next consecutive counter overflow or after a new trigger command (the WDT_WTGR register). This means at least one trigger must happen. The driver probably depended on someone calling it's .reset() callback, however that is not guaranteed e.g. if the WDT operates without servicing. Add this missing trigger. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Suniel Mahesh <sunil.m@techveda.org> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04watchdog: omap_wdt: Fix WDT timeout configurationMarek Vasut
The timeout parameter of omap3_wdt_start() is in miliseconds, while GET_WLDR_VAL() expects parameter in seconds. Fix this so the WDT driver is actually usable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Suniel Mahesh <sunil.m@techveda.org> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04gpio: da8xx_gpio: Add "ti,keystone-gpio" compatibleVignesh Raghavendra
Add "ti,keystone-gpio" compatible so as be able to use Linux DT files as is. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04gpio: da8xx_gpio: Fix compiler warningVignesh Raghavendra
Fix below compiler warning for 64bit builds drivers/gpio/da8xx_gpio.c: In function ‘davinci_get_gpio_bank’: drivers/gpio/da8xx_gpio.c:446:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] return (struct davinci_gpio *)addr; Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04gpio: pca953x_gpio: Add support for 24 bit IO expanderVignesh Raghavendra
J721e EVM has a TCA6424 IO expander that has 24 GPIOs. Add support for the same Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04x86: Move itss.h from Apollo Lake to the generic x86 include directoryWolfgang Wallner
The code in this file is not specific to Apollo Lake. According to coreboot sources (where this code comes from), it is common to at least: * Apollo Lake * Cannon Lake * Ice Lake * Skylake Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04spi: ich: Drop while loop in hardware sequencing erase caseWolfgang Wallner
When ich_spi_exec_op_hwseq() is called to erase a 4k block (opcode = SPINOR_OP_BE_4K), it expects to find a length value in op->data.nbytes, but that value is always 0. As a result, the while loop is never executed and no erase is carried out. Fix this by dropping the loop code entirely, only keeping the relevant parts of the loop body. See http://patchwork.ozlabs.org/patch/1222779/ for more detailed background information and discussion. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04x86: serial: Add a coreboot serial driverSimon Glass
Coreboot can provide information about the serial device in use on a platform. Add a driver that uses this information to produce a working UART. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04serial: ns16550: Support run-time configurationSimon Glass
At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-02Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
- DFU and Cadence USB 3 fixes
2020-02-02dfu: Add option to skip empty pages when flashing UBI images to NANDGuillermo Rodríguez
Add a new option to enable the DROP_FFS flag when flashing UBI images to NAND in order to drop trailing all-0xff pages. This is similar to the existing FASTBOOT_FLASH_NAND_TRIMFFS option. Signed-off-by: Guillermo Rodriguez <guille.rodriguez@gmail.com> Cc: Lukasz Majewski <lukma@denx.de>
2020-02-02usb: cdns3: ep0: Invalidate cache before reading Setup PacketVignesh Raghavendra
Invalidate dcache line before accessing Setup Packet contents. Otherwise driver will see stale content on non coherent architecture. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-02-01Merge tag 'u-boot-rockchip-20200130' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Support redundant boot for rk3399 - Support binman for rockchip platform - Update ram driver and add ddr4 support for rk3328
2020-01-31Merge tag 'uniphier-v2020.04-2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier UniPhier SoC updates for v2020.04 (2nd) Denali NAND driver changes: - Set up more registers in denali-spl for SOCFPGA - Make clocks optional - Do not assert reset signals in the remove hook - associate SPARE_AREA_SKIP_BYTES with DT compatible - switch to UCLASS_MTD UniPhier platform changes: - fix a bug in dram_init() - specify loadaddr for "source" command
2020-02-01mtd: rawnand: denali_dt: use UCLASS_MTD instead of UCLASS_MISCMasahiro Yamada
UCLASS_MTD is a better fit for NAND drivers. Make NAND_DENALI_DT depend on DM_MTD, which is needed to compile drivers/mtd/mtd-uclass.c Also, make ARCH_UNIPHIER select DM_MTD because all the defconfig of this platform enables NAND_DENALI_DT. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-02-01mtd: rawnand: denali: set SPARE_AREA_SKIP_BYTES based on DT compatibleMasahiro Yamada
Currently, the denali NAND driver in U-Boot configures the SPARE_AREA_SKIP_BYTES based on the CONFIG option. Recently, Linux kernel merged a patch that associates the proper value for this register with the DT compatible string. Do likewise in U-Boot too. The denali_spl.c still uses CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-01mtd: rawnand: denali_dt: insert udelay() after reset deassertMasahiro Yamada
When the reset signal is de-asserted, the HW-controlled bootstrap starts running unless it is disabled in the SoC integration. It issues some commands to detect a NAND chip, and sets up registers automatically. Until this process finishes, software should avoid any register access. Without this delay function, some of UniPhier boards hangs up while executing nand_scan_ident(). (denali_read_byte() is blocked) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-01mtd: rawnand: denali: Do not reset the block before booting the kernelMarek Vasut
The Denali NAND driver in mainline Linux currently cannot deassert the reset. The upcoming Linux 5.6 will support the reset controlling, and also set up SPARE_AREA_SKIP_BYTES correctly. So, the Denali driver in the future kernel will work without relying on any bootloader or firmware. However, we still need to take care of stable kernel versions for a while. U-boot should not assert the reset of this controller. Fixes: ed784ac3822b ("mtd: rawnand: denali: add reset handling") Signed-off-by: Marek Vasut <marex@denx.de> [yamada.masahiro: reword the commit description] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-01mtd: rawnand: denali_dt: make the core clock optionalMasahiro Yamada
The "nand_x" and "ecc" clocks are currently optional. Make the core clock optional in the same way. This will allow platforms with no clock driver support to use this driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Marek Vasut <marex@denx.de> # On SoCFPGA Arria V
2020-02-01mtd: rawnand: denali-spl: Add missing hardware init on SoCFPGAMarek Vasut
On Altera SoCFPGA, upon either cold-boot or power-on reset, the Denali NAND IP is initialized by the BootROM ; upon warm-reset, the Denali NAND IP is NOT initialized by BootROM. In fact, upon warm-reset, the SoCFPGA BootROM checks whether the SPL image in on-chip RAM is valid and if so, completely skips re-loading the SPL from the boot media. This does sometimes lead to problems where the software left the boot media in inconsistent state before warm-reset, and because the BootROM does not reset the boot media, the boot media is left in this inconsistent state, often until another component attempts to access the boot media and fails with an difficult to debug failure. To mitigate this problem, the SPL on Altera SoCFPGA always resets all the IPs on the SoC early on boot. This results in a couple of register values, pre-programmed by the BootROM, to be lost during this reset. To restore correct operation of the IP on SoCFPGA, these values must be programmed back into the controller by the driver. Note that on other SoCs which do not use the HW-controlled bootstrap, more registers may have to be programmed. This also aligns the SPL behavior with the full Denali NAND driver, which sets these values in denali_hw_init(). Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-01-30net: fix typoFlavio Suligoi
Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
2020-01-30ram: rk3328: only do data traning for cs0Kever Yang
No need to do twice data training for rk3328 ddr sdram, we re-use the setting for both channel. And adjust the sdram_init properly for correct init flow. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: YouMin Chen <cym@rock-chips.com>
2020-01-30arm: rockchip: Add common cru.hJagan Teki
Few of the rockchip family SoC atleast rk3288, rk3399 are sharing some cru register bits so adding common code between these SoC families would require to include both cru include files that indeed resulting function declarations error. So, create a common cru include as cru.h then include the rk3399 arch cru include file and move the common cru register bit definitions into it. The rest of rockchip cru files will add it in future. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-30ram: rk3399: don't assume phy_io_config() uses real regsThomas Hebb
In the RK3399 DRAM driver, the function set_ds_odt() supports operating in two different modes, selected by the ctl_phy_reg argument: when true, the function reads and writes directly from the DRAM registers, accessed through "chan->pctl->denali_*"; when false, the function reads and writes from an array, accessed through "params->pctl_regs.denali_*", which is written to DRAM registers at a later time. However, phy_config_io(), which is called by set_ds_odt() to do a subset of its register operations, operates directly on DRAM registers at all times. This means that it reads incorrect values (and writes new values prematurely) when ctl_phy_reg in set_ds_odt() is false. Fix this by passing in the address of the registers to work with. This prevents an "Invalid DRV value" error in the SPL debug log and (presumably) results in a more correct end state. See the following logs from a RK3399 NanoPi M4 board (4GB LPDDR3): Before: sdram_init() Starting SDRAM initialization... phy_io_config() Invalid DRV value. phy_io_config() Invalid DRV value. sdram_init() sdram_init: data trained for rank 2, ch 0 phy_io_config() Invalid DRV value. phy_io_config() Invalid DRV value. sdram_init() sdram_init: data trained for rank 2, ch 1 Channel 0: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride 256B stride sdram_init() Finish SDRAM initialization... After: sdram_init() Starting SDRAM initialization... sdram_init() sdram_init: data trained for rank 2, ch 0 sdram_init() sdram_init: data trained for rank 2, ch 1 Channel 0: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride 256B stride sdram_init() Finish SDRAM initialization... Signed-off-by: Thomas Hebb <tommyhebb@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-01-29net: Add support for Broadcom GENETv5 Ethernet controllerAmit Singh Tomar
The Broadcom GENET Ethernet MACs are used in several MIPS based SoCs and in the Broadcom 2711/2838 SoC used on the Raspberry Pi 4. There is no publicly available documentation, so this driver is based on the Linux driver. Compared to that the queue management is drastically simplified, also we only support version 5 of the IP and RGMII connections between MAC and PHY, as used on the RPi4. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: heavy cleanup and a few fixes] Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe@baylibre.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-01-29usb: dwc2_udc_otg: add bcm2835 SoC (Raspberry Pi4) supportMarek Szyprowski
Broadcom 2835 SoC requires special conversion of physical memory addresses for DMA purpose, so add needed wrappers to dwc2_udc_otg driver. Also extend the list of compatible devices with 'brcm,bcm2835-usb' entry. This allows to use USB gadget drivers (i.e. DFU) on Raspberry Pi4 boards. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-01-29dfu: mmc: remove file size limit for io operationsMarek Szyprowski
Add support for operations on files larger than CONFIG_SYS_DFU_MAX_FILE_SIZE. The buffered io mechanism is still used for aggregating io requests, so for files up to CONFIG_SYS_DFU_MAX_FILE_SIZE nothing is changed and they will be handled in a single filesystem call. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Lukasz Majewski <lukma@denx.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-01-29dfu: mmc: rearrange the codeMarek Szyprowski
Rename functions for bufferred file io operations to make them easier to understand. Also add missing file offset argument to them (currently unused). All this is a preparation to remove predefined file size limit (CONFIG_SYS_DFU_MAX_FILE_SIZE) for DFU read/write operations. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Lukasz Majewski <lukma@denx.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-10 22:52:44 +0000