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2022-03-28video: nexell: Drop unused and invalid codeSimon Glass
Unfortunately this driver uses the old video structure to store things. This is not supported with driver model. Drop the old code and comment out the other pieces, so the maintainer can take a look. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-28video: Drop cfg_consoleSimon Glass
The non-driver model video support was removed two years ago. Drop this driver, which is only used by nokia_rx51. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-28Merge tag 'v2022.04-rc5' into nextTom Rini
Prepare v2022.04-rc5
2022-03-28mtd: gpmi: fix the bch setting backward compatible issueHan Xu
Previous u-boot code changed the default bch setting behavior and caused backward compatible issue. This fix choose the legacy bch geometry back again as the default option. If the minimum ecc strength that NAND chips required need to be chosen, it can be enabled by either adding DT flag "fsl,use-minimum-ecc" or CONFIG_NAND_MXS_USE_MINIMUM_ECC in configs. The unused flag "fsl,legacy-bch-geometry" get removed. Fixes: 51cdf83eea (mtd: gpmi: provide the option to use legacy bch geometry) Fixes: 616f03daba (mtd: gpmi: change the BCH layout setting for large oob NAND) Tested-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Sean Nyekjaer <sean@geanix.com> Signed-off-by: Han Xu <han.xu@nxp.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
2022-03-28Fix URLs to old freescale git reposPali Rohár
Freescale git repos are now on source.codeaurora.org. Signed-off-by: Pali Rohár <pali@kernel.org>
2022-03-25bootcount: Add pmic pfuze100 bootcount driverPhilip Oberfichtner
Use the MEMA - MEMD registers on the PFUZE100 as bootcount registers. Based on work from Heiko Schocher <hs@denx.de>. Signed-off-by: Philip Oberfichtner <pro@denx.de>
2022-03-25disk: Add an option for partitions in SPLSimon Glass
In some cases we do not want to enable partition support in SPL. Add an option to allow this. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-25pinctrl: Add the pinctrl setting for PWM.Billy Tsai
This patchs add the signal description array for PWM pinctrl settings. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2022-03-25pwm: Add Aspeed ast2600 PWM supportBilly Tsai
This patch add the support of PWM controller which can be found at aspeed ast2600 soc. The pwm supoorts up to 16 channels and it's part function of multi-function device "pwm-tach controller". Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2022-03-25pci: Add defines for normal and subtractive PCI bridgesPali Rohár
Add following two new PCI class codes defines into pci_ids.h include file: PCI_CLASS_BRIDGE_PCI_NORMAL PCI_CLASS_BRIDGE_PCI_SUBTRACTIVE And use these defines in all U-Boot code for describing PCI class codes for normal and subtractive PCI bridges. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-03-25Convert CONFIG_LCD_INFO et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_LCD_INFO CONFIG_LCD_LOGO CONFIG_LCD_INFO_BELOW_LOGO CONFIG_LCD_IN_PSRAM Cc: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-25Convert CONFIG_ATMEL_LCD et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_ATMEL_LCD CONFIG_ATMEL_LCD_BGR555 CONFIG_ATMEL_LCD_RGB565 CONFIG_GURNARD_SPLASH Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-25Convert CONFIG_MII_INIT to KconfigTom Rini
This converts the following to Kconfig: CONFIG_MII_INIT Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-25Convert CONFIG_PHY_RESET_DELAY to KconfigTom Rini
This converts the following to Kconfig: CONFIG_PHY_RESET_DELAY Cc: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-25Convert CONFIG_LPC32XX_ETH to KconfigTom Rini
This converts the following to Kconfig: CONFIG_LPC32XX_ETH Cc: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-25Convert CONFIG_RMII to KconfigTom Rini
This converts the following to Kconfig: CONFIG_RMII Cc: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-23bootcount: clarify documentationMichael Opdenacker
- Grammar fixes - Clarify explanations Signed-off-by: Michael Opdenacker <michael.opdenacker@bootlin.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2022-03-23i2c: fix always-true condition in i2c_probe_chip()Nikita Yushchenko
Per dm_i2c_ops.probe_chip documentation, i2c_probe_chip() shall fallback to default probe method when .probe_chip() returns -ENOSYS. Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2022-03-23misc: atsha204a: fix i2c address readout from DTSAdrian Fiergolski
This patch replaces use fdtdec_get_addr with simpler dev_read_addr(). fdtdec_get_addr doesn't work properly on ZynqMP-based (64bit) system. Although not confirmed, it could be related to the fact, that quoting the documentation, "This variant hard-codes the number of cells used to represent the address and size based on sizeof(fdt_addr_t) and sizeof(fdt_size_t)". Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2022-03-23misc: atsha204a: add delay after sending the messageAdrian Fiergolski
Once request is sent, and before receiving a response, the delay is required. This patch fixes missing delay for before first response try. Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2022-03-23misc: atsha204a: return timeout from wakeup functionAdrian Fiergolski
If the maximum number of wake-up attempts is exceeded, return -ETIMEDOUT. Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2022-03-19Merge tag 'dm-pull-18mar22' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-dm into next binman FIT improvements various minor sandbox improvements
2022-03-18sandbox: Slow down the LCD sync rateSimon Glass
There is seldom a need to refresh at 100Hz and it uses a lot of CPU. Reduce the rate to 10Hz which seems to be adequate. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-18sandbox: Open host file for read-only access if neededSimon Glass
Some files cannot be written but read-only access is still useful for tests. Add a fallback to read-only access when needed. This is useful in CI when opening a large data file provided by docker, where read/write access would result in copying the file, thus needing a lot of extra disk space. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-18net: fec_mxc: Drop CONFIG_FEC_XCV_TYPETom Rini
With all boards now using DM_ETH we determine the value for CONFIG_FEC_XCV_TYPE at run time, except in the case of the default fall-back. Set the fallback directly now. Cc: Fabio Estevam <festevam@gmail.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18net: fec_mxc: Remove non-DM_ETH codeTom Rini
Now that all boards have been converted, remove the non-DM_ETH code. Cc: Fabio Estevam <festevam@gmail.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18rockchip: ram: sdram_rk3x88: replace comma by semicolonJohan Jonker
A comma at the end of a line gives sometimes strange effects in combination with some code formatters, so replace a comma by a semicolon in the sdram_rk3188.c and sdram_rk3288.c files. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-03-18rockchip: saradc: remove double semi-colonGiulio Benetti
Remove double semi-colon that has been forgotten while adding the driver. This is only a style fix since it doesn't change the functionality of the driver. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-03-16Merge tag 'xilinx-for-v2022.07-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.07-rc1 microblaze: - Add support for reserved memory xilinx: - Update FRU code with MAC reading zynqmp: - Remove double AMS setting - DT updates (mostly for SOMs) - Add support for zcu106 rev 1.0 zynq: - Update nand binding nand: - Aligned zynq_nand to upstream DT binding net: - Add support for ethernet-phy-id mmc: - Workaround CD in zynq_sdhci driver also for ZynqMP - Add support for dynamic/run-time SD config for SOMs gpio: - Add driver for slg7xl45106 firmware: - Add support for dynamic SD config power-domain: - Update zynqmp driver with the latest firmware video: - Add skeleton driver for DP and DPDMA i2c: - Fix i2c to work with QEMU pinctrl: - Add driver for zynqmp pinctrl driver
2022-03-16Merge https://source.denx.de/u-boot/custodians/u-boot-mmcTom Rini
- Rockchip, i.MX and xenon_sdhci updates
2022-03-16Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini
- k210 updates
2022-03-16rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3568Alper Nebi Yasak
On RK3568, a register bit must be set to enable Enhanced Strobe. However, it appears that the address of this register may differ from vendor to vendor and should be read from the underlying MMC IP. Let the Rockchip SDHCI driver read this address and set the relevant bit when Enhanced Strobe configuration is requested. The IP uses a custom mode select value (0x7) for HS400, use that instead of the common but non-standard SDHCI_CTRL_HS400 value (0x5). Also add some necessary DLL_STRBIN and DLL_TXCLK configuration for HS400. Additionally, a bit signifying that the connected hardware is an eMMC chip must be set to enable Data Strobe for HS400 and HS400ES modes. Also make the driver set this bit as appropriate. This is partly ported from Linux's Synopsys DWC MSHC driver which happens to be the underlying IP. (drivers/mmc/host/sdhci-of-dwcmshc.c in Linux tree). Co-developed-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-03-16rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3399Alper Nebi Yasak
On RK3399, a register bit must be set to enable Enhanced Strobe. Let the Rockchip SDHCI driver set it when Enhanced Strobe configuration is requested. However, having it set makes the lower-speed modes stop working and makes reinitialization fail, so let it be unset as needed in set_control_reg(). This is mostly ported from Linux's Arasan SDHCI driver which happens to be the underlying IP. (drivers/mmc/host/sdhci-of-arasan.c in Linux tree). Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-03-16mmc: sdhci: Add HS400 Enhanced Strobe supportAlper Nebi Yasak
Delegate setting the Enhanced Strobe configuration to individual drivers if they set a function for it. Return -ENOTSUPP if they do not, like what the MMC uclass does. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-03-16mmc: xenon_sdhci: remove wait_dat0 SDHCI OPRobert Marko
Generic SDHCI driver received support for checking the busy status by polling the DAT[0] level instead of waiting for the worst MMC switch time. Unfortunately, it appears that this does not work for Xenon controllers despite being a part of the standard SDHCI registers and the Armada 3720 datasheet itself telling that BIT(20) is useful for detecting the DAT[0] busy signal. I have tried increasing the timeout value, but I have newer managed to catch DAT_LEVEL bits change from 0 at all. This issue appears to hit most if not all SoC-s supported by Xenon driver, at least A3720, A8040 and CN9130 have non working eMMC currently. So, until a better solution is found drop the wait_dat0 OP for Xenon. I was able to only test it on A3720, but it should work for others as well. Fixes: 40e6f52454fc ("drivers: mmc: Add wait_dat0 support for sdhci driver") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Stefan Roese <sr@denx.de>
2022-03-16mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON when necessaryHaibo Chen
After commit f132aab40327 ("Revert "mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output""), it involve issue in mmc_switch_voltage(), because of the special design of usdhc. For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, these are reserved bits(Though RM contain the definition of these bits, but actually internal IC logic do not implement, already confirm with IC team). Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the card clock output. Here is the definition of this bit in RM: [8] FRC_SDCLK_ON Force CLK output active Do not set this bit to 1 unless it is necessary. Also, make sure that this bit is cleared when uSDHC’s clock is about to be changed (frequency change, clock source change, or delay chain tuning). 0b - CLK active or inactive is fully controlled by the hardware. 1b - Force CLK active In default, the FRC_SDCLK_ON is 0. This means, when there is no command or data transfer on bus, hardware will gate off the card clock. But in some case, we need the card clock keep on. Take IO voltage 1.8v switch as example, after IO voltage change to 1.8v, spec require gate off the card clock for 5ms, and gate on the clock back, once detect the card clock on, then the card will draw the dat0 to high immediately. If there is not clock gate off/on behavior, some card will keep the dat0 to low level. This is the reason we fail in mmc_switch_voltage(). To fix this issue, and concern that this is only the fsl usdhc hardware design limitation, set the bit FRC_SDCLK_ON in the beginning of the wait_dat0() and clear it in the end. To make sure the 1.8v IO voltage switch process align with SD specification. For standard tuning process, usdhc specification also require the card clock keep on, so also add these behavior in fsl_esdhc_execute_tuning(). Reviewed-by: Marek Vasut <marex@denx.de> Tested-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-03-15Merge tag 'u-boot-stm32-20220315' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-stm mtd: add NAND write protect support to stm32_fmc2_nand stm32mp1 bsec: Add permanent lock write support stm32mp1 bsec: Add dev in function description cmd_stboard: Update test on misc_read() result video: fix the check of return value of clk_set_rate in stm32_ltdc DT: Alignment with kernel v5.17 for stm32mp15 DT: Add USB OTG pinctrl and regulator in SPL for DHCOR DT: Move vdd_io extras into Avenger96 extras DT: Add DFU support for DHCOM recovery ram: stm32mp1: Unconditionally enable ASR psci: Implement PSCI system suspend and DRAM SSR for stm32mp
2022-03-15pinctrl: k210: Fix bias-pull-upNiklas Cassel
Using bias-pull-up would actually cause the pin to have its pull-down enabled. Fix this. Original Linux patch by Sean Anderson: https://lore.kernel.org/linux-gpio/20220209182822.640905-1-seanga2@gmail.com/ Fixes: 7224d5ccf8e1 ("pinctrl: Add support for Kendryte K210 FPIOA") Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-03-15pinctrl: k210: Fix loop in k210_pc_get_drive()Niklas Cassel
The loop exited too early so the k210_pc_drive_strength[0] array element was never used. Original Linux patch by Dan Carpenter: https://lore.kernel.org/linux-gpio/20220209180804.GA18385@kili/ Fixes: 7224d5ccf8e1 ("pinctrl: Add support for Kendryte K210 FPIOA") Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-03-15spi: dw: Actually mask interruptsSean Anderson
The designware spi driver unconditionally uses polling. The comment to spi_hw_init() also states that the function should disable interrupts. According to the DesignWare DW_apb_ssi Databook, value 0xff in IMR enables all interrupts. Since we want to mask all interrupts write 0x0 instead. On the canaan k210 board, pressing the reset button twice to reset the board will run u-boot. If u-boot boots Linux without having SPI interrupts masked, Linux will hang as soon as interrupts are enabled, because of an interrupt storm. Properly masking the SPI interrupts in u-boot allows us to successfully boot Linux, even after resetting the board. Fixes: 5bef6fd79f94 ("spi: Add designware master SPI DM driver used on SoCFPGA") Signed-off-by: Sean Anderson <seanga2@gmail.com> [Niklas: rewrite commit message] Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-03-15spi: dw: Force set K210 fifo length to 31Damien Le Moal
The Canaan Kendryte K210 SoC DW apb_ssi v4 spi controller is documented to have a 32 word deep TX and RX FIFO, which spi_hw_init() detects. However, when the RX FIFO is filled up to 32 entries (RXFLR = 32), an RX FIFO overrun error occurs. Avoid this problem by force setting fifo_len to 31. Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-03-15k210: dts: align fpioa node with LinuxDamien Le Moal
Linux kernel fpioa pinctrl driver expects the sysctl phandle and the power bit offset of the fpioa device to be specified as a single property "canaan,k210-sysctl-power". Replace the "canaan,k210-sysctl" and "canaan,k210-power-offset" properties with "canaan,k210-sysctl-power" to satisfy the Linux kernel requirements. This new property is parsed using the existing function dev_read_phandle_with_args(). Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-03-15k210: use the board vendor name rather than the marketing nameDamien Le Moal
"kendryte" is the marketing name for the K210 RISC-V SoC produced by Canaan Inc. Rather than "kendryte,k210", use the usual "canaan,k210" vendor,SoC compatibility string format in the device tree files and use the SoC name for file names. With these changes, the device tree files are more in sync with the Linux kernel DTS and drivers, making uboot device tree usable by the kernel. Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-03-15ram: stm32mp1: Unconditionally enable ASRMarek Vasut
Enable DRAM ASR, auto self-refresh, unconditionally. This saves non-trivial amount of power both at runtime and in suspend (on 2x W632GU6NB-15 ~150mW). Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com>
2022-03-15video: stm32: stm32_ltdc: fix the check of return value of clk_set_rate()Gabriel Fernandez
The clk_set_rate() function returns rate as an 'ulong' not an 'int' and rate > 0 by default. This patch avoids to display the associated warning when the set rate function returns the new frequency. Fixes: aeaf330649e8 ("video: stm32: stm32_ltdc: add bridge to display controller") Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-03-15mtd: rawnand: stm32_fmc2: add NAND Write Protect supportChristophe Kerello
This patch adds the support of the WP# signal. WP will be disabled before the first access to the NAND flash. Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-03-14Merge https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini
- Bugfix for dwc2 USB driver.
2022-03-14Merge tag 'video-20220314' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-video - fix display of the u-boot logo on Apple devices - convert Nokia RX-51 to CONFIG_DM_VIDEO
2022-03-14Merge tag 'v2022.04-rc4' into nextTom Rini
Prepare v2022.04-rc4
2022-03-14phy: cadence: Sierra: Move the link operations from serdes phy to link deviceAswath Govindraju
In commit 6f46c7441a9f ("phy: cadence: Sierra: Add a UCLASS_PHY device for links"), a separate udevice of type UCLASS_PHY was created for each link. Therefore, move the corresponding link operations under the link device. Also, change the uclass of sierra phy to UCLASS_MISC as it is no longer the phy device. Fixes: 6f46c7441a9f ("phy: cadence: Sierra: Add a UCLASS_PHY device for links") Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Georgi Vlaev <g-vlaev@ti.com>