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2022-12-12dm: pmic: ignore disabled node in pmic_bind_childrenPatrick Delaunay
Ignore the disabled children node in pmic_bind_children() so the disabled regulators in device tree are not registered. This patch is based on the dm_scan_fdt_node() code - only the activated nodes are bound - and it solves possible issue when a deactivated regulator is bound, error for duplicated regulator name for example. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-12phy: usbphyc: use regulator_set_enable_if_allowed for disabling vbus supplyPatrick Delaunay
Use regulator_set_enable_if_allowed() api instead of regulator_set_enable() while disabling vbus supply. This way the driver doesn't see an error when it disable an always-on regulator for VBUS. This patch is needed for STM32MP157C-DK2 board when the regulator v3v3: buck4 used as the phy vbus supply in kernel device tree is always on with the next hack for low power use-case: &usbphyc_port0 { ... /* * Hack to keep hub active until all connected devices are suspended * otherwise the hub will be powered off as soon as the v3v3 is disabled * and it can disturb connected devices. */ connector { compatible = "usb-a-connector"; vbus-supply = <&v3v3>; }; }; Without this patch and the previous update in DT the command "usb stop" failed and the next command "usb start" cause a crash. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Marek Vasut <marex@denx.de>
2022-12-10mtd: nand: mxs_nand_spl: don't read useless pagesDario Binacchi
The patch prevents pages beyond the last from being unnecessarily read. This occurs when the last page to be read is not the last page of the last block. Before this change we would have read all the pages up to the end of the last block. Suggested-by: Michael Trimarchi <michael@amarulasolutions.com> Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-by: Michael Trimarchi <michael@amarulasolutions.com> Link: https://lore.kernel.org/all/20221120095705.3019295-1-dario.binacchi@amarulasolutions.com
2022-12-10mtd: nand: drop EXPORT_SYMBOL_GPL for nanddev_erase()Dario Binacchi
This function is only used within this module, so it is no longer necessary to use EXPORT_SYMBOL_GPL(). This patch parallels the work done in the following patch: https://lore.kernel.org/linux-mtd/20221018170205.1733958-1-dario.binacchi@amarulasolutions.com Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com> Link: https://lore.kernel.org/all/20221108090719.3631621-1-dario.binacchi@amarulasolutions.com
2022-12-10mtd: nand: make Samsung SLC NAND usable againMichael Trimarchi
Upstream linux commit 69fc01296c9281 commit a1286a1fc416 ("mtd: nand: Move Samsung specific init/detection logic in nand_samsung.c") introduced a regression for Samsung SLC NAND chips. Prior to this commit chip->bits_per_cell was initialized by calling nand_get_bits_per_cell() before using nand_is_slc(). With the offending commit this call is skipped, leaving chip->bits_per_cell cleared to zero when the manufacturer specific '.detect' function calls nand_is_slc() which in turn interprets bits_per_cell != 1 as indication for an MLC chip. The effect is that e.g. a K9F1G08U0F NAND chip is falsely detected as MLC NAND with 4KiB page size rather than SLC with 2KiB page size. Add a call to nand_get_bits_per_cell() before calling the .detect hook function in nand_manufacturer_detect(), so that the nand_is_slc() calls in the manufacturer specific code will return correct results. Reported-by: Marcin Gołaś <marcingol30@gmail.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Link: https://lore.kernel.org/all/20221021060536.11747-1-michael@amarulasolutions.com Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-12-10mtd: rawnand: omap_gpmc: Reduce .bss usageRoger Quadros
Allocate omap_ecclayout on the heap as we have limited .bss space on AM64 R5 SPL configuration. Reduces .bss usage by 2984 bytes. Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com> Link: https://lore.kernel.org/all/20221011115012.6181-9-rogerq@kernel.org Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-12-10mtd: rawnand: nand_spl_loaders: Fix cast type build warningRoger Quadros
Fixes the below build warning on 64-bit platforms. drivers/mtd/nand/raw/nand_spl_loaders.c:26:21: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] dst = (void *)((int)dst - page_offset); Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Link: https://lore.kernel.org/all/20221011115012.6181-8-rogerq@kernel.org Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-12-10mtd: rawnand: omap_gpmc: Optimize NAND readsRoger Quadros
Rename omap_nand_read() to omap_nand_read_buf() to reflect actual behaviour. Use FIFO read address instead of raw read address for reads. The GPMC automatically converts 32-bit/16-bit reads to NAND device specific reads (8/16 bit). Use the largest possible read granularity size for more efficient reads. Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Link: https://lore.kernel.org/all/20221011115012.6181-5-rogerq@kernel.org Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-12-10mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platformsRoger Quadros
Pointer size cannot be assumed to be 32-bit, so use use uintptr_t instead of uint32_t. Fixes the below build warning on 64-bit builds. drivers/mtd/nand/raw/omap_gpmc.c:439:10: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] head = ((uint32_t) buf) % 4; Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Link: https://lore.kernel.org/all/20221011115012.6181-4-rogerq@kernel.org Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-12-10mtd: rawnand: omap_gpmc: Enable build for K2/K3 platformsRoger Quadros
The GPMC module is present on some K2 and K3 SoCs. Enable building GPMC NAND driver for K2/K3 platforms. Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com> Link: https://lore.kernel.org/all/20221011115012.6181-3-rogerq@kernel.org Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-12-10mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.hRoger Quadros
We want to get rid of <asm/arch/mem.h> so don't enforce it for new platforms. This also means GPMC_MAX CS doesn't have to be defined by platform code. Define it locally here for now. Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Link: https://lore.kernel.org/all/20221011115012.6181-2-rogerq@kernel.org Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-12-08Merge tag 'u-boot-stm32-20221207' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-stm - Drop MMCI interrupt-names in STM32H743, STM32MP15 and STM322MP13 DT DHSOM: - Enable assorted ST specific commands - Add version variable - Add boot counter STM32MP13: - Add sdmmc cd-gpios for STM32MP135F-DK - Add clock & reset support STM32 ADC: - Split channel init into several routines - Add support of generic channels binding
2022-12-08usb: gadget: rndis: Prevent InformationBufferOffset manipulationSzymon Heidrich
Prevent access to arbitrary memory locations in gen_ndis_set_resp via manipulation of buf->InformationBufferOffset. Original implementation permits manipulation of InformationBufferOffset to exploit OID_GEN_CURRENT_PACKET_FILTER to set arbitrary memory contents within a 32byte offset as the devices packet filter. The packet filter value may be next retrieved using gen_ndis_query_resp so it is possible to extract specific memory regions two bytes a time. The rndis_query_response was not modified as neither the buffer offset nor length passed to gen_ndis_query_resp is used. Signed-off-by: Szymon Heidrich <szymon.heidrich@gmail.com>
2022-12-08usb: gadget: dfu: Fix check of transfer directionHugo SIMELIERE
Commit fbce985e28eaca3af82afecc11961aadaf971a7e to fix CVE-2022-2347 blocks DFU usb requests. The verification of the transfer direction was done by an equality but it is a bit mask. Signed-off-by: Hugo SIMELIERE <hsimeliere.opensource@witekio.com> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Sultan Qasim Khan <sultan.qasimkhan@nccgroup.com> Reviewed-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de>
2022-12-07adc: stm32mp15: add support of generic channels bindingOlivier Moysan
Add support of generic IIO channels binding: ./devicetree/bindings/iio/adc/adc.yaml Keep support of st,adc-channels for backward compatibility. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-12-07adc: stm32mp15: split channel init into several routinesOlivier Moysan
Split stm32_adc_chan_of_init channel initialization function into several routines to increase readability and prepare channel generic binding handling. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-12-07clk: stm32mp13: introduce STM32MP13 RCC driverGabriel Fernandez
STM32MP13 RCC driver uses Common Clock Framework and also a 'clk-stm32-core' API. Then STM32MPx RCC driver will contain only data configuration (gates, mux, dividers and the way to check security) or some specific clocks. This API will be used by all new other generations of ST Socs. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Tested-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-12-05test: test sandbox sound driver more rigorouslyHeinrich Schuchardt
Consider unexpected values for frequency: * negative frequency * zero frequency * frequency exceeding sampling frequency As in these cases the sum of the samples is zero also check the count of the samples. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05sound: avoid endless loopHeinrich Schuchardt
'sound play 1 100000' results in an endless loop on the sandbox. If the frequency exceeds half the sampling rate, zero out the output buffer. Fixes: 511ed5fdd389 ("SOUND: SAMSUNG: Add I2S driver") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05Merge tag 'xilinx-for-v2023.01-rc3-v2' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2023.01-rc3-v2 xilinx: - Fix MAC address selection for System Controller from FRU - Cleanup Kconfig (ZYNQ_MAC_IN_EEPROM symbol) versal: - Create u-boot.elf for mini spi configurations versal-net: - Enable MT35XU flash zynq: - Add missing timer to DT for mini configurations zynqmp: - Do not include psu_init to U-Boot by default - Do not enable IPI by default to mini U-Boot - Update Luca's fragment - Fix SPL_FS_LOAD_PAYLOAD_NAME usage spi: - gqspi: Fix tapdelay values - gqspi: Fix 64bit address support - cadence: Remove condition for calling enable linear mode - nor-core: Invert logic to reflect sst26 flash unlocked net: - Add PCS/PMA phy support
2022-12-05mtd: spi-nor-core: Invert logic to reflect sst26 flash unlockedAlgapally Santosh Sagar
flash_is_locked is changed to flash_is_unlocked with commit 513c6071ce73 ("mtd: spi: Convert is_locked callback to is_unlocked"). sst26_is_locked() is also changed to sst26_is_unlocked() but the logic remained same. Invert the logic for the flash lock/unlock to work properly. Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Reviewed-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20221122051833.13306-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05spi: cadence-qspi: Remove condition for calling enable linear modeAshok Reddy Soma
cadence_qspi_apb_enable_linear_mode() has a weak function defined, so no need to gaurd this under if (CONFIG_IS_ENABLED(ARCH_VERSAL)). In cadence_qspi_apb_write_execute(), enable linear mode is called twice by mistake, remove extra one. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20221129114134.18909-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05spi: zynqmp_qspi: Add support for 64-bit read/writeVenkatesh Yadav Abbarapu
When we pass the 64-bit address to read/write, only lower 32-bit address is getting updated. Program the upper 32-bit address in the DMA destination memory address MSBs register, which can handle upto 44-bit destination address. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20221125104413.26140-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05spi: zynqmp_gqspi: Update tapdelay valueT Karthik Reddy
The driver was using an incorrect value for GQSPI_LPBK_DLY_ADJ_DLY_1 tapdelay for Versal for frequencies above 100MHz. Change it from 2 to 1 based on the recommended value in IP spec. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20221123090451.11409-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05net: xilinx_axi: check PCS/PMA PHY status in setup_phyAndy Chiu
Both PCS/PMA PHY and the external PHY need to have a valid link status in order to have Ethernet traffic. Check and wait this status at setup_phy() so that we could diagnose if there is a PHY issue. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Reviewed-by: Greentime Hu <greentime.hu@sifive.com> Link: https://lore.kernel.org/r/20221101035800.912644-3-andy.chiu@sifive.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05net: xilinx_axi: add PCS/PMA PHYAndy Chiu
If we bridge an external PHY to Xilinx's PCS/PMA PHY and would like to get and set the real status of the PHY facing the external world. Then we should phy_connect() to the external PHY instead of the PCS/PMA one. Thus, we add a pcs-handle DT entry, which have been merged in Linux, and leave the configuration of it to the driver itself. Unlike Linux, where the PCS/PMA PHY is managed by phylink, managing the PCS/PMA PHY is only internal to the driver in U-Boot. The PCS/PMA PHY pressents only when the phy-mode is configured as SGMII or 1000Base-X, so it is always 1 Gbps and full-duplex and we may skip passing link information out. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Reviewed-by: Greentime Hu <greentime.hu@sifive.com> Link: https://lore.kernel.org/r/20221101035800.912644-2-andy.chiu@sifive.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05i2c: nuvoton: renamed the NPCM i2c driverJim Liu
The Makefile name is npcm_i2c but the driver is npcm-i2c. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2022-12-02bus: Optionally include TI sysc driver in SPL/TPLPaul Barker
The TI sysc bus driver is required to allow access to the SPI bus on am335x platforms. To support SPI boot this driver needs to be enabled in the SPL/TPL as appropriate. Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2022-12-02bus: TI sysc driver requires DMPaul Barker
This driver does not build if CONFIG_DM is disabled as it uses the function `dev_get_priv`. Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2022-12-02dm: core: Fix iteration over driver_info recordsPaul Barker
We should only perform additional iteration steps when needed to initialize the parent of a device. Other binding errors (such as a missing driver) should not lead to additional iteration steps. Unnecessary iteration steps can cause issues when memory is tightly constrained (such as in the TPL/SPL) since device_bind_by_name() unconditionally allocates memory for a struct udevice. On the SanCloud BBE this led to boot failure caused by memory exhaustion in the SPL when booting from SPI flash. Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2022-11-28phy: add driver for Intel XWAY PHYTim Harvey
Add a driver for the Intel XWAY GbE PHY: - configure RGMII using dt phy-mode and standard delay properties - use genphy_config Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-11-28net: macb: Fix race caused by flushing unwanted descriptorsYaron Micher
The rx descriptor list is in cached memory, and there may be multiple descriptors per cache-line. After reclaim_rx_buffers marks a descriptor as unused it does a cache flush, which causes the entire cache-line to be written to memory, which may override other descriptors in the same cache-line that the controller may have written to. The fix skips freeing descriptors that are not the last in a cache-line, and if the freed descriptor is the last one in a cache-line, it marks all the descriptors in the cache-line as unused. This is similarly to what is done in drivers/net/fec_mxc.c In my case this bug caused tftpboot to fail some times when other packets are sent to u-boot in addition to the ongoing tftp (e.g. ping). The driver would stop receiving new packets because it is waiting on a descriptor that is marked unused, when in reality the descriptor contains a new unprocessed packet but while freeing the previous buffer descriptor & flushing the cache, the driver accidentally marked the descriptor as unused. Signed-off-by: Yaron Micher <yaronm@hailo.ai>
2022-11-28drivers: net: aquantia: fix typosTim Harvey
Fix a couple of typos: - s/Acquantia/Aquantia/ - s/firmare/firmware/ Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-28net: dwc_eth_qos: Add support for bulk RX descriptor cleaningMarek Vasut
Add new desc_per_cacheline property which lets a platform run RX descriptor cleanup after every power-of-2 - 1 received packets instead of every packet. This is useful on platforms where (axi_bus_width EQOS_AXI_WIDTH_n * DMA DSL inter-descriptor word skip count + DMA descriptor size) is less than cache line size, which necessitates packing multiple DMA descriptors into single cache line. In case of TX descriptors, this is not a problem, since the driver always does synchronous TX, i.e. the TX descriptor is always written, flushed and polled for completion in eqos_send(). In case of RX descriptors, it is necessary to update their status in bulk, i.e. after the entire cache line worth of RX descriptors has been used up to receive data. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-28net: dwc_eth_qos: Split TX and RX DMA ringsMarek Vasut
Separate TX and RX DMA rings to make their handling slightly clearer. This is a preparatory patch for bulk RX descriptor flushing. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-28liteeth: LiteX Ethernet deviceJoel Stanley
LiteX is a soft system-on-chip that targets FPGAs. LiteETH is a basic network device that is commonly used in LiteX designs. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-27usb: dwc3: Drop support for "snps, ref-clock-period-ns" DT propertyMarek Vasut
Drop support for quickly deprecated DT property "snps,ref-clock-period-ns" to prevent its proliferation. Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de>
2022-11-27usb: dwc3: Program GFLADJSean Anderson
GUCTL.REFCLKPER can only account for clock frequencies with integer periods. To address this, program REFCLK_FLADJ with the relative error caused by period truncation. The formula given in the register reference has been rearranged to allow calculation based on rate (instead of period), and to allow for fixed-point arithmetic. Additionally, calculate a value for 240MHZDECR. This configures a simulated 240Mhz clock using a counter with one fractional bit (PLS1). This register is programmed only for versions >= 2.50a, since this is the check also used by commit db2be4e9e30c ("usb: dwc3: Add frame length adjustment quirk"). [ marek: Ported from Linux kernel commit 596c87856e08d ("usb: dwc3: Program GFLADJ") ] Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux
2022-11-27usb: dwc3: Calculate REFCLKPER based on reference clockSean Anderson
Instead of using a special property to determine the reference clock period, use the rate of the reference clock. When we have a legacy snps,ref-clock-period-ns property and no reference clock, use it instead. Fractional clocks are not currently supported, and will be dealt with in the next commit. [ marek: Ported from Linux kernel commit 5114c3ee24875 ("usb: dwc3: Calculate REFCLKPER based on reference clock") ] Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux
2022-11-27usb: dwc3: reference clock period configurationBalaji Prakash J
Set reference clock period when it differs from dwc3 default hardware set. We could calculate clock period based on reference clock frequency. But this information is not always available. This is the case of PCI bus attached USB host. For that reason we use a custom property. Tested (USB2 only) on IPQ6010 SoC based board with 24 MHz reference clock while hardware default is 19.2 MHz. [ baruch: rewrite commit message; drop GFLADJ code; remove 'quirk-' from property name; mention tested hardware ] [ marek: Ported from Linux kernel commit 7bee318838890 ("usb: dwc3: reference clock period configuration") ] Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux
2022-11-27usb: dwc3: Cache ref_clk pointer in struct dwc3Marek Vasut
Cache ref_clk clock pointer in struct dwc3 . This is a preparatory patch for subsequent backports from Linux kernel which configure GFLADJ register content based on the ref_clk rate and therefore need access to the ref_clk pointer. It is possible to extract the clock pointer from existing clk_bulk list of already claimed clock, no need to call clk_get*() again. Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de>
2022-11-27usb: Expand buffer size in usb_find_and_bind_driver()Marek Vasut
The "generic_bus_%x_dev_%x" string which is printed into this buffer can be up to 34 characters long ("generic_bus_12345678_dev_12345678"). The buffer would be clipped by snprintf() if both %x were at maximum range. Make sure the buffer is long enough to cover such possibility. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-24ram: ast2600: Align the RL and WL settingDylan Hung
Use macro to represent the RL and WL setting to ensure the PHY and controller setting are aligned. Review-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-11-24ram: ast2600: Improve ddr4 timing and signal qualityDylan Hung
Adjust the following settings to get better timing and signal quality. 1. write DQS/DQ delay - 1e6e2304[0] - 1e6e2304[15:8] 2. read DQS/DQ delay - 0x1e6e0298[0] - 0x1e6e0298[15:8] 3. CLK/CA timing - 0x1e6e01a8[31] 4. Read and write termination - change RTT_ROM from 40 ohm to 48 ohm (MR1[10:8]) - change RTT_PARK from disable to 48 ohm (MR5[8:6]) - change RTT_WR from 120 ohm to disable (MR2[11:9]) - change PHY ODT from 40 ohm to 80 ohm (0x1e6e0130[10:8]) Note1: Both DDR-PHY and DDR controller have their own registers for DDR4 Mode Registers (MR0~MR6). This patch introduces macros to synchronize the MR value on both sides. Note2: the waveform meansurement can be found in item #21 of Aspeed AST26x0 Application note (AP note). Review-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-11-24ram: ast2600: Fix incorrect statement of the register pollingDylan Hung
The condition "~data" in the if-statement is a typo. The original intention is to poll if SDRAM_PHYCTRL0_INIT bit equals to 0. So use "data == 0" for instead. Besides, the bit[1] of "phy_status" register is hardwired to SDRAM_PHYCTRL0_INIT (with inverse logic). Since SDRAM_PHYCTRL0_INIT has already done, remove the unnecessary checking of phy_status[1]. Fixes: fde93143469f ("ram: aspeed: Add AST2600 DRAM control support") Review-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-11-23Merge tag 'u-boot-amlogic-20221122' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-amlogic - Implement setbrg op to meson serial device - Re-add the old PHY reset binding for nanopi-k2
2022-11-22sandbox: check lseek return value in handle_ufi_commandHeinrich Schuchardt
Invoking lseek() may result in an error. Handle it. Addresses-Coverity-ID: 376212 ("Error handling issues (CHECKED_RETURN)") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-11-22arm: amlogic: add setbrg op to serial deviceEdoardo Tomelleri
Implement setbrg in amlogic/meson serial device with driver model similar to how the meson_uart.c driver does it in Linux. Also configure (probe) the serial device with the new reg5 register. Signed-off-by: Edoardo Tomelleri <e.tomell@gmail.com> Link: https://lore.kernel.org/r/20220918161701.572814-1-e.tomell@gmail.com Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2022-11-22Merge tag 'xilinx-for-v2023.01-rc3' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2023.01-rc3 microblaze: - Enable 32 bit addressing mode for SPIs zynq: - Minor DT fixes (PL clock enabling) zynqmp: - Disable watchdog by default - Remove unused xlnx,eeprom chosen support - Add missing symlink for vck190 SC revB - Use mdio bus with ethernet-phy-id description versal: - Add mini qspi/ospi configuration versal-net: - Add soc driver - Fix Kconfig entry for SOC - Fix loading address location for MINI configuration - Disable LMB for mini configuration net: - Fix ethernet-phy-id usage in the code pinctrl: - Revert high impedance/output enable support timer: - Fix timer relocation for Microblaze - Fix timer wrap in 32bit Xilinx timer driver
2022-11-22spi: cadence-qspi: Fix compilation error in mini u-boot flash resetAshok Reddy Soma
When cadence_qspi_versal_flash_reset() function is called in mini u-boot where there is no firmware support, it is missing defines for macro's BOOT_MODE_POR_0 & BOOT_MODE_POR_1. Remove them and replace with already define macro's which have same values as these. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20221116141155.14788-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
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