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2018-01-19GPIO: tca642x: Rework to not include commands in SPLTom Rini
The command portion of the GPIO driver can only be used in full SPL so re-work to guard the command related portions and mark it as static. Cc: Dan Murphy <dmurphy@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2018-01-19GPIO: pca953x: Rework to not include commands in SPLTom Rini
The command portion of the GPIO driver can only be used in full SPL so re-work to guard the command related portions and mark it as static. Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-19drivers: dma: ti-edma3: add support for memory fillTero Kristo
Add support for simple memory fill operation. With large data sizes it is much faster to use EDMA for memory fill rather than CPU. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-01-19mmc: omap_hsmmc: Fix incorrect bit operations for disabling a bitKishon Vijay Abraham I
omap_hsmmc driver uses "|" in a couple of places for disabling a bit. While it's okay to use it in "mmc_reg_out" (since mmc_reg_out has a _mask_ argument to take care of resetting a bit), it's incorrectly used for resetting flags in "omap_hsmmc_send_cmd". Fix it here by using "&= ~()" to reset a bit. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-19mmc: omap_hsmmc: Enable Auto command (CMD12) enableKishon Vijay Abraham I
Instead of sending STOP TRANSMISSION command from MMC core, enable the auto command feature so that the Host Controller issues CMD12 automatically when last block transfer is completed. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-19mmc: omap_hsmmc: Add support for DMA (ADMA2)Kishon Vijay Abraham I
The omap hsmmc host controller can have the ADMA2 feature. It brings better read and write throughput. On most SOC, the capability is read from the hl_hwinfo register. On OMAP3, DMA support is compiled out. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-18Revert "omap_hsmmc: update struct hsmmc to accommodate omap3 from DT"Jean-Jacques Hiblot
This reverts commit 46831c1a4cda75d92f7ad18d4e2b1eb196c62b2f. This reserved area at the beginning of struct hsmm, will be used later to support ADMA Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-17Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2018-01-16i2c: mxc_i2c: Use or operationPeng Fan
The operation should be OR, not BIT OR. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Heiko Schocher <hs@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2018-01-16i2c: lpi2c: do not add 4 for bus seqPeng Fan
The number 4 is dedicated on i.MX7ULP, but lpi2c will be reused on i.MX8, 4 is not valid. The seq number could be configured by alias node. The following patch will use i2c4 as the begin for i.MX7ULP. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-01-15Merge git://git.denx.de/u-boot-netTom Rini
2018-01-15Merge git://git.denx.de/u-boot-imxTom Rini
2018-01-15db410c: replace reset driver with psciJorge Ramirez-Ortiz
this should be the norm for armv8 platforms. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2018-01-15db820c: enable pmic gpios for pm8994Jorge Ramirez-Ortiz
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2018-01-15serial: lpuart: Proper device identificationSriram Dash
Identify and distinguish between platform device type of MX7ULP and LS1021A. This is a fix to commit 7edf5c45("serial: lpuart: add i.MX7ULP support"). Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-15phy: atheros: set auto-negotiation for AR8021Zhao Qiang
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: sh-eth: Add to Kconfig and convertNobuhiro Iwamatsu
This adds SH_ETHER to drivers/net/Kconfig and convert to Kconfig. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: sh-eth: Fix misaligned cache operation warningNobuhiro Iwamatsu
When we using network on board using sh-eth, it prints a lot of "CACHE: Misaligned operation at range" messages. This commit fixes this problem. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: sh-eth: Change read/write() param to struct sh_eth_infoNobuhiro Iwamatsu
This changes Change structure used in sh_eth_read and sh_eth_write function from struct sh_eth_dev to struct sh_eth_info. This is necessary to convert to Driver Model. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: sh-eth: Remove bd_t from sh_eth_config()Nobuhiro Iwamatsu
bd_t is not used in sh_eth_config(). This deletes bd_t from sh_eth_config() Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: sh-eth: Fix coding style checked by checkpatch.plNobuhiro Iwamatsu
This fixes the chord style checked by checkpatch.pl. Details of change details are as follows: - Fix typo Change from alligned to aligned. - Remove whitespace before ',' - Add spaces preferred around that '|' - Fix missing a blank line after declarations - Remove space after a cast declaration - Fix format of block comments - Add a blank line after function/struct/union/enum declarations Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: phy: b53: Add b53_reg read/write commandsFlorian Fainelli
Add a b53_reg read/write command which allows inspecting the switch registers. Because the Broadcom BCM53xx registers have different sizes, we need to split the accesses in 8, 16, 32, 48 or 64 bits to obtain expected results. Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-01-15net: designware: Pad small packetsFlorian Fainelli
Make sure that we pad small packets to a minimum length of 60 bytes (without FCS). This is necessary to interface with Ethernet switches that will reject RUNT frames unless padded correctly. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-01-15net: phy: Add Broadcom BCM53xx switch driverFlorian Fainelli
Add a minimalistic Broadcom BCM53xx (roboswitch) switch driver similar to the Marvell MV88E617x. This takes care of configuring the minimum amount out of the switch hardware such that each user visible port (configurable) and the CPU port can forward packets between each other while preserving isolation with other ports. This is useful for e.g: the Lamobo R1 board featuring a Broadcom BCM53125 switch. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-01-15net: designware: add clock supportPatrice Chotard
This implementation manages several clocks, disable and free all of them in case of error during probe and in remove callback. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15dm: core: add missing dev_count_phandle_with_args()Patrice Chotard
Add missing dev_count_phandle_with_args() to avoid compilation issue. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: mvneta - Fixed recv() when multiple packets have arrived.Jason Brown
This patch fixes a problem in the mvneta driver where if more than one packet arrives between calls to mvneta_recv(), the additional descriptors will be marked as free even though only one descriptor has been read and processed from the receive queue. This causes the additional packet(s) to be delayed until the next packet arrives. >From this point on all packets will be delayed because the receive queue will contain unprocessed packets but the hardware shows no busy descriptors. Signed-off-by: Jason Brown <jason.brown@apcon.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: miiphybb: fix casting errorChris Brandt
Since the return value is a signed int, if the leading MSB of rdreg is a 1, it will get signed extended and will return a negative value which is an error even though we read the correct value. Fixes: dfcc496ed7e2 ("net: mii: Changes not made by spatch") Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: sh-eth: remove sh_eth_offset_rz tableChris Brandt
First, this table could never be included in the build anyway because SH_ETH_TYPE_RZ is not defined until later in the file. Second, the register PIR was missing, so PHY MDIO never worked. Third, after adding the PIR register, the table is EXACTLY the same as sh_eth_offset_gigabit, so there is no value to it. Therefore, just delete it use the gigabit one. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: sh-eth: fix inl and outl definitionsChris Brandt
The macros inl and outl maybe already be defined from file arch/arm/include/asm/io.h so there may be no reason to define them. And if you do try defined them here, you get a redefined complier warning. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: phy: marvell: Add functions to read PHY's extended registersLukasz Majewski
This commit allows extended Marvell registers to be read with: foo > mdio rx FEC 3.10 Reading from bus FEC PHY at address 0: 3.16 - 0x1063 foo > mdio wx FEC 3.10 0x1011 The above code changes the way ETH connector LEDs blink. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: York Sun <york.sun@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: Fix buffer overrun error in netconsoleJoe Hershberger
Need to not access the byte after the input_buffer. Reported-by: Coverity (CID: 144423) Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: macb: Add support for Xilinx Zynq SoCWilson Lee
Although Xilinx Zynq SoC was using MACB similar hardware. However, U-boot MACB driver was not supporting Xilinx Zynq SoC. This patch is to add support for the Xilinx Zynq SoC to the existing MACB network driver. This patch is to add Zynq GEM DMA Config, provide callback function for different linkspeed for case of using Xilinx Zynq Programmable Logic as GMII to RGMII converter. This patch convert the return value to use error codes. Signed-off-by: Wilson Lee <wilson.lee@ni.com> Cc: Chen Yee Chew <chen.yee.chew@ni.com> Cc: Keng Soon Cheah <keng.soon.cheah@ni.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15dm: core: parse chosen nodeRob Clark
This is the node that would contain, for example, the framebuffer setup by an earlier stage. Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-01-15spmi: msm: display the PMIC Arb version (debug)Jorge Ramirez-Ortiz
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2018-01-14Merge git://git.denx.de/u-boot-mmcTom Rini
2018-01-13mmc: fsl_esdhc: Fix eMMC 1.8v setting issuePeng Fan
Current USDHC driver will reset VSELECT to 0 (3.3v) during mmc init, then set to 1 for 1.8v eMMC I/O. When booting from eMMC, since ROM has already set VSELECT to 1.8v before running the u-boot. This reset in USDHC driver causes a short 2.2v pulse on CMD pin. Fix this issue by not reset VSELECT to 0 when 1.8v flag is set. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-01-13power: Rearrange code to guard power command with CONFIG_SPL_BUILD guardTom Rini
In order to discard this code when unused in SPL we need to guard the command with a check for CONFIG_SPL_BUILD and we rearrange the code slightly to make this cleaner. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2018-01-12drivers: pci: imx: fix enumeration logic errorKoen Vandeputte
By default, the subordinate is set equally to the secondary bus (1) when the RC boots, and does not alter afterwards. This means that theoretically, the highest bus reachable downstream is bus 1. Force the PCIe RC subordinate to 0xff, otherwise no downstream devices will be detected behind bus 1 if the booting OS does not allow enumerating a higher busnr than the subordinate value of the primary bus. Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
2018-01-12spi: fsl_qspi: support i.MX6UL/6ULLL/7DPeng Fan
The QSPI module on i.MX7D is modified from i.MX6SX. The module used on i.MX6UL/6ULL is reused from i.MX7D. They share same tx buffer size. The endianness is not set at qspi driver initialization. So if we don't boot from QSPI, we will get wrong endianness when accessing from AHB address directly. Add the compatible entry for 6ul/7d. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-01-12pci: imx: request gpio before usePeng Fan
Before use GPIO, we need to request gpio first. Free gpio after use. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefano Babic <ssbabic@denx.de>
2018-01-12misc: mxc_ocotp: check fuse word before programming on i.MX7ULPPeng Fan
On i.MX7ULP, the fuse words (except bank 0 and 1) only supports to write once, because they use ECC mode. Multiple writes may damage the ECC value and cause a wrong fuse value decoded when reading. This patch adds a checking before the fuse word programming, only can write when the word value is 0. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-01-12mmc: remove hc_wp_grp_size from struct mmc if not neededJean-Jacques Hiblot
hc_wp_grp_size is needed only if hardware partitionning is used. On ARM removing it saves about 30 bytes of code space. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: don't read the size of eMMC enhanced user data area in SPLJean-Jacques Hiblot
This information is only used by the "mmc info" command. On ARM removing this information from SPL saves about 140 of code space. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: compile out erase and write mmc commands if write operations are not ↵Jean-Jacques Hiblot
enabled Also remove erase_grp_size and write_bl_len from struct mmc as they are not used anymore. On ARM, removing them saves about 100 bytes of code space in SPL. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: read ssr only if MMC write support is enabledJean-Jacques Hiblot
The content of ssr is useful only for erase operations. on ARM, removing sd_read_ssr() saves around 300 bytes. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: add a Kconfig option to enable the support for MMC write operationsJean-Jacques Hiblot
This allows using CONFIG_IS_ENABLED(MMC_WRITE) to compile out code needed only if write support is required. The option is added for u-boot and for SPL Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: reworked version lookup in mmc_startup_v4Jean-Jacques Hiblot
Using a table versus a switch() structure saves a bit of space Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: compile out more code if support for UHS and HS200 is not enabledJean-Jacques Hiblot
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: atmel: when sending a data command, use the provided block sizeJean-Jacques Hiblot
struct mmc_data contains the block size to use for the data transfer. Use this information instead of using the default value or the block length information stored in struct mmc. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
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