| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-07-26 | fpga: xilinx: add bitstream flags to driver desc | Oleksandr Suvorov | |
| Store a set of supported bitstream types in xilinx_desc structure. It will be used to determine whether an FPGA image is able to be loaded with a given driver. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Tested-by: Ricardo Salveti <ricardo@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-4-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com> | |||
| 2019-10-08 | arm64: versal: fpga: Add PL bit stream load support | Siva Durga Prasad Paladugu | |
| This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | |||
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