From 2c72ead7387404eba16c556d2f204c52c36c27f9 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Tue, 4 Jun 2019 21:56:29 +0200 Subject: usb: gadget: f_sdp: Allow SPL to load and boot FIT via SDP Add support for loading u-boot FIT images over the USB SDP protocol in the SPL Signed-off-by: Frieder Schrempf [Various build fixes] Signed-off-by: Sjoerd Simons Tested-by: Fabio Estevam Tested-by: Lukasz Majewski --- common/spl/spl_sdp.c | 12 +++++++---- drivers/usb/gadget/f_sdp.c | 53 ++++++++++++++++++++++++++++++++++++++++------ include/sdp.h | 9 +++++++- 3 files changed, 63 insertions(+), 11 deletions(-) diff --git a/common/spl/spl_sdp.c b/common/spl/spl_sdp.c index 807256e908c..51b245b8862 100644 --- a/common/spl/spl_sdp.c +++ b/common/spl/spl_sdp.c @@ -25,10 +25,14 @@ static int spl_sdp_load_image(struct spl_image_info *spl_image, return -ENODEV; } - /* This command typically does not return but jumps to an image */ - sdp_handle(controller_index); - pr_err("SDP ended\n"); + /* + * This command either loads a legacy image, jumps and never returns, + * or it loads a FIT image and returns it to be handled by the SPL + * code. + */ + ret = spl_sdp_handle(controller_index, spl_image); + debug("SDP ended\n"); - return -EINVAL; + return ret; } SPL_LOAD_IMAGE_METHOD("USB SDP", 0, BOOT_DEVICE_BOARD, spl_sdp_load_image); diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c index ae97ab2b497..fab7ce6f97b 100644 --- a/drivers/usb/gadget/f_sdp.c +++ b/drivers/usb/gadget/f_sdp.c @@ -638,7 +638,20 @@ static u32 sdp_jump_imxheader(void *address) return 0; } -static void sdp_handle_in_ep(void) +#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_SPL_LOAD_FIT +static ulong sdp_fit_read(struct spl_load_info *load, ulong sector, + ulong count, void *buf) +{ + debug("%s: sector %lx, count %lx, buf %lx\n", + __func__, sector, count, (ulong)buf); + memcpy(buf, (void *)(load->dev + sector), count); + return count; +} +#endif +#endif + +static void sdp_handle_in_ep(struct spl_image_info *spl_image) { u8 *data = sdp_func->in_req->buf; u32 status; @@ -690,10 +703,25 @@ static void sdp_handle_in_ep(void) /* If imx header fails, try some U-Boot specific headers */ if (status) { #ifdef CONFIG_SPL_BUILD + image_header_t *header = + sdp_ptr(sdp_func->jmp_address); +#ifdef CONFIG_SPL_LOAD_FIT + if (image_get_magic(header) == FDT_MAGIC) { + struct spl_load_info load; + + debug("Found FIT\n"); + load.dev = header; + load.bl_len = 1; + load.read = sdp_fit_read; + spl_load_simple_fit(spl_image, &load, 0, + header); + + return; + } +#endif /* In SPL, allow jumps to U-Boot images */ struct spl_image_info spl_image = {}; - spl_parse_image_header(&spl_image, - (struct image_header *)sdp_func->jmp_address); + spl_parse_image_header(&spl_image, header); jump_to_image_no_args(&spl_image); #else /* In U-Boot, allow jumps to scripts */ @@ -715,19 +743,32 @@ static void sdp_handle_in_ep(void) }; } -void sdp_handle(int controller_index) +#ifndef CONFIG_SPL_BUILD +int sdp_handle(int controller_index) +#else +int spl_sdp_handle(int controller_index, struct spl_image_info *spl_image) +#endif { printf("SDP: handle requests...\n"); while (1) { if (ctrlc()) { puts("\rCTRL+C - Operation aborted.\n"); - return; + return -EINVAL; } +#ifdef CONFIG_SPL_BUILD + if (spl_image->flags & SPL_FIT_FOUND) + return 0; +#endif + WATCHDOG_RESET(); usb_gadget_handle_interrupts(controller_index); - sdp_handle_in_ep(); +#ifdef CONFIG_SPL_BUILD + sdp_handle_in_ep(spl_image); +#else + sdp_handle_in_ep(NULL); +#endif } } diff --git a/include/sdp.h b/include/sdp.h index f6252d027f0..6ac64fb1f31 100644 --- a/include/sdp.h +++ b/include/sdp.h @@ -10,6 +10,13 @@ #define __SDP_H_ int sdp_init(int controller_index); -void sdp_handle(int controller_index); + +#ifdef CONFIG_SPL_BUILD +#include + +int spl_sdp_handle(int controller_index, struct spl_image_info *spl_image); +#else +int sdp_handle(int controller_index); +#endif #endif /* __SDP_H_ */ -- cgit v1.2.3 From 936675c6f447f8333d9dde988917bf8a3d0c6422 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Tue, 25 Jun 2019 14:48:06 +0300 Subject: apalis_imx6: fix set_emmcargs wrapper Fix set_emmcargs wrapper, which prepares proper bootargs for booting from eMMC. Signed-off-by: Igor Opaniuk Reviewed-by: Philippe Schenker --- include/configs/apalis_imx6.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 4b0a3fb26b3..cffb90a6906 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -121,8 +121,8 @@ "imx6q-apalis-cam-eval.dtb fat 0 1" #define EMMC_BOOTCMD \ - "set_emmcargs emmcargs ip=off root=PARTUUID=${uuid} ro,noatime " \ - "rootfstype=ext4 rootwait\0" \ + "set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} " \ + "ro,noatime rootfstype=ext4 rootwait\0" \ "emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \ "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \ "${vidargs}; echo Booting from internal eMMC chip...; " \ -- cgit v1.2.3 From 36adc9a06f64bffc327457418b5b6506ad1d18b4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 26 Apr 2019 09:36:23 -0300 Subject: pico-imx7d: README: Adjust the binary name after DM conversion After the conversion to DM the U-Boot binary is called u-boot-dtb.imx, so fix the README file accordingly. Signed-off-by: Fabio Estevam Acked-by: Joris Offouga --- board/technexion/pico-imx7d/README | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/technexion/pico-imx7d/README b/board/technexion/pico-imx7d/README index f21d8301cbe..6aa0d25af51 100644 --- a/board/technexion/pico-imx7d/README +++ b/board/technexion/pico-imx7d/README @@ -11,7 +11,7 @@ $ make mrproper $ make pico-imx7d_defconfig $ make -This generates the SPL and u-boot.img binaries. +This generates the SPL and u-boot-dtb.img binaries. 1. Loading U-Boot via USB Serial Download Protocol @@ -32,15 +32,15 @@ to use an externally powered USB hub between the board and the host computer. Open a terminal program such as minicom. -Copy SPL and u-boot.img to the imx_usb_loader folder. +Copy SPL and u-boot-dtb.img to the imx_usb_loader folder. Load the SPL binary via USB: $ sudo ./imx_usb SPL -Load the u-boot.img binary via USB: +Load the u-boot-dtb.img binary via USB: -$ sudo ./imx_usb u-boot.img +$ sudo ./imx_usb u-boot-dtb.img Then U-Boot starts and its messages appear in the console program. @@ -55,11 +55,11 @@ Run the DFU agent so we can flash the new images using dfu-util tool: => dfu 0 mmc 0 -Flash SPL and u-boot.img into the eMMC running the following commands on a PC: +Flash SPL and u-boot-dtb.img into the eMMC running the following commands on a PC: $ sudo dfu-util -D SPL -a spl -$ sudo dfu-util -D u-boot.img -a u-boot +$ sudo dfu-util -D u-boot-dtb.img -a u-boot Remove power from the pico board. -- cgit v1.2.3 From 5760069ae8dd4dd36ea44b5a9890bd6e4bf09382 Mon Sep 17 00:00:00 2001 From: Breno Matheus Lima Date: Tue, 7 May 2019 20:19:17 +0000 Subject: mx6sl: hab: Fix pu_irom_mmu_enabled address According to hab.c code we have to notify the ROM code if the MMU is enabled or not. This is achieved by setting the "pu_irom_mmu_enabled" to 0x1. The current address in hab.c code is wrong for i.MX6SL, according to ROM map file the correct address is 0x00901c60. As we are writing in the wrong address the ROM code is not flushing the caches when needed, and the following HAB event is observed in certain scenarios: --------- HAB Event 1 ----------------- event data: 0xdb 0x00 0x14 0x41 0x33 0x18 0xc0 0x00 0xca 0x00 0x0c 0x00 0x01 0xc5 0x00 0x00 0x00 0x00 0x07 0xe4 STS = HAB_FAILURE (0x33) RSN = HAB_INV_SIGNATURE (0x18) CTX = HAB_CTX_COMMAND (0xC0) ENG = HAB_ENG_ANY (0x00) Update MX6SL_PU_IROM_MMU_EN_VAR to address this issue. Reported-by: Frank Zhang Signed-off-by: Breno Lima Reviewed-by: Ye Li Reviewed-by: Fabio Estevam --- arch/arm/mach-imx/hab.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index d42a15e8772..24d16299e8d 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -17,7 +17,7 @@ #define ALIGN_SIZE 0x1000 #define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8 #define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0 -#define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18 +#define MX6SL_PU_IROM_MMU_EN_VAR 0x00901c60 #define IS_HAB_ENABLED_BIT \ (is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \ (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2)) -- cgit v1.2.3 From 6de474340652af22574913aeffadd08913d00702 Mon Sep 17 00:00:00 2001 From: Pierre-Jean Texier Date: Tue, 7 May 2019 23:53:48 +0200 Subject: pico-imx7d: remove unused 'script' variable Since the pico-pi uses the distroboot, this commit remove the 'script' variable (cf boot_scripts). Signed-off-by: Pierre-Jean Texier Reviewed-by: Fabio Estevam --- include/configs/pico-imx7d.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 9a3b3b1e80b..91015402efd 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -79,7 +79,6 @@ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ "image=zImage\0" \ "splashpos=m,m\0" \ "console=ttymxc4\0" \ -- cgit v1.2.3 From 1d255904c306c6fde694a0abb433192ebc01655a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 9 Jun 2019 18:46:41 +0200 Subject: ARM: dts: imx: imx53: Synchronize iMX53 DT with Linux Synchronize iMX53 device tree from Linux next-20190607 3f310e51ceb1 , this is needed to get NFC, UART, USBOTG DT nodes. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Stefano Babic --- arch/arm/dts/imx53.dtsi | 745 ++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 588 insertions(+), 157 deletions(-) diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi index 211ff5f69ef..ed341cfd9d0 100644 --- a/arch/arm/dts/imx53.dtsi +++ b/arch/arm/dts/imx53.dtsi @@ -1,17 +1,8 @@ -/* - * Copyright 2016 Beckhoff Automation - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "skeleton.dtsi" +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2011 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + #include "imx53-pinfunc.h" #include #include @@ -19,8 +10,17 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + aliases { - serial1 = &uart2; + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -36,7 +36,45 @@ mmc1 = &esdhc2; mmc2 = &esdhc3; mmc3 = &esdhc4; - usb1 = &usbh1; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &cspi; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0x0>; + clocks = <&clks IMX5_CLK_ARM>; + clock-latency = <61036>; + voltage-tolerance = <5>; + operating-points = < + /* kHz */ + 166666 850000 + 400000 900000 + 800000 1050000 + 1000000 1200000 + 1200000 1300000 + >; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&ipu_di0>, <&ipu_di1>; + }; + + capture_subsystem { + compatible = "fsl,imx-capture-subsystem"; + ports = <&ipu_csi0>, <&ipu_csi1>; }; tzic: tz-interrupt-controller@fffc000 { @@ -46,13 +84,143 @@ reg = <0x0fffc000 0x4000>; }; + clocks { + ckil { + compatible = "fsl,imx-ckil", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + ckih1 { + compatible = "fsl,imx-ckih1", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <22579200>; + }; + + ckih2 { + compatible = "fsl,imx-ckih2", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + osc { + compatible = "fsl,imx-osc", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + pmu: pmu { + compatible = "arm,cortex-a8-pmu"; + interrupt-parent = <&tzic>; + interrupts = <77>; + }; + + usbphy0: usbphy-0 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; + clock-names = "main_clk"; + #phy-cells = <0>; + status = "okay"; + }; + + usbphy1: usbphy-1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; + clock-names = "main_clk"; + #phy-cells = <0>; + status = "okay"; + }; + soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&tzic>; ranges; - u-boot,dm-pre-reloc; + + sata: sata@10000000 { + compatible = "fsl,imx53-ahci"; + reg = <0x10000000 0x1000>; + interrupts = <28>; + clocks = <&clks IMX5_CLK_SATA_GATE>, + <&clks IMX5_CLK_SATA_REF>, + <&clks IMX5_CLK_AHB>; + clock-names = "sata", "sata_ref", "ahb"; + status = "disabled"; + }; + + ipu: ipu@18000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ipu"; + reg = <0x18000000 0x08000000>; + interrupts = <11 10>; + clocks = <&clks IMX5_CLK_IPU_GATE>, + <&clks IMX5_CLK_IPU_DI0_GATE>, + <&clks IMX5_CLK_IPU_DI1_GATE>; + clock-names = "bus", "di0", "di1"; + resets = <&src 2>; + + ipu_csi0: port@0 { + reg = <0>; + + ipu_csi0_from_parallel_sensor: endpoint { + }; + }; + + ipu_csi1: port@1 { + reg = <1>; + + ipu_csi1_from_parallel_sensor: endpoint { + }; + }; + + ipu_di0: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + ipu_di0_disp0: endpoint@0 { + reg = <0>; + }; + + ipu_di0_lvds0: endpoint@1 { + reg = <1>; + remote-endpoint = <&lvds0_in>; + }; + }; + + ipu_di1: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + ipu_di1_disp1: endpoint@0 { + reg = <0>; + }; + + ipu_di1_lvds1: endpoint@1 { + reg = <1>; + remote-endpoint = <&lvds1_in>; + }; + + ipu_di1_tve: endpoint@2 { + reg = <2>; + remote-endpoint = <&tve_in>; + }; + }; + }; + + gpu: gpu@30000000 { + compatible = "amd,imageon-200.0", "amd,imageon"; + reg = <0x30000000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <12>; + interrupt-names = "kgsl_3d0_irq"; + clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; + clock-names = "core_clk", "mem_iface_clk"; + }; aips@50000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; @@ -92,6 +260,47 @@ status = "disabled"; }; + uart3: serial@5000c000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x5000c000 0x4000>; + interrupts = <33>; + clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, + <&clks IMX5_CLK_UART3_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 42 4 0>, <&sdma 43 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi1: spi@50010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; + reg = <0x50010000 0x4000>; + interrupts = <36>; + clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, + <&clks IMX5_CLK_ECSPI1_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ssi2: ssi@50014000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx53-ssi", + "fsl,imx51-ssi", + "fsl,imx21-ssi"; + reg = <0x50014000 0x4000>; + interrupts = <30>; + clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, + <&clks IMX5_CLK_SSI2_ROOT_GATE>; + clock-names = "ipg", "baud"; + dmas = <&sdma 24 1 0>, + <&sdma 25 1 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + esdhc3: esdhc@50020000 { compatible = "fsl,imx53-esdhc"; reg = <0x50020000 0x4000>; @@ -117,25 +326,18 @@ }; }; - iomuxc: iomuxc@53fa8000 { - compatible = "fsl,imx53-iomuxc"; - reg = <0x53fa8000 0x4000>; - }; - - gpr: iomuxc-gpr@53fa8000 { - compatible = "fsl,imx53-iomuxc-gpr", "syscon"; - reg = <0x53fa8000 0xc>; + aipstz1: bridge@53f00000 { + compatible = "fsl,imx53-aipstz"; + reg = <0x53f00000 0x60>; }; - uart2: serial@53fc0000 { - compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart"; - reg = <0x53fc0000 0x4000>; - interrupts = <32>; - clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, - <&clks IMX5_CLK_UART2_PER_GATE>; - clock-names = "ipg", "per"; - dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; - dma-names = "rx", "tx"; + usbotg: usb@53f80000 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80000 0x0200>; + interrupts = <18>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 0>; + fsl,usbphy = <&usbphy0>; status = "disabled"; }; @@ -144,15 +346,37 @@ reg = <0x53f80200 0x0200>; interrupts = <14>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 1>; + fsl,usbphy = <&usbphy1>; dr_mode = "host"; status = "disabled"; }; - clks: ccm@53fd4000{ - compatible = "fsl,imx53-ccm"; - reg = <0x53fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; - #clock-cells = <1>; + usbh2: usb@53f80400 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80400 0x0200>; + interrupts = <16>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 2>; + dr_mode = "host"; + status = "disabled"; + }; + + usbh3: usb@53f80600 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80600 0x0200>; + interrupts = <17>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 3>; + dr_mode = "host"; + status = "disabled"; + }; + + usbmisc: usbmisc@53f80800 { + #index-cells = <1>; + compatible = "fsl,imx53-usbmisc"; + reg = <0x53f80800 0x200>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; }; gpio1: gpio@53f84000 { @@ -195,6 +419,188 @@ #interrupt-cells = <2>; }; + kpp: kpp@53f94000 { + compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; + reg = <0x53f94000 0x4000>; + interrupts = <60>; + clocks = <&clks IMX5_CLK_DUMMY>; + status = "disabled"; + }; + + wdog1: wdog@53f98000 { + compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; + reg = <0x53f98000 0x4000>; + interrupts = <58>; + clocks = <&clks IMX5_CLK_DUMMY>; + }; + + wdog2: wdog@53f9c000 { + compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; + reg = <0x53f9c000 0x4000>; + interrupts = <59>; + clocks = <&clks IMX5_CLK_DUMMY>; + status = "disabled"; + }; + + gpt: timer@53fa0000 { + compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; + reg = <0x53fa0000 0x4000>; + interrupts = <39>; + clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, + <&clks IMX5_CLK_GPT_HF_GATE>; + clock-names = "ipg", "per"; + }; + + srtc: rtc@53fa4000 { + compatible = "fsl,imx53-rtc"; + reg = <0x53fa4000 0x4000>; + interrupts = <24>; + clocks = <&clks IMX5_CLK_SRTC_GATE>; + }; + + iomuxc: iomuxc@53fa8000 { + compatible = "fsl,imx53-iomuxc"; + reg = <0x53fa8000 0x4000>; + }; + + gpr: iomuxc-gpr@53fa8000 { + compatible = "fsl,imx53-iomuxc-gpr", "syscon"; + reg = <0x53fa8000 0xc>; + }; + + ldb: ldb@53fa8008 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ldb"; + reg = <0x53fa8008 0x4>; + gpr = <&gpr>; + clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, + <&clks IMX5_CLK_LDB_DI1_SEL>, + <&clks IMX5_CLK_IPU_DI0_SEL>, + <&clks IMX5_CLK_IPU_DI1_SEL>, + <&clks IMX5_CLK_LDB_DI0_GATE>, + <&clks IMX5_CLK_LDB_DI1_GATE>; + clock-names = "di0_pll", "di1_pll", + "di0_sel", "di1_sel", + "di0", "di1"; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + status = "disabled"; + + port@0 { + reg = <0>; + + lvds0_in: endpoint { + remote-endpoint = <&ipu_di0_lvds0>; + }; + }; + + port@2 { + reg = <2>; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + status = "disabled"; + + port@1 { + reg = <1>; + + lvds1_in: endpoint { + remote-endpoint = <&ipu_di1_lvds1>; + }; + }; + + port@2 { + reg = <2>; + }; + }; + }; + + pwm1: pwm@53fb4000 { + #pwm-cells = <2>; + compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; + reg = <0x53fb4000 0x4000>; + clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, + <&clks IMX5_CLK_PWM1_HF_GATE>; + clock-names = "ipg", "per"; + interrupts = <61>; + }; + + pwm2: pwm@53fb8000 { + #pwm-cells = <2>; + compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; + reg = <0x53fb8000 0x4000>; + clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, + <&clks IMX5_CLK_PWM2_HF_GATE>; + clock-names = "ipg", "per"; + interrupts = <94>; + }; + + uart1: serial@53fbc000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53fbc000 0x4000>; + interrupts = <31>; + clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, + <&clks IMX5_CLK_UART1_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 18 4 0>, <&sdma 19 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@53fc0000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53fc0000 0x4000>; + interrupts = <32>; + clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, + <&clks IMX5_CLK_UART2_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + can1: can@53fc8000 { + compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; + reg = <0x53fc8000 0x4000>; + interrupts = <82>; + clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, + <&clks IMX5_CLK_CAN1_SERIAL_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can2: can@53fcc000 { + compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; + reg = <0x53fcc000 0x4000>; + interrupts = <83>; + clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, + <&clks IMX5_CLK_CAN2_SERIAL_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + src: src@53fd0000 { + compatible = "fsl,imx53-src", "fsl,imx51-src"; + reg = <0x53fd0000 0x4000>; + #reset-cells = <1>; + }; + + clks: ccm@53fd4000{ + compatible = "fsl,imx53-ccm"; + reg = <0x53fd4000 0x4000>; + interrupts = <0 71 0x04 0 72 0x04>; + #clock-cells = <1>; + }; + gpio5: gpio@53fdc000 { compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; reg = <0x53fdc000 0x4000>; @@ -234,6 +640,18 @@ clocks = <&clks IMX5_CLK_I2C3_GATE>; status = "disabled"; }; + + uart4: serial@53ff0000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53ff0000 0x4000>; + interrupts = <13>; + clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, + <&clks IMX5_CLK_UART4_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 2 4 0>, <&sdma 3 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; }; aips@60000000 { /* AIPS2 */ @@ -243,25 +661,74 @@ reg = <0x60000000 0x10000000>; ranges; + aipstz2: bridge@63f00000 { + compatible = "fsl,imx53-aipstz"; + reg = <0x63f00000 0x60>; + }; + + iim: iim@63f98000 { + compatible = "fsl,imx53-iim", "fsl,imx27-iim"; + reg = <0x63f98000 0x4000>; + interrupts = <69>; + clocks = <&clks IMX5_CLK_IIM_GATE>; + }; + + uart5: serial@63f90000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x63f90000 0x4000>; + interrupts = <86>; + clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, + <&clks IMX5_CLK_UART5_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 16 4 0>, <&sdma 17 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + tigerp: tigerp@63fa0000 { + compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp"; + reg = <0x63fa0000 0x28>; + }; + + owire: owire@63fa4000 { + compatible = "fsl,imx53-owire", "fsl,imx21-owire"; + reg = <0x63fa4000 0x4000>; + clocks = <&clks IMX5_CLK_OWIRE_GATE>; + status = "disabled"; + }; + + ecspi2: spi@63fac000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; + reg = <0x63fac000 0x4000>; + interrupts = <37>; + clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, + <&clks IMX5_CLK_ECSPI2_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + sdma: sdma@63fb0000 { compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; reg = <0x63fb0000 0x4000>; interrupts = <6>; clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_SDMA_GATE>; + <&clks IMX5_CLK_AHB>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; }; - fec: ethernet@63fec000 { - compatible = "fsl,imx53-fec", "fsl,imx25-fec"; - reg = <0x63fec000 0x4000>; - interrupts = <87>; - clocks = <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>; - clock-names = "ipg", "ahb", "ptp"; + cspi: spi@63fc0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; + reg = <0x63fc0000 0x4000>; + interrupts = <38>; + clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, + <&clks IMX5_CLK_CSPI_IPG_GATE>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -284,66 +751,65 @@ clocks = <&clks IMX5_CLK_I2C1_GATE>; status = "disabled"; }; - }; - - ipu: ipu@18000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ipu"; - reg = <0x18000000 0x08000000>; - interrupts = <11 10>; - clocks = <&clks IMX5_CLK_IPU_GATE>, - <&clks IMX5_CLK_IPU_DI0_GATE>, - <&clks IMX5_CLK_IPU_DI1_GATE>; - clock-names = "bus", "di0", "di1"; - resets = <&src 2>; - u-boot,dm-pre-reloc; - ipu_csi0: port@0 { - reg = <0>; + ssi1: ssi@63fcc000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", + "fsl,imx21-ssi"; + reg = <0x63fcc000 0x4000>; + interrupts = <29>; + clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, + <&clks IMX5_CLK_SSI1_ROOT_GATE>; + clock-names = "ipg", "baud"; + dmas = <&sdma 28 0 0>, + <&sdma 29 0 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; }; - ipu_csi1: port@1 { - reg = <1>; + audmux: audmux@63fd0000 { + compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; + reg = <0x63fd0000 0x4000>; + status = "disabled"; }; - ipu_di0: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - ipu_di0_disp0: endpoint@0 { - reg = <0>; - }; - - ipu_di0_lvds0: endpoint@1 { - reg = <1>; - remote-endpoint = <&lvds0_in>; - }; + nfc: nand@63fdb000 { + compatible = "fsl,imx53-nand"; + reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; + interrupts = <8>; + clocks = <&clks IMX5_CLK_NFC_GATE>; + status = "disabled"; }; - ipu_di1: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - ipu_di1_disp1: endpoint@0 { - reg = <0>; - }; - - ipu_di1_lvds1: endpoint@1 { - reg = <1>; - remote-endpoint = <&lvds1_in>; - }; + ssi3: ssi@63fe8000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", + "fsl,imx21-ssi"; + reg = <0x63fe8000 0x4000>; + interrupts = <96>; + clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, + <&clks IMX5_CLK_SSI3_ROOT_GATE>; + clock-names = "ipg", "baud"; + dmas = <&sdma 46 0 0>, + <&sdma 47 0 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; - ipu_di1_tve: endpoint@2 { - reg = <2>; - remote-endpoint = <&tve_in>; - }; + fec: ethernet@63fec000 { + compatible = "fsl,imx53-fec", "fsl,imx25-fec"; + reg = <0x63fec000 0x4000>; + interrupts = <87>; + clocks = <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>; + clock-names = "ipg", "ahb", "ptp"; + status = "disabled"; }; - }; - tve: tve@63ff0000 { + tve: tve@63ff0000 { compatible = "fsl,imx53-tve"; reg = <0x63ff0000 0x1000>; interrupts = <92>; @@ -357,68 +823,33 @@ remote-endpoint = <&ipu_di1_tve>; }; }; - }; - - src: src@53fd0000 { - compatible = "fsl,imx53-src", "fsl,imx51-src"; - reg = <0x53fd0000 0x4000>; - #reset-cells = <1>; - }; - - ldb: ldb@53fa8008 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ldb"; - reg = <0x53fa8008 0x4>; - gpr = <&gpr>; - clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, - <&clks IMX5_CLK_LDB_DI1_SEL>, - <&clks IMX5_CLK_IPU_DI0_SEL>, - <&clks IMX5_CLK_IPU_DI1_SEL>, - <&clks IMX5_CLK_LDB_DI0_GATE>, - <&clks IMX5_CLK_LDB_DI1_GATE>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", - "di0", "di1"; - status = "disabled"; - - lvds-channel@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - - lvds0_in: endpoint { - remote-endpoint = <&ipu_di0_lvds0>; - }; - }; - - port@2 { - reg = <2>; - }; - }; - - lvds-channel@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - status = "disabled"; + }; - port@1 { - reg = <1>; + vpu: vpu@63ff4000 { + compatible = "fsl,imx53-vpu", "cnm,coda7541"; + reg = <0x63ff4000 0x1000>; + interrupts = <9>; + clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, + <&clks IMX5_CLK_VPU_GATE>; + clock-names = "per", "ahb"; + resets = <&src 1>; + iram = <&ocram>; + }; - lvds1_in: endpoint { - remote-endpoint = <&ipu_di1_lvds1>; - }; - }; + sahara: crypto@63ff8000 { + compatible = "fsl,imx53-sahara"; + reg = <0x63ff8000 0x4000>; + interrupts = <19 20>; + clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, + <&clks IMX5_CLK_SAHARA_IPG_GATE>; + clock-names = "ipg", "ahb"; + }; + }; - port@2 { - reg = <2>; - }; - }; + ocram: sram@f8000000 { + compatible = "mmio-sram"; + reg = <0xf8000000 0x20000>; + clocks = <&clks IMX5_CLK_OCRAM>; }; }; }; -- cgit v1.2.3 From 26bb95f0561cd34837c1ea588eac8537f2b91912 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 9 Jun 2019 18:46:42 +0200 Subject: ARM: dts: imx: m53menlo: Import M53Menlo DT from Linux Import iMX53 M53Menlo device tree from Linux next-20190607 3f310e51ceb1 . Enable DT control in full U-Boot . Add U-Boot extras into separate DTSi, the GPIO controllers need to be inited early, otherwise m53_set_clock() won't be able to detect the correct CPU clock frequency by reading the GPIO. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Stefano Babic --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx53-m53.dtsi | 132 ++++++++++++++ arch/arm/dts/imx53-m53menlo-u-boot.dtsi | 42 +++++ arch/arm/dts/imx53-m53menlo.dts | 312 ++++++++++++++++++++++++++++++++ configs/m53menlo_defconfig | 3 +- 5 files changed, 490 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/imx53-m53.dtsi create mode 100644 arch/arm/dts/imx53-m53menlo-u-boot.dtsi create mode 100644 arch/arm/dts/imx53-m53menlo.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 528fb909d5b..2271d787297 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -535,7 +535,8 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ vf610-bk4r1.dtb dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \ - imx53-kp.dtb + imx53-kp.dtb \ + imx53-m53menlo.dtb dtb-$(CONFIG_MX6Q) += \ imx6-apalis.dtb \ diff --git a/arch/arm/dts/imx53-m53.dtsi b/arch/arm/dts/imx53-m53.dtsi new file mode 100644 index 00000000000..fe5e0d308e9 --- /dev/null +++ b/arch/arm/dts/imx53-m53.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2014 Marek Vasut + */ + +#include "imx53.dtsi" + +/ { + model = "Aries/DENX M53"; + compatible = "aries,imx53-m53", "denx,imx53-m53", "fsl,imx53"; + + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0x20000000>, + <0xb0000000 0x20000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p2v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P2V"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; + + reg_backlight: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "lcd-supply"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <400000>; + status = "okay"; + + touchscreen@41 { + compatible = "st,stmpe610"; + reg = <0x41>; + id = <0>; + blocks = <0x5>; + interrupts = <6 0x0>; + interrupt-parent = <&gpio7>; + irq-trigger = <0x1>; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + st,ave-ctrl = <3>; + st,touch-det-delay = <3>; + st,settling = <4>; + st,fraction-z = <7>; + st,i-drive = <1>; + }; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + pagesize = <32>; + }; + + rtc: rtc@68 { + compatible = "st,m41t62"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-m53evk { + pinctrl_hog: hoggrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 + MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 + MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000 + MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000 + >; + }; + + pinctrl_nand: nandgrp { + fsl,pins = < + MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 + MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 + MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 + MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 + MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 + MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 + MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 + MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 + MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 + MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 + MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 + MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 + MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 + MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 + MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 + >; + }; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + status = "okay"; +}; diff --git a/arch/arm/dts/imx53-m53menlo-u-boot.dtsi b/arch/arm/dts/imx53-m53menlo-u-boot.dtsi new file mode 100644 index 00000000000..329fa3b5e27 --- /dev/null +++ b/arch/arm/dts/imx53-m53menlo-u-boot.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Marek Vasut + */ + +/ { + soc { + u-boot,dm-pre-reloc; + + aips@50000000 { + u-boot,dm-pre-reloc; + }; + }; +}; + +&gpio1 { + u-boot,dm-pre-reloc; +}; + +&gpio2 { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + +&gpio4 { + u-boot,dm-pre-reloc; +}; + +&gpio5 { + u-boot,dm-pre-reloc; +}; + +&gpio6 { + u-boot,dm-pre-reloc; +}; + +&gpio7 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx53-m53menlo.dts b/arch/arm/dts/imx53-m53menlo.dts new file mode 100644 index 00000000000..a6805eca9d0 --- /dev/null +++ b/arch/arm/dts/imx53-m53menlo.dts @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Marek Vasut + */ + +/dts-v1/; +#include "imx53-m53.dtsi" +#include "imx53-m53menlo-u-boot.dtsi" + +/ { + model = "MENLO M53 EMBEDDED DEVICE"; + compatible = "menlo,m53menlo", "fsl,imx53"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + user1 { + label = "TestLed601"; + gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + user2 { + label = "TestLed602"; + gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + eth { + label = "EthLedYe"; + gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + }; + + panel { + compatible = "edt,etm070080dh6"; + enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + reg_usbh1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX5_CLK_CKO1_SEL>, + <&clks IMX5_CLK_CKO1_PODF>, + <&clks IMX5_CLK_CKO1>; + assigned-clock-parents = <&clks IMX5_CLK_AHB>; + assigned-clock-rates = <133333334>, <33333334>, <33333334>; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ft5x06>; + interrupt-parent = <&gpio6>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + dac@60 { + compatible = "microchip,mcp4725"; + reg = <0x60>; + }; +}; + +&i2c2 { + touchscreen@41 { + status = "disabled"; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-m53evk { + hoggrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 + MX53_PAD_EIM_EB3__GPIO2_31 0x1d5 + MX53_PAD_PATA_DA_0__GPIO7_6 0x1d5 + MX53_PAD_GPIO_19__CCM_CLKO 0x1d5 + MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x1d5 + MX53_PAD_CSI0_DAT4__GPIO5_22 0x1d5 + MX53_PAD_CSI0_DAT5__GPIO5_23 0x1d5 + MX53_PAD_CSI0_DAT6__GPIO5_24 0x1d5 + MX53_PAD_CSI0_DAT7__GPIO5_25 0x1d5 + MX53_PAD_CSI0_DAT8__GPIO5_26 0x1d5 + MX53_PAD_CSI0_DAT9__GPIO5_27 0x1d5 + MX53_PAD_CSI0_DAT10__GPIO5_28 0x1d5 + MX53_PAD_CSI0_DAT11__GPIO5_29 0x1d5 + MX53_PAD_CSI0_DAT14__GPIO6_0 0x1d5 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX53_PAD_CSI0_DAT15__GPIO6_1 0x1d5 + MX53_PAD_CSI0_DAT16__GPIO6_2 0x1d5 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX53_PAD_GPIO_7__CAN1_TXCAN 0x1c4 + MX53_PAD_GPIO_8__CAN1_RXCAN 0x1c4 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1c4 + MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4 + >; + }; + + pinctrl_display_gpio: display-gpiogrp { + fsl,pins = < + MX53_PAD_CSI0_DAT12__GPIO5_30 0x1d5 /* Reset */ + MX53_PAD_CSI0_DAT13__GPIO5_31 0x1d5 /* Interrupt */ + >; + }; + + pinctrl_edt_ft5x06: edt-ft5x06grp { + fsl,pins = < + MX53_PAD_PATA_DATA9__GPIO2_9 0x1d5 /* Reset */ + MX53_PAD_CSI0_DAT19__GPIO6_5 0x1d5 /* Interrupt */ + MX53_PAD_PATA_DATA10__GPIO2_10 0x1d5 /* Wake */ + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x4 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 + MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4 + MX53_PAD_GPIO_5__I2C3_SCL 0x400001e4 + >; + }; + + pinctrl_lvds0: lvds0grp { + /* LVDS pins only have pin mux configuration */ + fsl,pins = < + MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 + MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 + MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 + MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 + MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 + >; + }; + + pinctrl_usb: usbgrp { + fsl,pins = < + MX53_PAD_GPIO_2__GPIO1_2 0x1d5 + MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1d5 + >; + }; + }; +}; + +&ldb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0>; + status = "okay"; + + lvds0: lvds-channel@0 { + reg = <0>; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + port@2 { + reg = <2>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb>; + vbus-supply = <®_usbh1_vbus>; + phy_type = "utmi"; + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index 0e5fa01fde2..ef57fbea917 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -48,6 +48,8 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1m(u-boot),512k(env1),512k(env2),-(ubi)" CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx53-m53menlo" CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 @@ -71,4 +73,3 @@ CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_IMX_WATCHDOG=y CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y -- cgit v1.2.3 From 9b352ae1ae9fb53ce94a05cc06d300227f4eacc4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 9 Jun 2019 18:46:43 +0200 Subject: ARM: imx: m53menlo: Enable DM GPIO Enable DM GPIO support on iMX53 M53Menlo and fix up board code where applicable. Enable MALLOC_F to let the GPIO controllers bind early on. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Stefano Babic --- board/menlo/m53menlo/m53menlo.c | 8 ++++++++ configs/m53menlo_defconfig | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c index 6bdd6d5b234..a46041868ca 100644 --- a/board/menlo/m53menlo/m53menlo.c +++ b/board/menlo/m53menlo/m53menlo.c @@ -88,6 +88,7 @@ int board_ehci_hcd_init(int port) imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4, PAD_CTL_PKE | PAD_CTL_DSE_HIGH)); + gpio_request(IMX_GPIO_NR(1, 4), "USB_OTG_PWRON"); gpio_direction_output(IMX_GPIO_NR(1, 4), 0); /* USB OTG Over Current */ @@ -97,6 +98,7 @@ int board_ehci_hcd_init(int port) imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2, PAD_CTL_PKE | PAD_CTL_DSE_HIGH)); + gpio_request(IMX_GPIO_NR(1, 2), "USB_HOST_PWRON"); gpio_direction_output(IMX_GPIO_NR(1, 2), 0); /* USB Host Over Current */ @@ -215,6 +217,8 @@ static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk) static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev) { + gpio_request(IMX_GPIO_NR(6, 0), "LCD"); + /* For ETM0430G0DH6 model, this must be enabled before the clock. */ gpio_direction_output(IMX_GPIO_NR(6, 0), 1); @@ -227,6 +231,8 @@ static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev) static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev) { + gpio_request(IMX_GPIO_NR(6, 0), "LCD"); + /* * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 . @@ -424,6 +430,8 @@ static void m53_set_clock(void) const u32 dramclk = 400; u32 cpuclk; + gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK"); + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0, PAD_CTL_DSE_HIGH | PAD_CTL_PKE)); gpio_direction_input(IMX_GPIO_NR(4, 0)); diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index ef57fbea917..3b527b9fdcb 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x71000000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_TARGET_M53MENLO=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 @@ -29,6 +30,7 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND_TRIMFFS=y @@ -51,9 +53,11 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx53-m53menlo" CONFIG_ENV_IS_IN_NAND=y +CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041 +CONFIG_DM_GPIO=y CONFIG_FSL_ESDHC=y CONFIG_NAND=y CONFIG_NAND_MXC=y -- cgit v1.2.3 From 86aa7103b61edf02baad492fa601cd6a3db0e77e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 9 Jun 2019 18:46:44 +0200 Subject: ARM: imx: m53menlo: Convert MMC, USB and block to DM Enable DM block and DM MMC and DM USB support on iMX53 M53Menlo . Convert board code to match the DM support. This also enables DM pincontrol to configure the SDHI pins. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Stefano Babic --- board/menlo/m53menlo/m53menlo.c | 66 ----------------------------------------- configs/m53menlo_defconfig | 9 ++++++ 2 files changed, 9 insertions(+), 66 deletions(-) diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c index a46041868ca..340c750a819 100644 --- a/board/menlo/m53menlo/m53menlo.c +++ b/board/menlo/m53menlo/m53menlo.c @@ -80,35 +80,6 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); } -#ifdef CONFIG_USB_EHCI_MX5 -int board_ehci_hcd_init(int port) -{ - if (port == 0) { - /* USB OTG PWRON */ - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4, - PAD_CTL_PKE | - PAD_CTL_DSE_HIGH)); - gpio_request(IMX_GPIO_NR(1, 4), "USB_OTG_PWRON"); - gpio_direction_output(IMX_GPIO_NR(1, 4), 0); - - /* USB OTG Over Current */ - imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13); - } else if (port == 1) { - /* USB Host PWRON */ - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2, - PAD_CTL_PKE | - PAD_CTL_DSE_HIGH)); - gpio_request(IMX_GPIO_NR(1, 2), "USB_HOST_PWRON"); - gpio_direction_output(IMX_GPIO_NR(1, 2), 0); - - /* USB Host Over Current */ - imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC); - } - - return 0; -} -#endif - static void setup_iomux_fec(void) { static const iomux_v3_cfg_t fec_pads[] = { @@ -152,43 +123,6 @@ static void setup_iomux_fec(void) imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); } -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg esdhc_cfg = { - MMC_SDHC1_BASE_ADDR, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1); - gpio_direction_input(IMX_GPIO_NR(1, 1)); - - return !gpio_get_value(IMX_GPIO_NR(1, 1)); -} - -#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP) -#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_DSE_HIGH) - -int board_mmc_init(bd_t *bis) -{ - static const iomux_v3_cfg_t sd1_pads[] = { - NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), - }; - - esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); - - return fsl_esdhc_initialize(bis, &esdhc_cfg); -} -#endif - #ifdef CONFIG_VIDEO static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk) { diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index 3b527b9fdcb..c9a8b0dff91 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -28,12 +28,14 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND_TRIMFFS=y +# CONFIG_CMD_PINMUX is not set CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -58,14 +60,21 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041 CONFIG_DM_GPIO=y +CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_NAND=y CONFIG_NAND_MXC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX5=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_RTC_M41T62=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_MX5=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y -- cgit v1.2.3 From f0be8ff45fb89d02ae4aa5b87076edd034cad9fc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 9 Jun 2019 18:46:46 +0200 Subject: ARM: imx: m53menlo: Convert to DM VIDEO Enable DM Video support on iMX53 M53Menlo and fix minor details to restore previous behavior of the system. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Stefano Babic --- board/menlo/m53menlo/m53menlo.c | 48 +++++++++++++++++++++++++++++++++++++++-- configs/m53menlo_defconfig | 7 +++--- include/configs/m53menlo.h | 4 ++-- 3 files changed, 51 insertions(+), 8 deletions(-) diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c index 340c750a819..31ba44e452d 100644 --- a/board/menlo/m53menlo/m53menlo.c +++ b/board/menlo/m53menlo/m53menlo.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -28,6 +29,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -123,7 +125,6 @@ static void setup_iomux_fec(void) imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); } -#ifdef CONFIG_VIDEO static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk) { static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; @@ -270,7 +271,6 @@ struct display_info_t const displays[] = { }; size_t display_count = ARRAY_SIZE(displays); -#endif #ifdef CONFIG_SPLASH_SCREEN static struct splash_location default_splash_locations[] = { @@ -289,6 +289,50 @@ int splash_screen_prepare(void) } #endif +int board_late_init(void) +{ +#if defined(CONFIG_VIDEO_IPUV3) + struct udevice *dev; + int xpos, ypos, ret; + char *s; + void *dst; + ulong addr, len; + + splash_get_pos(&xpos, &ypos); + + s = env_get("splashimage"); + if (!s) + return 0; + + addr = simple_strtoul(s, NULL, 16); + dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE); + if (!dst) + return -ENOMEM; + + ret = splash_screen_prepare(); + if (ret < 0) + return ret; + + len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE; + ret = gunzip(dst + 2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE - 2, + (uchar *)addr, &len); + if (ret) { + printf("Error: no valid bmp or bmp.gz image at %lx\n", addr); + free(dst); + return ret; + } + + ret = uclass_get_device(UCLASS_VIDEO, 0, &dev); + if (ret) + return ret; + + ret = video_bmp_display(dev, (ulong)dst + 2, xpos, ypos, true); + if (ret) + return ret; +#endif + return 0; +} + #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index c9a8b0dff91..5a1fbf52985 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -18,9 +18,8 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/menlo/m53menlo/imximage.cfg" CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttymxc0,115200" -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_VERSION_VARIABLE=y +CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_TEXT_BASE=0x70008000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_NAND_SUPPORT=y @@ -81,8 +80,8 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set CONFIG_IMX_WATCHDOG=y CONFIG_FAT_WRITE=y diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index fc0b1f480ce..7b68c1c0a1e 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -136,7 +136,6 @@ /* * LCD */ -#ifdef CONFIG_VIDEO #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_VIDEO_BMP_GZIP #define CONFIG_SPLASH_SCREEN @@ -145,7 +144,6 @@ #define CONFIG_BMP_16BPP #define CONFIG_VIDEO_LOGO #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) -#endif /* LVDS display */ #define CONFIG_SYS_LDB_CLOCK 33260000 @@ -205,6 +203,8 @@ "splashfile=boot/usplash.bmp.gz\0" \ "splashimage=0x88000000\0" \ "splashpos=m,m\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" \ "addcons=" \ "setenv bootargs ${bootargs} " \ "console=${consdev},${baudrate}\0" \ -- cgit v1.2.3 From 0ac662da35e48b859b5d43e0c86f233f25730ee5 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Mon, 24 Jun 2019 11:39:14 +0300 Subject: apalis_imx6: increase phy autoneg timeout Default value (4000ms) of PHY_ANEG_TIMEOUT for Micrel KSZ9031 contoller isn't sufficient to finish auto-negotiation, which sometimes leads to timeout errors: Apalis iMX6 # dhcp FEC Waiting for PHY auto negotiation to complete......... TIMEOUT ! Increase the auto-negotiation time-out to 15000ms. Signed-off-by: Igor Opaniuk Reviewed-by: Philippe Schenker --- include/configs/apalis_imx6.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index cffb90a6906..db37fa7b731 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -58,6 +58,7 @@ #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_ETHPRIME "FEC" +#define PHY_ANEG_TIMEOUT 15000 /* PHY needs longer aneg time */ #define CONFIG_FEC_MXC_PHYADDR 6 #define CONFIG_TFTP_TSIZE -- cgit v1.2.3