From 17fe55fd6fe9d32270380f574b33ff0bc15bb47e Mon Sep 17 00:00:00 2001 From: Peter Hoyes Date: Thu, 11 Nov 2021 09:26:00 +0000 Subject: vexpress64: Refactor header file to make it easier to add new FVPs Rename from vexpress_aemv8a.h -> vepxress_aemv8.h as new FVPs may not be v8-A. No change in behavior. This is towards future work to enable support for the FVP_BaseR. Signed-off-by: Peter Hoyes Reviewed-by: Andre Przywara --- board/armltd/vexpress64/Kconfig | 2 +- doc/README.semihosting | 2 +- include/configs/vexpress_aemv8.h | 214 ++++++++++++++++++++++++++++++++++++++ include/configs/vexpress_aemv8a.h | 213 ------------------------------------- 4 files changed, 216 insertions(+), 215 deletions(-) create mode 100644 include/configs/vexpress_aemv8.h delete mode 100644 include/configs/vexpress_aemv8a.h diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index 1d13f542e67..4aab3f092ec 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "armltd" config SYS_CONFIG_NAME - default "vexpress_aemv8a" + default "vexpress_aemv8" config JUNO_DTB_PART string "NOR flash partition holding DTB" diff --git a/doc/README.semihosting b/doc/README.semihosting index c019999bedd..f382d0131eb 100644 --- a/doc/README.semihosting +++ b/doc/README.semihosting @@ -25,7 +25,7 @@ or turning on CONFIG_BASE_FVP for the more full featured model. Rather than create a new armv8 board similar to armltd/vexpress64, add semihosting calls to the existing one, enabled with CONFIG_SEMIHOSTING and CONFIG_BASE_FVP both set. Also reuse the existing board config file -vexpress_aemv8a.h but differentiate the two models by the presence or +vexpress_aemv8.h but differentiate the two models by the presence or absence of CONFIG_BASE_FVP. This change is tested and works on both the Foundation and Base fastmodel simulators. diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h new file mode 100644 index 00000000000..52fc15d5fc8 --- /dev/null +++ b/include/configs/vexpress_aemv8.h @@ -0,0 +1,214 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for Versatile Express. Parts were derived from other ARM + * configurations. + */ + +#ifndef __VEXPRESS_AEMV8_H +#define __VEXPRESS_AEMV8_H + +#define CONFIG_REMAKE_ELF + +/* Link Definitions */ +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) +#else +/* ATF loads u-boot here for BASE_FVP model */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) +#endif + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +/* CS register bases for the original memory map. */ +#define V2M_BASE 0x80000000 +#define V2M_PA_BASE 0x00000000 + +#define V2M_PA_CS0 (V2M_PA_BASE + 0x00000000) +#define V2M_PA_CS1 (V2M_PA_BASE + 0x14000000) +#define V2M_PA_CS2 (V2M_PA_BASE + 0x18000000) +#define V2M_PA_CS3 (V2M_PA_BASE + 0x1c000000) +#define V2M_PA_CS4 (V2M_PA_BASE + 0x0c000000) +#define V2M_PA_CS5 (V2M_PA_BASE + 0x10000000) + +#define V2M_PERIPH_OFFSET(x) (x << 16) +#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) +#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) +#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3)) + +/* Common peripherals relative to CS7. */ +#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) +#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) +#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) +#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) + +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +#define V2M_UART0 0x7ff80000 +#define V2M_UART1 0x7ff70000 +#else /* Not Juno */ +#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) +#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) +#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) +#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) +#endif + +#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) + +#define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17)) +#define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18)) + +#define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22)) +#define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23)) + +#define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26)) + +#define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31)) + +/* System register offsets. */ +#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) +#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) +#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 24000000 /* 24MHz */ + +/* Generic Interrupt Controller Definitions */ +#ifdef CONFIG_GICV3 +#define GICD_BASE (V2M_PA_BASE + 0x2f000000) +#define GICR_BASE (V2M_PA_BASE + 0x2f100000) +#else + +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +#define GICD_BASE (0x2C010000) +#define GICC_BASE (0x2C02f000) +#else +#define GICD_BASE (V2M_PA_BASE + 0x2f000000) +#define GICC_BASE (V2M_PA_BASE + 0x2c000000) +#endif +#endif /* !CONFIG_GICV3 */ + +#ifndef CONFIG_TARGET_VEXPRESS64_JUNO +/* The Vexpress64 simulators use SMSC91C111 */ +#define CONFIG_SMC91111 1 +#define CONFIG_SMC91111_BASE (V2M_PA_BASE + 0x01A000000) +#endif + +/* PL011 Serial Configuration */ +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +#define CONFIG_PL011_CLOCK 7372800 +#else +#define CONFIG_PL011_CLOCK 24000000 +#endif + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* Miscellaneous configurable options */ + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ +/* Top 16MB reserved for secure world use */ +#define DRAM_SEC_SIZE 0x01000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +#define PHYS_SDRAM_2 (0x880000000) +#define PHYS_SDRAM_2_SIZE 0x180000000 +#elif CONFIG_NR_DRAM_BANKS == 2 +#define PHYS_SDRAM_2 (0x880000000) +#define PHYS_SDRAM_2_SIZE 0x80000000 +#endif + +/* Enable memtest */ + +/* Initial environment variables */ +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +/* Copy the kernel and FDT to DRAM memory and boot */ +#define BOOTENV_DEV_AFS(devtypeu, devtypel, instance) \ + "bootcmd_afs=" \ + "afs load ${kernel_name} ${kernel_addr_r} ;"\ + "if test $? -eq 1; then "\ + " echo Loading ${kernel_alt_name} instead of ${kernel_name}; "\ + " afs load ${kernel_alt_name} ${kernel_addr_r};"\ + "fi ; "\ + "afs load ${fdtfile} ${fdt_addr_r} ;"\ + "if test $? -eq 1; then "\ + " echo Loading ${fdt_alt_name} instead of ${fdtfile}; "\ + " afs load ${fdt_alt_name} ${fdt_addr_r}; "\ + "fi ; "\ + "fdt addr ${fdt_addr_r}; fdt resize; " \ + "if afs load ${ramdisk_name} ${ramdisk_addr_r} ; "\ + "then "\ + " setenv ramdisk_param ${ramdisk_addr_r}; "\ + "else "\ + " setenv ramdisk_param -; "\ + "fi ; " \ + "booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}\0" +#define BOOTENV_DEV_NAME_AFS(devtypeu, devtypel, instance) "afs " + +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(SATA, sata, 0) \ + func(SATA, sata, 1) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) \ + func(AFS, afs, na) + +#include + +/* + * Defines where the kernel and FDT exist in NOR flash and where it will + * be copied into DRAM + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_name=norkern\0" \ + "kernel_alt_name=Image\0" \ + "kernel_addr_r=0x80080000\0" \ + "ramdisk_name=ramdisk.img\0" \ + "ramdisk_addr_r=0x88000000\0" \ + "fdtfile=board.dtb\0" \ + "fdt_alt_name=juno\0" \ + "fdt_addr_r=0x80000000\0" \ + BOOTENV + +#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_name=Image\0" \ + "kernel_addr=0x80080000\0" \ + "initrd_name=ramdisk.img\0" \ + "initrd_addr=0x88000000\0" \ + "fdtfile=devtree.dtb\0" \ + "fdt_addr=0x83000000\0" \ + "boot_name=boot.img\0" \ + "boot_addr=0x8007f800\0" +#endif + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +#define CONFIG_SYS_FLASH_BASE 0x08000000 +/* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */ +#define CONFIG_SYS_MAX_FLASH_SECT 259 +/* Store environment at top of flash in the same location as blank.img */ +/* in the Juno firmware. */ +#else +#define CONFIG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000) +/* 256 x 256KiB sectors */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 +/* Store environment at top of flash */ +#endif + +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 +#endif + +#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ +#define FLASH_MAX_SECTOR_SIZE 0x00040000 + +#endif /* __VEXPRESS_AEMV8_H */ diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h deleted file mode 100644 index 44c746f6f2b..00000000000 --- a/include/configs/vexpress_aemv8a.h +++ /dev/null @@ -1,213 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Versatile Express. Parts were derived from other ARM - * configurations. - */ - -#ifndef __VEXPRESS_AEMV8A_H -#define __VEXPRESS_AEMV8A_H - -#define CONFIG_REMAKE_ELF - -/* Link Definitions */ -#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP -/* ATF loads u-boot here for BASE_FVP model */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) -#elif CONFIG_TARGET_VEXPRESS64_JUNO -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -#endif - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* CS register bases for the original memory map. */ -#define V2M_PA_CS0 0x00000000 -#define V2M_PA_CS1 0x14000000 -#define V2M_PA_CS2 0x18000000 -#define V2M_PA_CS3 0x1c000000 -#define V2M_PA_CS4 0x0c000000 -#define V2M_PA_CS5 0x10000000 - -#define V2M_PERIPH_OFFSET(x) (x << 16) -#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) -#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) -#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3)) - -#define V2M_BASE 0x80000000 - -/* Common peripherals relative to CS7. */ -#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) -#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) -#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) -#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) - -#ifdef CONFIG_TARGET_VEXPRESS64_JUNO -#define V2M_UART0 0x7ff80000 -#define V2M_UART1 0x7ff70000 -#else /* Not Juno */ -#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) -#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) -#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) -#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) -#endif - -#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) - -#define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17)) -#define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18)) - -#define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22)) -#define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23)) - -#define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26)) - -#define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31)) - -/* System register offsets. */ -#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) -#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) -#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) - -/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY 24000000 /* 24MHz */ - -/* Generic Interrupt Controller Definitions */ -#ifdef CONFIG_GICV3 -#define GICD_BASE (0x2f000000) -#define GICR_BASE (0x2f100000) -#else - -#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP -#define GICD_BASE (0x2f000000) -#define GICC_BASE (0x2c000000) -#elif CONFIG_TARGET_VEXPRESS64_JUNO -#define GICD_BASE (0x2C010000) -#define GICC_BASE (0x2C02f000) -#endif -#endif /* !CONFIG_GICV3 */ - -#ifndef CONFIG_TARGET_VEXPRESS64_JUNO -/* The Vexpress64 simulators use SMSC91C111 */ -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE (0x01A000000) -#endif - -/* PL011 Serial Configuration */ -#ifdef CONFIG_TARGET_VEXPRESS64_JUNO -#define CONFIG_PL011_CLOCK 7372800 -#else -#define CONFIG_PL011_CLOCK 24000000 -#endif - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* Miscellaneous configurable options */ - -/* Physical Memory Map */ -#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ -/* Top 16MB reserved for secure world use */ -#define DRAM_SEC_SIZE 0x01000000 -#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -#ifdef CONFIG_TARGET_VEXPRESS64_JUNO -#define PHYS_SDRAM_2 (0x880000000) -#define PHYS_SDRAM_2_SIZE 0x180000000 -#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP && CONFIG_NR_DRAM_BANKS == 2 -#define PHYS_SDRAM_2 (0x880000000) -#define PHYS_SDRAM_2_SIZE 0x80000000 -#endif - -/* Enable memtest */ - -/* Initial environment variables */ -#ifdef CONFIG_TARGET_VEXPRESS64_JUNO -/* Copy the kernel and FDT to DRAM memory and boot */ -#define BOOTENV_DEV_AFS(devtypeu, devtypel, instance) \ - "bootcmd_afs=" \ - "afs load ${kernel_name} ${kernel_addr_r} ;"\ - "if test $? -eq 1; then "\ - " echo Loading ${kernel_alt_name} instead of ${kernel_name}; "\ - " afs load ${kernel_alt_name} ${kernel_addr_r};"\ - "fi ; "\ - "afs load ${fdtfile} ${fdt_addr_r} ;"\ - "if test $? -eq 1; then "\ - " echo Loading ${fdt_alt_name} instead of ${fdtfile}; "\ - " afs load ${fdt_alt_name} ${fdt_addr_r}; "\ - "fi ; "\ - "fdt addr ${fdt_addr_r}; fdt resize; " \ - "if afs load ${ramdisk_name} ${ramdisk_addr_r} ; "\ - "then "\ - " setenv ramdisk_param ${ramdisk_addr_r}; "\ - "else "\ - " setenv ramdisk_param -; "\ - "fi ; " \ - "booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}\0" -#define BOOTENV_DEV_NAME_AFS(devtypeu, devtypel, instance) "afs " - -#define BOOT_TARGET_DEVICES(func) \ - func(USB, usb, 0) \ - func(SATA, sata, 0) \ - func(SATA, sata, 1) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) \ - func(AFS, afs, na) - -#include - -/* - * Defines where the kernel and FDT exist in NOR flash and where it will - * be copied into DRAM - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_name=norkern\0" \ - "kernel_alt_name=Image\0" \ - "kernel_addr_r=0x80080000\0" \ - "ramdisk_name=ramdisk.img\0" \ - "ramdisk_addr_r=0x88000000\0" \ - "fdtfile=board.dtb\0" \ - "fdt_alt_name=juno\0" \ - "fdt_addr_r=0x80000000\0" \ - BOOTENV - -#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_name=Image\0" \ - "kernel_addr=0x80080000\0" \ - "initrd_name=ramdisk.img\0" \ - "initrd_addr=0x88000000\0" \ - "fdtfile=devtree.dtb\0" \ - "fdt_addr=0x83000000\0" \ - "boot_name=boot.img\0" \ - "boot_addr=0x8007f800\0" -#endif - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#ifdef CONFIG_TARGET_VEXPRESS64_JUNO -#define CONFIG_SYS_FLASH_BASE 0x08000000 -/* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */ -#define CONFIG_SYS_MAX_FLASH_SECT 259 -/* Store environment at top of flash in the same location as blank.img */ -/* in the Juno firmware. */ -#else -#define CONFIG_SYS_FLASH_BASE 0x0C000000 -/* 256 x 256KiB sectors */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 -/* Store environment at top of flash */ -#endif - -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#endif - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ -#define FLASH_MAX_SECTOR_SIZE 0x00040000 - -#endif /* __VEXPRESS_AEMV8A_H */ -- cgit v1.2.3