From 2775e08a2b73e53b26c23c67301ecfdae182b899 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 28 Jan 2020 00:46:40 +0000 Subject: sunxi: SPL SPI: Split off SPI0 base address So far on all supported Allwinner SoCs we find the old generation SPI controller always at address 0x1c05000, and the new generation one at 0x1c68000. However the Allwinner R40 SoC has a new generation SPI at the old address, and the H6 uses a completely different address. So split off the base address from the respective SPI registers, by changing the #defines to just contain offsets. The base address is provided by a function, so it can easily be extended later when support for those SoCs materialises. This does not change the code size (since the toolchain is clever enough to optimise this properly), also does not bring any functional change at this point. Signed-off-by: Andre Przywara Reviewed-by: Jagan Teki --- arch/arm/mach-sunxi/spl_spi_sunxi.c | 94 +++++++++++++++++++++---------------- 1 file changed, 53 insertions(+), 41 deletions(-) diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 043d9f6eade..5b4598a25b3 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -36,13 +36,13 @@ /* SUN4I variant of the SPI controller */ /*****************************************************************************/ -#define SUN4I_SPI0_CCTL (0x01C05000 + 0x1C) -#define SUN4I_SPI0_CTL (0x01C05000 + 0x08) -#define SUN4I_SPI0_RX (0x01C05000 + 0x00) -#define SUN4I_SPI0_TX (0x01C05000 + 0x04) -#define SUN4I_SPI0_FIFO_STA (0x01C05000 + 0x28) -#define SUN4I_SPI0_BC (0x01C05000 + 0x20) -#define SUN4I_SPI0_TC (0x01C05000 + 0x24) +#define SUN4I_SPI0_CCTL 0x1C +#define SUN4I_SPI0_CTL 0x08 +#define SUN4I_SPI0_RX 0x00 +#define SUN4I_SPI0_TX 0x04 +#define SUN4I_SPI0_FIFO_STA 0x28 +#define SUN4I_SPI0_BC 0x20 +#define SUN4I_SPI0_TC 0x24 #define SUN4I_CTL_ENABLE BIT(0) #define SUN4I_CTL_MASTER BIT(1) @@ -54,15 +54,15 @@ /* SUN6I variant of the SPI controller */ /*****************************************************************************/ -#define SUN6I_SPI0_CCTL (0x01C68000 + 0x24) -#define SUN6I_SPI0_GCR (0x01C68000 + 0x04) -#define SUN6I_SPI0_TCR (0x01C68000 + 0x08) -#define SUN6I_SPI0_FIFO_STA (0x01C68000 + 0x1C) -#define SUN6I_SPI0_MBC (0x01C68000 + 0x30) -#define SUN6I_SPI0_MTC (0x01C68000 + 0x34) -#define SUN6I_SPI0_BCC (0x01C68000 + 0x38) -#define SUN6I_SPI0_TXD (0x01C68000 + 0x200) -#define SUN6I_SPI0_RXD (0x01C68000 + 0x300) +#define SUN6I_SPI0_CCTL 0x24 +#define SUN6I_SPI0_GCR 0x04 +#define SUN6I_SPI0_TCR 0x08 +#define SUN6I_SPI0_FIFO_STA 0x1C +#define SUN6I_SPI0_MBC 0x30 +#define SUN6I_SPI0_MTC 0x34 +#define SUN6I_SPI0_BCC 0x38 +#define SUN6I_SPI0_TXD 0x200 +#define SUN6I_SPI0_RXD 0x300 #define SUN6I_CTL_ENABLE BIT(0) #define SUN6I_CTL_MASTER BIT(1) @@ -100,11 +100,21 @@ static void spi0_pinmux_setup(unsigned int pin_function) sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function); } +static uintptr_t spi0_base_address(void) +{ + if (!IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + return 0x01C05000; + + return 0x01C68000; +} + /* * Setup 6 MHz from OSC24M (because the BROM is doing the same). */ static void spi0_enable_clock(void) { + uintptr_t base = spi0_base_address(); + /* Deassert SPI0 reset on SUN6I */ if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) setbits_le32(SUN6I_BUS_SOFT_RST_REG0, @@ -114,36 +124,37 @@ static void spi0_enable_clock(void) setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); /* Divide by 4 */ - writel(SPI0_CLK_DIV_BY_4, IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ? - SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL); + writel(SPI0_CLK_DIV_BY_4, base + (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ? + SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL)); /* 24MHz from OSC24M */ writel((1 << 31), CCM_SPI0_CLK); if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { /* Enable SPI in the master mode and do a soft reset */ - setbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | - SUN6I_CTL_ENABLE | - SUN6I_CTL_SRST); + setbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | + SUN6I_CTL_ENABLE | SUN6I_CTL_SRST); /* Wait for completion */ - while (readl(SUN6I_SPI0_GCR) & SUN6I_CTL_SRST) + while (readl(base + SUN6I_SPI0_GCR) & SUN6I_CTL_SRST) ; } else { /* Enable SPI in the master mode and reset FIFO */ - setbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | - SUN4I_CTL_ENABLE | - SUN4I_CTL_TF_RST | - SUN4I_CTL_RF_RST); + setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | + SUN4I_CTL_ENABLE | + SUN4I_CTL_TF_RST | + SUN4I_CTL_RF_RST); } } static void spi0_disable_clock(void) { + uintptr_t base = spi0_base_address(); + /* Disable the SPI0 controller */ if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) - clrbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | + clrbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | SUN6I_CTL_ENABLE); else - clrbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | + clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | SUN4I_CTL_ENABLE); /* Disable the SPI0 clock */ @@ -227,6 +238,7 @@ static void spi0_read_data(void *buf, u32 addr, u32 len) { u8 *buf8 = buf; u32 chunk_len; + uintptr_t base = spi0_base_address(); while (len > 0) { chunk_len = len; @@ -235,23 +247,23 @@ static void spi0_read_data(void *buf, u32 addr, u32 len) if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { sunxi_spi0_read_data(buf8, addr, chunk_len, - SUN6I_SPI0_TCR, + base + SUN6I_SPI0_TCR, SUN6I_TCR_XCH, - SUN6I_SPI0_FIFO_STA, - SUN6I_SPI0_TXD, - SUN6I_SPI0_RXD, - SUN6I_SPI0_MBC, - SUN6I_SPI0_MTC, - SUN6I_SPI0_BCC); + base + SUN6I_SPI0_FIFO_STA, + base + SUN6I_SPI0_TXD, + base + SUN6I_SPI0_RXD, + base + SUN6I_SPI0_MBC, + base + SUN6I_SPI0_MTC, + base + SUN6I_SPI0_BCC); } else { sunxi_spi0_read_data(buf8, addr, chunk_len, - SUN4I_SPI0_CTL, + base + SUN4I_SPI0_CTL, SUN4I_CTL_XCH, - SUN4I_SPI0_FIFO_STA, - SUN4I_SPI0_TX, - SUN4I_SPI0_RX, - SUN4I_SPI0_BC, - SUN4I_SPI0_TC, + base + SUN4I_SPI0_FIFO_STA, + base + SUN4I_SPI0_TX, + base + SUN4I_SPI0_RX, + base + SUN4I_SPI0_BC, + base + SUN4I_SPI0_TC, 0); } -- cgit v1.2.3 From 56f51f3875144822415757f1887d2254b6b8e937 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 28 Jan 2020 00:46:41 +0000 Subject: sunxi: SPL SPI: Introduce is_sun6i_gen_spi() So far we were using the CONFIG_SUNXI_GEN_SUN6I symbol to select between the two SPI controller generations used on Allwinner SoCs. This is a convenience symbol to roughly differentiate between "older" and "newer" generation of SoCs. The H6 SoCs is the newest SoC so far, but is sufficiently different to not define this symbol. However it is using a SPI controller compatible to the "new gen" SoCs. To prepare for H6 support, we replace the check for this single symbol with an explicit function, which can later be extended. For now we just return CONFIG_SUNXI_GEN_SUN6I in there, so this does not create a functional change. Signed-off-by: Andre Przywara Reviewed-by: Jagan Teki --- arch/arm/mach-sunxi/spl_spi_sunxi.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 5b4598a25b3..cab6affe8d1 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -100,9 +100,14 @@ static void spi0_pinmux_setup(unsigned int pin_function) sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function); } +static bool is_sun6i_gen_spi(void) +{ + return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I); +} + static uintptr_t spi0_base_address(void) { - if (!IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + if (!is_sun6i_gen_spi()) return 0x01C05000; return 0x01C68000; @@ -116,7 +121,7 @@ static void spi0_enable_clock(void) uintptr_t base = spi0_base_address(); /* Deassert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + if (is_sun6i_gen_spi()) setbits_le32(SUN6I_BUS_SOFT_RST_REG0, (1 << AHB_RESET_SPI0_SHIFT)); @@ -124,12 +129,12 @@ static void spi0_enable_clock(void) setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); /* Divide by 4 */ - writel(SPI0_CLK_DIV_BY_4, base + (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ? + writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ? SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL)); /* 24MHz from OSC24M */ writel((1 << 31), CCM_SPI0_CLK); - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { + if (is_sun6i_gen_spi()) { /* Enable SPI in the master mode and do a soft reset */ setbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | SUN6I_CTL_ENABLE | SUN6I_CTL_SRST); @@ -150,7 +155,7 @@ static void spi0_disable_clock(void) uintptr_t base = spi0_base_address(); /* Disable the SPI0 controller */ - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + if (is_sun6i_gen_spi()) clrbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | SUN6I_CTL_ENABLE); else @@ -164,7 +169,7 @@ static void spi0_disable_clock(void) clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); /* Assert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + if (is_sun6i_gen_spi()) clrbits_le32(SUN6I_BUS_SOFT_RST_REG0, (1 << AHB_RESET_SPI0_SHIFT)); } @@ -184,7 +189,8 @@ static void spi0_deinit(void) { /* New SoCs can disable pins, older could only set them as input */ unsigned int pin_function = SUNXI_GPIO_INPUT; - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + + if (is_sun6i_gen_spi()) pin_function = SUNXI_GPIO_DISABLE; spi0_disable_clock(); @@ -245,7 +251,7 @@ static void spi0_read_data(void *buf, u32 addr, u32 len) if (chunk_len > SPI_READ_MAX_SIZE) chunk_len = SPI_READ_MAX_SIZE; - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { + if (is_sun6i_gen_spi()) { sunxi_spi0_read_data(buf8, addr, chunk_len, base + SUN6I_SPI0_TCR, SUN6I_TCR_XCH, -- cgit v1.2.3 From da19a0dbc817fcda7a564360767e02b5c174cf1e Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 28 Jan 2020 00:46:42 +0000 Subject: sunxi: SPL SPI: Add SPI boot support for the Allwinner R40 SoC Now that we can easily select an SoC specific SPI0 base address, adding support for the Allwinner R40 is fairly trivial: We set the base address, add this SoC to the ones that use PC23 and enable it in Kconfig. This allows booting from SPI flash on R40 boards. Tested on a Bananapi M2 Berry with SPI flash connected to the header pins. Signed-off-by: Andre Przywara Reviewed-by: Jagan Teki --- arch/arm/mach-sunxi/Kconfig | 2 +- arch/arm/mach-sunxi/spl_spi_sunxi.c | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 3a3b6734301..eb046160e63 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -994,7 +994,7 @@ config SPL_STACK_R_ADDR config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 help Enable support for SPI Flash. This option allows SPL to read from sunxi SPI Flash. It uses the same method as the boot ROM, so does diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index cab6affe8d1..357953cfcef 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -94,7 +94,8 @@ static void spi0_pinmux_setup(unsigned int pin_function) for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++) sunxi_gpio_set_cfgpin(pin, pin_function); - if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I)) + if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) || + IS_ENABLED(CONFIG_MACH_SUN8I_R40)) sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function); else sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function); @@ -107,6 +108,9 @@ static bool is_sun6i_gen_spi(void) static uintptr_t spi0_base_address(void) { + if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) + return 0x01C05000; + if (!is_sun6i_gen_spi()) return 0x01C05000; -- cgit v1.2.3 From fd40ad0d579412ea2cd31388e287d0592ddb5d73 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 28 Jan 2020 00:46:43 +0000 Subject: sunxi: SPL SPI: Add SPI boot support for the Allwinner H6 SoC The Allwinner H6 SoC uses a quite different memory map, also changes the clocks quite a bit. This requires some changes to the SPL SPI routine, which hardcodes these values so far. Using the just introduced helper functions to determine base address and SPI controller generation, we can cover some of these differences easily. The clock setup is different, so requires some explicit code changes there (reset and clock gate in one register at a different address). Also we need to change the pinmux function to use a different set of pins that the H6 uses for SPI0. Eventually we can enable the H6 to use SPI booting in Kconfig. Signed-off-by: Andre Przywara Reviewed-by: Jagan Teki --- arch/arm/mach-sunxi/Kconfig | 2 +- arch/arm/mach-sunxi/spl_spi_sunxi.c | 41 +++++++++++++++++++++++++++++-------- 2 files changed, 33 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index eb046160e63..be0822bfb7d 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -994,7 +994,7 @@ config SPL_STACK_R_ADDR config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 help Enable support for SPI Flash. This option allows SPL to read from sunxi SPI Flash. It uses the same method as the boot ROM, so does diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 357953cfcef..a3997b25901 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -72,7 +72,12 @@ /*****************************************************************************/ #define CCM_AHB_GATING0 (0x01C20000 + 0x60) +#define CCM_H6_SPI_BGR_REG (0x03001000 + 0x96c) +#ifdef CONFIG_MACH_SUN50I_H6 +#define CCM_SPI0_CLK (0x03001000 + 0x940) +#else #define CCM_SPI0_CLK (0x01C20000 + 0xA0) +#endif #define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0) #define AHB_RESET_SPI0_SHIFT 20 @@ -86,14 +91,21 @@ /* * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3. + * The H6 uses PC0, PC2, PC3, PC5. */ static void spi0_pinmux_setup(unsigned int pin_function) { - unsigned int pin; + /* All chips use PC0 and PC2. */ + sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); + sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function); - for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++) - sunxi_gpio_set_cfgpin(pin, pin_function); + /* All chips except H6 use PC1, and only H6 uses PC5. */ + if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function); + else + sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function); + /* Older generations use PC23 for CS, newer ones use PC3. */ if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) || IS_ENABLED(CONFIG_MACH_SUN8I_R40)) sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function); @@ -103,7 +115,8 @@ static void spi0_pinmux_setup(unsigned int pin_function) static bool is_sun6i_gen_spi(void) { - return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I); + return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) || + IS_ENABLED(CONFIG_MACH_SUN50I_H6); } static uintptr_t spi0_base_address(void) @@ -111,6 +124,9 @@ static uintptr_t spi0_base_address(void) if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) return 0x01C05000; + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + return 0x05010000; + if (!is_sun6i_gen_spi()) return 0x01C05000; @@ -125,12 +141,15 @@ static void spi0_enable_clock(void) uintptr_t base = spi0_base_address(); /* Deassert SPI0 reset on SUN6I */ - if (is_sun6i_gen_spi()) + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + setbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1); + else if (is_sun6i_gen_spi()) setbits_le32(SUN6I_BUS_SOFT_RST_REG0, (1 << AHB_RESET_SPI0_SHIFT)); /* Open the SPI0 gate */ - setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); + if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); /* Divide by 4 */ writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ? @@ -170,10 +189,13 @@ static void spi0_disable_clock(void) writel(0, CCM_SPI0_CLK); /* Close the SPI0 gate */ - clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); + if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); /* Assert SPI0 reset on SUN6I */ - if (is_sun6i_gen_spi()) + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + clrbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1); + else if (is_sun6i_gen_spi()) clrbits_le32(SUN6I_BUS_SOFT_RST_REG0, (1 << AHB_RESET_SPI0_SHIFT)); } @@ -182,7 +204,8 @@ static void spi0_init(void) { unsigned int pin_function = SUNXI_GPC_SPI0; - if (IS_ENABLED(CONFIG_MACH_SUN50I)) + if (IS_ENABLED(CONFIG_MACH_SUN50I) || + IS_ENABLED(CONFIG_MACH_SUN50I_H6)) pin_function = SUN50I_GPC_SPI0; spi0_pinmux_setup(pin_function); -- cgit v1.2.3 From e66a34eaba40aef876585075bc54f7528e9eccf4 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 28 Jan 2020 00:46:44 +0000 Subject: sunxi: Pine H64: Enable SPI booting in defconfig The Pine H64 board comes with some onboard SPI flash chip, which is perfect for loading SPL, ATF and U-Boot proper from there. Enable the functionality in the defconfig, so that we use sunxi-fel to transfer a bootable image to the NOR flash. Signed-off-by: Andre Przywara Reviewed-by: Jagan Teki --- configs/pine_h64_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index b49dbea4d4f..c0adbf3dd0f 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -16,3 +16,4 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_SPL_SPI_SUNXI=y -- cgit v1.2.3 From 48313fe51008f777ee97e8963ff8b392fb6c4228 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 20 Feb 2020 17:51:14 +0000 Subject: sunxi: Move common defconfig options to Kconfig Some config symbols are found in *almost* every _defconfig file for Allwinner boards, because those options are actually a platform choice, and not a per-board decision. Some of these options are older, some have recently been added. Move those options to be set for all Allwinner boards in their respective Kconfig files. The rationales are as follows: - NR_DRAM_BANKS: All Allwinner SoC map DRAM at one contiguous region of address space only, starting at 1 GB. So it's always one bank. - SPL_{DOS,EFI}_PARTITION: The Allwinner SPL does only support raw MMC accesses, we don't care about filesystems or partitions in there, so there is no need to define those symbols at all. - USE_PREBOOT: We start USB early when a keyboard is configured, using the preboot env variable, so we need to set this variable. - SYS_RELOC_GD_ENV_ADDR: We don't specify any ENV_ADDR, so need this symbol to be set (according to 8d8ee47e03e). - SYS_USB_EVENT_POLL_VIA_INT_QUEUE: According to commit eab9433aa55428, specifying this reduces the latency of the USB keyboard handling, so this was formerly enabled in config headers for all Allwinner boards. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Tested-by: Jagan Teki # Amarula A64-Relic Reviewed-by: Jagan Teki --- Kconfig | 1 + arch/arm/Kconfig | 2 ++ disk/Kconfig | 2 ++ drivers/usb/Kconfig | 1 + 4 files changed, 6 insertions(+) diff --git a/Kconfig b/Kconfig index 66148ce4779..b4864cdf8d3 100644 --- a/Kconfig +++ b/Kconfig @@ -115,6 +115,7 @@ config ENV_VARS_UBOOT_CONFIG config NR_DRAM_BANKS int "Number of DRAM banks" + default 1 if ARCH_SUNXI default 4 help This defines the number of DRAM banks. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5d367888d8a..1cf134624a9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -989,6 +989,8 @@ config ARCH_SUNXI select USB_KEYBOARD if DISTRO_DEFAULTS select USB_STORAGE if DISTRO_DEFAULTS select SPL_USE_TINY_PRINTF + select USE_PREBOOT + select SYS_RELOC_GD_ENV_ADDR imply CMD_DM imply CMD_GPT imply CMD_UBI if MTD_RAW_NAND diff --git a/disk/Kconfig b/disk/Kconfig index 28fb81c2ee6..747275c2ba1 100644 --- a/disk/Kconfig +++ b/disk/Kconfig @@ -46,6 +46,7 @@ config DOS_PARTITION config SPL_DOS_PARTITION bool "Enable MS Dos partition table for SPL" depends on SPL && PARTITIONS + default n if ARCH_SUNXI default y if DOS_PARTITION config ISO_PARTITION @@ -112,6 +113,7 @@ config EFI_PARTITION_ENTRIES_OFF config SPL_EFI_PARTITION bool "Enable EFI GPT partition table for SPL" depends on SPL && PARTITIONS + default n if ARCH_SUNXI default y if EFI_PARTITION config PARTITION_UUIDS diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index bea4a92b61f..928a89133cf 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -108,6 +108,7 @@ config USB_KEYBOARD_FN_KEYS choice prompt "USB keyboard polling" + default SYS_USB_EVENT_POLL_VIA_INT_QUEUE if ARCH_SUNXI default SYS_USB_EVENT_POLL ---help--- Enable a polling mechanism for USB keyboard. -- cgit v1.2.3 From cd27b933f50fba58c764a775389d68f4ff9ebe88 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 20 Feb 2020 17:51:15 +0000 Subject: sunxi: Remove no longer needed default options from defconfigs Now that those common Allwinner config symbols are defined automatically for all boards in their Kconfig files, we can remove the now redundant definitions from the boards' _defconfig files. Some boards had a differing definiton for some of those symbols, it looks like mostly to "merge races" when the symbol was introduced (new board *_defconfig file missed the "add symbol to all files" patch). Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Tested-by: Jagan Teki # Amarula A64-Relic Reviewed-by: Jagan Teki --- configs/A10-OLinuXino-Lime_defconfig | 6 ------ configs/A10s-OLinuXino-M_defconfig | 6 ------ configs/A13-OLinuXinoM_defconfig | 6 ------ configs/A13-OLinuXino_defconfig | 5 ----- configs/A20-OLinuXino-Lime2-eMMC_defconfig | 5 ----- configs/A20-OLinuXino-Lime2_defconfig | 5 ----- configs/A20-OLinuXino-Lime_defconfig | 6 ------ configs/A20-OLinuXino_MICRO-eMMC_defconfig | 6 ------ configs/A20-OLinuXino_MICRO_defconfig | 6 ------ configs/A20-Olimex-SOM-EVB_defconfig | 6 ------ configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 5 ----- configs/A20-Olimex-SOM204-EVB_defconfig | 5 ----- configs/A33-OLinuXino_defconfig | 6 ------ configs/Ainol_AW1_defconfig | 6 ------ configs/Ampe_A76_defconfig | 6 ------ configs/Auxtek-T003_defconfig | 6 ------ configs/Auxtek-T004_defconfig | 6 ------ configs/Bananapi_M2_Ultra_defconfig | 4 ---- configs/Bananapi_defconfig | 6 ------ configs/Bananapi_m2m_defconfig | 4 ---- configs/Bananapro_defconfig | 6 ------ configs/CHIP_defconfig | 6 ------ configs/CHIP_pro_defconfig | 4 ---- configs/CSQ_CS908_defconfig | 6 ------ configs/Chuwi_V7_CW0825_defconfig | 6 ------ configs/Colombus_defconfig | 6 ------ configs/Cubieboard2_defconfig | 6 ------ configs/Cubieboard4_defconfig | 6 ------ configs/Cubieboard_defconfig | 6 ------ configs/Cubietruck_defconfig | 5 ----- configs/Cubietruck_plus_defconfig | 6 ------ configs/Empire_electronix_d709_defconfig | 6 ------ configs/Empire_electronix_m712_defconfig | 6 ------ configs/Hummingbird_A31_defconfig | 6 ------ configs/Hyundai_A7HD_defconfig | 6 ------ configs/Itead_Ibox_A20_defconfig | 6 ------ configs/Lamobo_R1_defconfig | 6 ------ configs/LicheePi_Zero_defconfig | 6 ------ configs/Linksprite_pcDuino3_Nano_defconfig | 6 ------ configs/Linksprite_pcDuino3_defconfig | 6 ------ configs/Linksprite_pcDuino_defconfig | 6 ------ configs/MK808C_defconfig | 6 ------ configs/MSI_Primo73_defconfig | 6 ------ configs/MSI_Primo81_defconfig | 6 ------ configs/Marsboard_A10_defconfig | 6 ------ configs/Mele_A1000G_quad_defconfig | 6 ------ configs/Mele_A1000_defconfig | 6 ------ configs/Mele_I7_defconfig | 6 ------ configs/Mele_M3_defconfig | 6 ------ configs/Mele_M5_defconfig | 6 ------ configs/Mele_M9_defconfig | 6 ------ configs/Merrii_A80_Optimus_defconfig | 6 ------ configs/Mini-X_defconfig | 6 ------ configs/Nintendo_NES_Classic_Edition_defconfig | 6 ------ configs/Orangepi_defconfig | 6 ------ configs/Orangepi_mini_defconfig | 6 ------ configs/Sinlinx_SinA31s_defconfig | 6 ------ configs/Sinlinx_SinA33_defconfig | 5 ----- configs/Sinovoip_BPI_M2_defconfig | 6 ------ configs/Sinovoip_BPI_M3_defconfig | 6 ------ configs/Sunchip_CX-A99_defconfig | 6 ------ configs/UTOO_P66_defconfig | 6 ------ configs/Wexler_TAB7200_defconfig | 6 ------ configs/Wits_Pro_A20_DKT_defconfig | 6 ------ configs/Wobo_i5_defconfig | 6 ------ configs/Yones_Toptech_BD1078_defconfig | 6 ------ configs/Yones_Toptech_BS1078_V2_defconfig | 6 ------ configs/a64-olinuxino-emmc_defconfig | 6 ------ configs/a64-olinuxino_defconfig | 6 ------ configs/amarula_a64_relic_defconfig | 6 ------ configs/ba10_tv_box_defconfig | 6 ------ configs/bananapi_m1_plus_defconfig | 5 ----- configs/bananapi_m2_berry_defconfig | 4 ---- configs/bananapi_m2_plus_h3_defconfig | 6 ------ configs/bananapi_m2_plus_h5_defconfig | 6 ------ configs/bananapi_m2_zero_defconfig | 4 ---- configs/bananapi_m64_defconfig | 6 ------ configs/beelink_gs1_defconfig | 5 ----- configs/beelink_x2_defconfig | 5 ----- configs/colorfly_e708_q1_defconfig | 6 ------ configs/difrnce_dit4350_defconfig | 6 ------ configs/dserve_dsrv9703c_defconfig | 6 ------ configs/emlid_neutis_n5_devboard_defconfig | 5 ----- configs/ga10h_v1_1_defconfig | 6 ------ configs/gt90h_v4_defconfig | 6 ------ configs/h8_homlet_v2_defconfig | 6 ------ configs/i12-tvbox_defconfig | 6 ------ configs/iNet_3F_defconfig | 6 ------ configs/iNet_3W_defconfig | 6 ------ configs/iNet_86VS_defconfig | 6 ------ configs/iNet_D978_rev2_defconfig | 6 ------ configs/icnova-a20-swac_defconfig | 6 ------ configs/inet1_defconfig | 6 ------ configs/inet86dz_defconfig | 6 ------ configs/inet97fv2_defconfig | 6 ------ configs/inet98v_rev2_defconfig | 6 ------ configs/inet9f_rev03_defconfig | 6 ------ configs/inet_q972_defconfig | 6 ------ configs/jesurun_q5_defconfig | 6 ------ configs/libretech_all_h3_cc_h2_plus_defconfig | 6 ------ configs/libretech_all_h3_cc_h3_defconfig | 6 ------ configs/libretech_all_h3_cc_h5_defconfig | 6 ------ configs/libretech_all_h3_it_h5_defconfig | 6 ------ configs/libretech_all_h5_cc_h5_defconfig | 6 ------ configs/mixtile_loftq_defconfig | 6 ------ configs/mk802_a10s_defconfig | 6 ------ configs/mk802_defconfig | 6 ------ configs/mk802ii_defconfig | 6 ------ configs/nanopi_a64_defconfig | 6 ------ configs/nanopi_m1_defconfig | 6 ------ configs/nanopi_m1_plus_defconfig | 6 ------ configs/nanopi_neo2_defconfig | 6 ------ configs/nanopi_neo_air_defconfig | 6 ------ configs/nanopi_neo_defconfig | 6 ------ configs/nanopi_neo_plus2_defconfig | 5 ----- configs/oceanic_5205_5inmfd_defconfig | 6 ------ configs/orangepi_2_defconfig | 6 ------ configs/orangepi_lite2_defconfig | 5 ----- configs/orangepi_lite_defconfig | 6 ------ configs/orangepi_one_defconfig | 6 ------ configs/orangepi_one_plus_defconfig | 5 ----- configs/orangepi_pc2_defconfig | 6 ------ configs/orangepi_pc_defconfig | 6 ------ configs/orangepi_pc_plus_defconfig | 6 ------ configs/orangepi_plus2e_defconfig | 6 ------ configs/orangepi_plus_defconfig | 6 ------ configs/orangepi_prime_defconfig | 6 ------ configs/orangepi_r1_defconfig | 4 ---- configs/orangepi_win_defconfig | 6 ------ configs/orangepi_zero_defconfig | 4 ---- configs/orangepi_zero_plus2_defconfig | 6 ------ configs/orangepi_zero_plus2_h3_defconfig | 5 ----- configs/orangepi_zero_plus_defconfig | 6 ------ configs/parrot_r16_defconfig | 5 ----- configs/pine64-lts_defconfig | 6 ------ configs/pine64_plus_defconfig | 6 ------ configs/pine_h64_defconfig | 5 ----- configs/pinebook_defconfig | 5 ----- configs/polaroid_mid2407pxe03_defconfig | 6 ------ configs/polaroid_mid2809pxe04_defconfig | 6 ------ configs/pov_protab2_ips9_defconfig | 6 ------ configs/q8_a13_tablet_defconfig | 6 ------ configs/q8_a23_tablet_800x480_defconfig | 6 ------ configs/q8_a33_tablet_1024x600_defconfig | 6 ------ configs/q8_a33_tablet_800x480_defconfig | 6 ------ configs/r7-tv-dongle_defconfig | 6 ------ configs/sopine_baseboard_defconfig | 6 ------ configs/sun8i_a23_evb_defconfig | 6 ------ configs/sunxi_Gemei_G9_defconfig | 6 ------ configs/tbs_a711_defconfig | 5 ----- configs/teres_i_defconfig | 5 ----- 151 files changed, 872 deletions(-) diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig index 363156c4e21..b835f15b6fe 100644 --- a/configs/A10-OLinuXino-Lime_defconfig +++ b/configs/A10-OLinuXino-Lime_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=480 @@ -11,12 +10,8 @@ CONFIG_I2C1_ENABLE=y CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_MII=y CONFIG_SUN4I_EMAC=y @@ -25,4 +20,3 @@ CONFIG_AXP_ALDO4_VOLT=2800 CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig index b31d6ac2f5e..4145f720a35 100644 --- a/configs/A10s-OLinuXino-M_defconfig +++ b/configs/A10s-OLinuXino-M_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 @@ -9,16 +8,11 @@ CONFIG_MMC1_CD_PIN="PG13" CONFIG_MMC_SUNXI_SLOT_EXTRA=1 CONFIG_USB1_VBUS_PIN="PB10" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_MII=y CONFIG_SUN4I_EMAC=y CONFIG_AXP152_POWER=y CONFIG_CONS_INDEX=2 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig index fe5b20f5d8f..a879021e7f5 100644 --- a/configs/A13-OLinuXinoM_defconfig +++ b/configs/A13-OLinuXinoM_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=408 @@ -13,13 +12,8 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y CONFIG_VIDEO_LCD_POWER="PB10" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUNXI_NO_PMIC=y CONFIG_CONS_INDEX=2 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig index 5163b331f83..bb68698fd69 100644 --- a/configs/A13-OLinuXino_defconfig +++ b/configs/A13-OLinuXino_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=408 @@ -15,14 +14,11 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DFU_RAM=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_AXP_ALDO3_VOLT=3300 @@ -30,4 +26,3 @@ CONFIG_CONS_INDEX=2 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig index 7dc736e9e10..40b3883971b 100644 --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 @@ -13,14 +12,11 @@ CONFIG_SATAPWR="PC3" CONFIG_SPL_SPI_SUNXI=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2-emmc" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_DFU_RAM=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y @@ -36,4 +32,3 @@ CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig index ea97bbb0524..2b082cab595 100644 --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 @@ -11,14 +10,11 @@ CONFIG_I2C1_ENABLE=y CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_DFU_RAM=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y @@ -34,4 +30,3 @@ CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig index 3fbf8746185..975df4e7783 100644 --- a/configs/A20-OLinuXino-Lime_defconfig +++ b/configs/A20-OLinuXino-Lime_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 @@ -9,12 +8,8 @@ CONFIG_I2C1_ENABLE=y CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y @@ -24,4 +19,3 @@ CONFIG_AXP_ALDO4_VOLT=2800 CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig index 2802df63b44..0ccb609a22f 100644 --- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig +++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 @@ -11,12 +10,8 @@ CONFIG_VIDEO_VGA=y CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro-emmc" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y @@ -27,4 +22,3 @@ CONFIG_AXP_ALDO4_VOLT=2800 CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig index fe72b1fb074..0a68fd9e6a8 100644 --- a/configs/A20-OLinuXino_MICRO_defconfig +++ b/configs/A20-OLinuXino_MICRO_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 @@ -12,12 +11,8 @@ CONFIG_VIDEO_VGA=y CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y @@ -28,4 +23,3 @@ CONFIG_AXP_ALDO4_VOLT=2800 CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig index 696a211e49a..5b5ed3bb0a9 100644 --- a/configs/A20-Olimex-SOM-EVB_defconfig +++ b/configs/A20-Olimex-SOM-EVB_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 @@ -13,12 +12,8 @@ CONFIG_USB0_VBUS_DET="PH5" CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som-evb" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y @@ -29,4 +24,3 @@ CONFIG_AXP_ALDO4_VOLT=2800 CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig index ba18d1aac44..ee3b752ec33 100644 --- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 @@ -13,12 +12,9 @@ CONFIG_SATAPWR="PC3" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som204-evb-emmc" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_PHY_ADDR=3 @@ -34,4 +30,3 @@ CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig index 9515ba36aa2..0272911ecfe 100644 --- a/configs/A20-Olimex-SOM204-EVB_defconfig +++ b/configs/A20-Olimex-SOM204-EVB_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 @@ -12,12 +11,9 @@ CONFIG_SATAPWR="PC3" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som204-evb" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_PHY_ADDR=3 @@ -33,4 +29,3 @@ CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/A33-OLinuXino_defconfig b/configs/A33-OLinuXino_defconfig index 3c6ddad62a5..5f4149861af 100644 --- a/configs/A33-OLinuXino_defconfig +++ b/configs/A33-OLinuXino_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_A33=y CONFIG_DRAM_CLK=432 @@ -16,11 +15,6 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PB2" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-olinuxino" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP_DCDC1_VOLT=3300 CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig index d66ad1bb70c..72aac60c16c 100644 --- a/configs/Ainol_AW1_defconfig +++ b/configs/Ainol_AW1_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 @@ -14,11 +13,6 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ainol-aw1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig index b36a9737056..1f547334c2c 100644 --- a/configs/Ampe_A76_defconfig +++ b/configs/Ampe_A76_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 @@ -15,12 +14,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig index 2be5edc7568..5c72c97ecbc 100644 --- a/configs/Auxtek-T003_defconfig +++ b/configs/Auxtek-T003_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=408 @@ -8,14 +7,9 @@ CONFIG_DRAM_EMR1=0 CONFIG_USB1_VBUS_PIN="PB10" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t003" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP152_POWER=y CONFIG_CONS_INDEX=2 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig index 5fbefd2a97a..1cd13b90fcc 100644 --- a/configs/Auxtek-T004_defconfig +++ b/configs/Auxtek-T004_defconfig @@ -1,19 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP152_POWER=y CONFIG_CONS_INDEX=2 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig index 31a37e96757..e3d676708d7 100644 --- a/configs/Bananapi_M2_Ultra_defconfig +++ b/configs/Bananapi_M2_Ultra_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_R40=y CONFIG_DRAM_CLK=576 @@ -11,10 +10,8 @@ CONFIG_USB1_VBUS_PIN="PH23" CONFIG_USB2_VBUS_PIN="PH23" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_RGMII=y CONFIG_SUN8I_EMAC=y @@ -23,4 +20,3 @@ CONFIG_AXP_ELDO3_VOLT=1200 CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig index 6471a2c74e8..b309171d041 100644 --- a/configs/Bananapi_defconfig +++ b/configs/Bananapi_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 @@ -9,12 +8,8 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y @@ -24,4 +19,3 @@ CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Bananapi_m2m_defconfig b/configs/Bananapi_m2m_defconfig index 576262215b9..2649c7e84a0 100644 --- a/configs/Bananapi_m2m_defconfig +++ b/configs/Bananapi_m2m_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_A33=y CONFIG_DRAM_CLK=600 @@ -10,11 +9,8 @@ CONFIG_MMC0_CD_PIN="PB4" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB0_ID_DET="PH8" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-bananapi-m2m" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig index e9f4f3086a5..0cec760ffa2 100644 --- a/configs/Bananapro_defconfig +++ b/configs/Bananapro_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 @@ -11,12 +10,8 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y @@ -27,4 +22,3 @@ CONFIG_AXP_ALDO4_VOLT=2500 CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig index f28f5fc89c4..a373dfd0782 100644 --- a/configs/CHIP_defconfig +++ b/configs/CHIP_defconfig @@ -1,19 +1,14 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y CONFIG_USB0_VBUS_PIN="PB10" CONFIG_VIDEO_COMPOSITE=y -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DFU_RAM=y # CONFIG_MMC is not set CONFIG_AXP_ALDO3_VOLT=3300 @@ -22,4 +17,3 @@ CONFIG_CONS_INDEX=2 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig index 844b6a6143e..3bd8b2a5414 100644 --- a/configs/CHIP_pro_defconfig +++ b/configs/CHIP_pro_defconfig @@ -1,11 +1,9 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y CONFIG_USB0_VBUS_PIN="PB10" -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTDPARTS=y @@ -15,7 +13,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-gr8-chip-pro" CONFIG_ENV_IS_IN_UBI=y CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="uboot-env" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y @@ -28,5 +25,4 @@ CONFIG_CONS_INDEX=2 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y CONFIG_USB_FUNCTION_MASS_STORAGE=y diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig index a3470d64e07..f9026a422df 100644 --- a/configs/CSQ_CS908_defconfig +++ b/configs/CSQ_CS908_defconfig @@ -1,17 +1,12 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-cs908" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_SUN7I_GMAC=y @@ -20,4 +15,3 @@ CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig index a6693435b98..9af5eb3cdb3 100644 --- a/configs/Chuwi_V7_CW0825_defconfig +++ b/configs/Chuwi_V7_CW0825_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=408 @@ -14,14 +13,9 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-chuwi-v7-cw0825" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y CONFIG_VIDEO_LCD_SPI_CS="PA0" CONFIG_VIDEO_LCD_SPI_SCLK="PA1" CONFIG_VIDEO_LCD_SPI_MOSI="PA2" diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig index cc59f5dc479..f70f92e0a62 100644 --- a/configs/Colombus_defconfig +++ b/configs/Colombus_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_CLK=240 @@ -17,11 +16,7 @@ CONFIG_VIDEO_LCD_PANEL_I2C_SDA="PA23" CONFIG_VIDEO_LCD_PANEL_I2C_SCL="PA24" CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-colombus" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y CONFIG_MII=y @@ -29,4 +24,3 @@ CONFIG_SUN7I_GMAC=y CONFIG_AXP_ALDO1_VOLT=3300 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig index 0c05ca4604d..0c7aafd25af 100644 --- a/configs/Cubieboard2_defconfig +++ b/configs/Cubieboard2_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=480 @@ -8,12 +7,8 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y @@ -21,4 +16,3 @@ CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig index 84280a2149b..90b2c69e5f1 100644 --- a/configs/Cubieboard4_defconfig +++ b/configs/Cubieboard4_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN9I=y CONFIG_DRAM_CLK=672 @@ -12,10 +11,5 @@ CONFIG_USB0_ID_DET="PH16" CONFIG_USB1_VBUS_PIN="PH14" CONFIG_USB3_VBUS_PIN="PH15" CONFIG_AXP_GPIO=y -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-cubieboard4" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP809_POWER=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig index ad2a0069747..2b96c113ad1 100644 --- a/configs/Cubieboard_defconfig +++ b/configs/Cubieboard_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=480 @@ -8,16 +7,11 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_MII=y CONFIG_SUN4I_EMAC=y CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig index bc4d4a27eb2..32c44ff382a 100644 --- a/configs/Cubietruck_defconfig +++ b/configs/Cubietruck_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 @@ -13,14 +12,11 @@ CONFIG_SATAPWR="PH12" CONFIG_GMAC_TX_DELAY=1 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_DFU_RAM=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y @@ -32,4 +28,3 @@ CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig index 79763c1457e..7717feb56e1 100644 --- a/configs/Cubietruck_plus_defconfig +++ b/configs/Cubietruck_plus_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_A83T=y CONFIG_DRAM_CLK=672 @@ -15,12 +14,8 @@ CONFIG_USB2_VBUS_PIN="PL6" CONFIG_I2C0_ENABLE=y CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y CONFIG_AXP_DLDO3_VOLT=2500 @@ -29,4 +24,3 @@ CONFIG_AXP_FLDO1_VOLT=1200 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig index cfeb356ad93..8e284a3718f 100644 --- a/configs/Empire_electronix_d709_defconfig +++ b/configs/Empire_electronix_d709_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 @@ -16,12 +15,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-d709" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Empire_electronix_m712_defconfig b/configs/Empire_electronix_m712_defconfig index 24a04937502..26cc0e7ed6d 100644 --- a/configs/Empire_electronix_m712_defconfig +++ b/configs/Empire_electronix_m712_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=408 @@ -15,12 +14,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-m712" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig index aa97e5a5d39..15984ec5a3c 100644 --- a/configs/Hummingbird_A31_defconfig +++ b/configs/Hummingbird_A31_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_ZQ=251 @@ -9,11 +8,7 @@ CONFIG_USB2_VBUS_PIN="" CONFIG_VIDEO_VGA_VIA_LCD=y CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-hummingbird" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y CONFIG_MII=y @@ -21,4 +16,3 @@ CONFIG_SUN7I_GMAC=y CONFIG_AXP_ALDO1_VOLT=3300 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig index ff84e2d5c7d..01580a8488f 100644 --- a/configs/Hyundai_A7HD_defconfig +++ b/configs/Hyundai_A7HD_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_EMR1=4 @@ -15,11 +14,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-hyundai-a7hd" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig index 71ffb9d45f9..9ddfb6f5e2a 100644 --- a/configs/Itead_Ibox_A20_defconfig +++ b/configs/Itead_Ibox_A20_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=480 @@ -8,12 +7,8 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-itead-ibox" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y @@ -21,4 +16,3 @@ CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig index 869fd7463fd..c3cb3654bb2 100644 --- a/configs/Lamobo_R1_defconfig +++ b/configs/Lamobo_R1_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 @@ -10,12 +9,8 @@ CONFIG_SATAPWR="PB3" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_B53_SWITCH=y CONFIG_B53_PHY_PORTS=0x1f @@ -26,4 +21,3 @@ CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig index d86d255ff08..04d7b645047 100644 --- a/configs/LicheePi_Zero_defconfig +++ b/configs/LicheePi_Zero_defconfig @@ -1,13 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_V3S=y CONFIG_DRAM_CLK=360 -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_NETDEVICES is not set -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig index 891251ed473..7377debc9be 100644 --- a/configs/Linksprite_pcDuino3_Nano_defconfig +++ b/configs/Linksprite_pcDuino3_Nano_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=408 @@ -10,12 +9,8 @@ CONFIG_SATAPWR="PH2" CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3-nano" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y @@ -24,4 +19,3 @@ CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig index 9444bb50158..ad78152a045 100644 --- a/configs/Linksprite_pcDuino3_defconfig +++ b/configs/Linksprite_pcDuino3_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=480 @@ -8,12 +7,8 @@ CONFIG_DRAM_ZQ=122 CONFIG_SATAPWR="PH2" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y @@ -21,4 +16,3 @@ CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig index f31d29816ee..e5166e9665c 100644 --- a/configs/Linksprite_pcDuino_defconfig +++ b/configs/Linksprite_pcDuino_defconfig @@ -1,19 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_MII=y CONFIG_SUN4I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig index 75b5221230f..b323e3232ce 100644 --- a/configs/MK808C_defconfig +++ b/configs/MK808C_defconfig @@ -1,16 +1,10 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig index 52f6927fc22..69561be71d5 100644 --- a/configs/MSI_Primo73_defconfig +++ b/configs/MSI_Primo73_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 @@ -10,10 +9,5 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-primo73" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig index 3fbd89f4bd6..29c2c682ef5 100644 --- a/configs/MSI_Primo81_defconfig +++ b/configs/MSI_Primo81_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_CLK=360 @@ -13,15 +12,10 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-primo81" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP_DLDO1_VOLT=3300 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y CONFIG_VIDEO_LCD_SSD2828_TX_CLK=27 CONFIG_VIDEO_LCD_SSD2828_RESET="PA26" CONFIG_VIDEO_LCD_SPI_CS="PH9" diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig index b1214e07dc3..be608698c71 100644 --- a/configs/Marsboard_A10_defconfig +++ b/configs/Marsboard_A10_defconfig @@ -1,15 +1,10 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_MII=y CONFIG_SUN4I_EMAC=y @@ -17,4 +12,3 @@ CONFIG_SUNXI_NO_PMIC=y CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig index b9ff12e0f3f..babe9f11e58 100644 --- a/configs/Mele_A1000G_quad_defconfig +++ b/configs/Mele_A1000G_quad_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_ZQ=120 @@ -8,11 +7,7 @@ CONFIG_INITIAL_USB_SCAN_DELAY=2000 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_SUN7I_GMAC=y @@ -23,4 +18,3 @@ CONFIG_AXP_DLDO4_VOLT=3300 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig index c23413eff06..20906ff5f5d 100644 --- a/configs/Mele_A1000_defconfig +++ b/configs/Mele_A1000_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_MACPWR="PH15" @@ -8,16 +7,11 @@ CONFIG_VIDEO_VGA=y CONFIG_VIDEO_COMPOSITE=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_MII=y CONFIG_SUN4I_EMAC=y CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig index b4825f28427..1282d8763ab 100644 --- a/configs/Mele_I7_defconfig +++ b/configs/Mele_I7_defconfig @@ -1,17 +1,12 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_ZQ=120 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-i7" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_SUN7I_GMAC=y @@ -21,4 +16,3 @@ CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_AXP_DLDO4_VOLT=3300 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig index ba1018fce12..60d15ab05b1 100644 --- a/configs/Mele_M3_defconfig +++ b/configs/Mele_M3_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 @@ -9,15 +8,10 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_VIDEO_VGA=y CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_SUN7I_GMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig index f8b71e9c3cf..8900c7a1f12 100644 --- a/configs/Mele_M5_defconfig +++ b/configs/Mele_M5_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 @@ -9,12 +8,8 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_VIDEO_COMPOSITE=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m5" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y @@ -22,4 +17,3 @@ CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig index 4051ade7215..b1b3b7af161 100644 --- a/configs/Mele_M9_defconfig +++ b/configs/Mele_M9_defconfig @@ -1,17 +1,12 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_ZQ=120 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-m9" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_SUN7I_GMAC=y @@ -21,4 +16,3 @@ CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_AXP_DLDO4_VOLT=3300 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig index a691e4869fd..15db3962fe6 100644 --- a/configs/Merrii_A80_Optimus_defconfig +++ b/configs/Merrii_A80_Optimus_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN9I=y CONFIG_DRAM_CLK=672 @@ -12,10 +11,5 @@ CONFIG_USB0_ID_DET="PH3" CONFIG_USB1_VBUS_PIN="PH4" CONFIG_USB3_VBUS_PIN="PH5" CONFIG_AXP_GPIO=y -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP809_POWER=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig index 29e32a42732..30468e16c8c 100644 --- a/configs/Mini-X_defconfig +++ b/configs/Mini-X_defconfig @@ -1,18 +1,12 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_USB0_VBUS_PIN="PB9" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Nintendo_NES_Classic_Edition_defconfig b/configs/Nintendo_NES_Classic_Edition_defconfig index b2e8b83b76e..ba9cc58a544 100644 --- a/configs/Nintendo_NES_Classic_Edition_defconfig +++ b/configs/Nintendo_NES_Classic_Edition_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_A33=y CONFIG_DRAM_CLK=600 @@ -9,13 +8,9 @@ CONFIG_DRAM_ODT_EN=y CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTDPARTS=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-nintendo-nes-classic-edition" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y @@ -26,5 +21,4 @@ CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_AXP_ELDO2_VOLT=1800 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_GADGET=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y CONFIG_USB_FUNCTION_MASS_STORAGE=y diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig index 82545519789..af8c17defb7 100644 --- a/configs/Orangepi_defconfig +++ b/configs/Orangepi_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 @@ -12,12 +11,8 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y @@ -26,4 +21,3 @@ CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig index 0bba89d6061..43ee76fa184 100644 --- a/configs/Orangepi_mini_defconfig +++ b/configs/Orangepi_mini_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 @@ -14,12 +13,8 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y @@ -28,4 +23,3 @@ CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig index d7bd8489929..74fb9e3d0ad 100644 --- a/configs/Sinlinx_SinA31s_defconfig +++ b/configs/Sinlinx_SinA31s_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_CLK=432 @@ -11,15 +10,10 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=3 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sina31s" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_SUN7I_GMAC=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig index c68d8315aa7..9f29870902e 100644 --- a/configs/Sinlinx_SinA33_defconfig +++ b/configs/Sinlinx_SinA33_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_A33=y CONFIG_DRAM_CLK=552 @@ -13,16 +12,12 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_CMD_DFU=y -# CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DFU_RAM=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y CONFIG_USB_FUNCTION_MASS_STORAGE=y diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig index b8a2d477428..b2ecf4ee920 100644 --- a/configs/Sinovoip_BPI_M2_defconfig +++ b/configs/Sinovoip_BPI_M2_defconfig @@ -1,17 +1,12 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sinovoip-bpi-m2" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y CONFIG_MII=y @@ -21,4 +16,3 @@ CONFIG_AXP_ALDO2_VOLT=1800 CONFIG_AXP_DLDO1_VOLT=3000 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig index 6188e69e12f..b1b75bf5a15 100644 --- a/configs/Sinovoip_BPI_M3_defconfig +++ b/configs/Sinovoip_BPI_M3_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_A83T=y CONFIG_DRAM_TYPE=7 @@ -16,12 +15,8 @@ CONFIG_USB1_VBUS_PIN="PD24" CONFIG_AXP_GPIO=y CONFIG_SATAPWR="PD25" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-bananapi-m3" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y CONFIG_AXP_DCDC5_VOLT=1200 @@ -30,4 +25,3 @@ CONFIG_AXP_SW_ON=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Sunchip_CX-A99_defconfig b/configs/Sunchip_CX-A99_defconfig index 5e2ec3fae1b..ca175234e53 100644 --- a/configs/Sunchip_CX-A99_defconfig +++ b/configs/Sunchip_CX-A99_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN9I=y CONFIG_DRAM_CLK=600 @@ -12,9 +11,4 @@ CONFIG_USB0_VBUS_PIN="PH15" CONFIG_USB1_VBUS_PIN="PL7" CONFIG_USB3_VBUS_PIN="PL8" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-cx-a99" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig index a562b09808d..0c18423220e 100644 --- a/configs/UTOO_P66_defconfig +++ b/configs/UTOO_P66_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 @@ -20,13 +19,8 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_TL059WV5C0=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-utoo-p66" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig index 019549df010..2253dd3d982 100644 --- a/configs/Wexler_TAB7200_defconfig +++ b/configs/Wexler_TAB7200_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 @@ -13,13 +12,8 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig index 08cbba2a575..8630f39a5f1 100644 --- a/configs/Wits_Pro_A20_DKT_defconfig +++ b/configs/Wits_Pro_A20_DKT_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 @@ -12,12 +11,8 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wits-pro-a20-dkt" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y @@ -26,4 +21,3 @@ CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig index cc282269439..1cfd6835731 100644 --- a/configs/Wobo_i5_defconfig +++ b/configs/Wobo_i5_defconfig @@ -1,21 +1,15 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 CONFIG_MMC0_CD_PIN="PB3" CONFIG_USB1_VBUS_PIN="PG12" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-wobo-i5" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP_ALDO3_VOLT=3300 CONFIG_AXP_ALDO4_VOLT=3300 CONFIG_CONS_INDEX=2 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig index da8a891bbf7..6fb1a7c186d 100644 --- a/configs/Yones_Toptech_BD1078_defconfig +++ b/configs/Yones_Toptech_BD1078_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=408 @@ -19,11 +18,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig index 6fd09205589..a44207e3343 100644 --- a/configs/Yones_Toptech_BS1078_V2_defconfig +++ b/configs/Yones_Toptech_BS1078_V2_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_CLK=420 @@ -16,11 +15,6 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-yones-toptech-bs1078-v2" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/a64-olinuxino-emmc_defconfig b/configs/a64-olinuxino-emmc_defconfig index 8443a6dae9e..d2618d5e577 100644 --- a/configs/a64-olinuxino-emmc_defconfig +++ b/configs/a64-olinuxino-emmc_defconfig @@ -1,17 +1,11 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-olinuxino-emmc" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig index 1ba59cc21b7..27243610ca0 100644 --- a/configs/a64-olinuxino_defconfig +++ b/configs/a64-olinuxino_defconfig @@ -1,17 +1,11 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-olinuxino" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig index e31e21bbfbf..9567d676ca8 100644 --- a/configs/amarula_a64_relic_defconfig +++ b/configs/amarula_a64_relic_defconfig @@ -1,18 +1,12 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig index 18b880ea39c..df196469ae3 100644 --- a/configs/ba10_tv_box_defconfig +++ b/configs/ba10_tv_box_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=384 @@ -9,15 +8,10 @@ CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB2_VBUS_PIN="PH12" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_MII=y CONFIG_SUN4I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/bananapi_m1_plus_defconfig b/configs/bananapi_m1_plus_defconfig index be61a82012f..3813b6e89ad 100644 --- a/configs/bananapi_m1_plus_defconfig +++ b/configs/bananapi_m1_plus_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 @@ -9,12 +8,8 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi-m1-plus" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig index 9b028783a15..256d9fc06c1 100644 --- a/configs/bananapi_m2_berry_defconfig +++ b/configs/bananapi_m2_berry_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_R40=y CONFIG_DRAM_CLK=576 @@ -8,10 +7,8 @@ CONFIG_MMC0_CD_PIN="PH13" CONFIG_USB1_VBUS_PIN="PH23" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-v40-bananapi-m2-berry" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_RGMII=y CONFIG_SUN8I_EMAC=y @@ -20,4 +17,3 @@ CONFIG_AXP_ELDO3_VOLT=1200 CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/bananapi_m2_plus_h3_defconfig b/configs/bananapi_m2_plus_h3_defconfig index d5161254608..21c6aa6b66e 100644 --- a/configs/bananapi_m2_plus_h3_defconfig +++ b/configs/bananapi_m2_plus_h3_defconfig @@ -1,19 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-bananapi-m2-plus" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/bananapi_m2_plus_h5_defconfig b/configs/bananapi_m2_plus_h5_defconfig index 94d18cebe95..afed137243e 100644 --- a/configs/bananapi_m2_plus_h5_defconfig +++ b/configs/bananapi_m2_plus_h5_defconfig @@ -1,19 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=672 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-bananapi-m2-plus" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/bananapi_m2_zero_defconfig b/configs/bananapi_m2_zero_defconfig index cecea59c687..f95c7faf7ef 100644 --- a/configs/bananapi_m2_zero_defconfig +++ b/configs/bananapi_m2_zero_defconfig @@ -5,8 +5,4 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 CONFIG_MMC0_CD_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-bananapi-m2-zero" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/bananapi_m64_defconfig b/configs/bananapi_m64_defconfig index c26fd0c5813..7f31cf00553 100644 --- a/configs/bananapi_m64_defconfig +++ b/configs/bananapi_m64_defconfig @@ -1,19 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-bananapi-m64" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig index 818931465e0..42e38975c08 100644 --- a/configs/beelink_gs1_defconfig +++ b/configs/beelink_gs1_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H6=y CONFIG_SUNXI_DRAM_H6_LPDDR3=y @@ -8,11 +7,7 @@ CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-beelink-gs1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/beelink_x2_defconfig b/configs/beelink_x2_defconfig index d314cfa1700..7aca82cbd87 100644 --- a/configs/beelink_x2_defconfig +++ b/configs/beelink_x2_defconfig @@ -5,11 +5,6 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=567 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-beelink-x2" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig index 82bf8b4c53b..e0bcaf35086 100644 --- a/configs/colorfly_e708_q1_defconfig +++ b/configs/colorfly_e708_q1_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_CLK=432 @@ -16,12 +15,7 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-colorfly-e708-q1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_AXP_DLDO2_VOLT=1800 CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig index c9cccd6d6f3..12088d4d9ea 100644 --- a/configs/difrnce_dit4350_defconfig +++ b/configs/difrnce_dit4350_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=408 @@ -15,12 +14,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-difrnce-dit4350" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig index 80c1d24b149..a19b89024eb 100644 --- a/configs/dserve_dsrv9703c_defconfig +++ b/configs/dserve_dsrv9703c_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_MMC0_CD_PIN="PH1" @@ -14,11 +13,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-dserve-dsrv9703c" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/emlid_neutis_n5_devboard_defconfig b/configs/emlid_neutis_n5_devboard_defconfig index 9b106ab40f5..2a2392c4136 100644 --- a/configs/emlid_neutis_n5_devboard_defconfig +++ b/configs/emlid_neutis_n5_devboard_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=408 @@ -8,8 +7,4 @@ CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-emlid-neutis-n5-devboard" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig index 954e73c51de..0b7af23551a 100644 --- a/configs/ga10h_v1_1_defconfig +++ b/configs/ga10h_v1_1_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_A33=y CONFIG_DRAM_CLK=432 @@ -17,14 +16,9 @@ CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ga10h-v1.1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig index 53098762ded..dd64241745a 100644 --- a/configs/gt90h_v4_defconfig +++ b/configs/gt90h_v4_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_A23=y CONFIG_DRAM_CLK=480 @@ -16,12 +15,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-gt90h-v4" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig index fb18004b68e..c6246c8e815 100644 --- a/configs/h8_homlet_v2_defconfig +++ b/configs/h8_homlet_v2_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_A83T=y CONFIG_DRAM_CLK=480 @@ -10,14 +9,9 @@ CONFIG_USB0_VBUS_PIN="PL5" CONFIG_USB1_VBUS_PIN="PL6" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-allwinner-h8homlet-v2" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP_DLDO4_VOLT=3300 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig index b15c9de0541..8543780a7d5 100644 --- a/configs/i12-tvbox_defconfig +++ b/configs/i12-tvbox_defconfig @@ -1,21 +1,15 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 CONFIG_MACPWR="PH21" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_SUN7I_GMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig index d4f256f899c..8bd104a5fb7 100644 --- a/configs/iNet_3F_defconfig +++ b/configs/iNet_3F_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=432 @@ -14,11 +13,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3f" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig index 3bafd4c8962..d996075510c 100644 --- a/configs/iNet_3W_defconfig +++ b/configs/iNet_3W_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=408 @@ -14,11 +13,6 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3w" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig index 771cdfa3c98..16d08448d0a 100644 --- a/configs/iNet_86VS_defconfig +++ b/configs/iNet_86VS_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=408 @@ -13,12 +12,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-86vs" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/iNet_D978_rev2_defconfig b/configs/iNet_D978_rev2_defconfig index 598465d93ee..ff271f343ec 100644 --- a/configs/iNet_D978_rev2_defconfig +++ b/configs/iNet_D978_rev2_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_A33=y CONFIG_DRAM_CLK=456 @@ -17,13 +16,8 @@ CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-inet-d978-rev2" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP_DLDO1_VOLT=3300 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig index f9b8c73da2d..d6da5acd5ee 100644 --- a/configs/icnova-a20-swac_defconfig +++ b/configs/icnova-a20-swac_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 @@ -13,16 +12,11 @@ CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo CONFIG_VIDEO_LCD_POWER="PH22" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_UNZIP=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-icnova-swac" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_SUN7I_GMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig index 293a7476caa..ca898c25a83 100644 --- a/configs/inet1_defconfig +++ b/configs/inet1_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=432 @@ -14,13 +13,8 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/inet86dz_defconfig b/configs/inet86dz_defconfig index 0fdcf2b9d6d..dbe32c1c329 100644 --- a/configs/inet86dz_defconfig +++ b/configs/inet86dz_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_A23=y CONFIG_DRAM_CLK=552 @@ -16,12 +15,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-inet86dz" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig index 7bf1439d83d..4490e2fe387 100644 --- a/configs/inet97fv2_defconfig +++ b/configs/inet97fv2_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=408 @@ -13,11 +12,6 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet97fv2" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig index cc8602be624..d36bb75f778 100644 --- a/configs/inet98v_rev2_defconfig +++ b/configs/inet98v_rev2_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 @@ -15,12 +14,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-98v-rev2" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig index 2837f065ef6..0c53a1210a1 100644 --- a/configs/inet9f_rev03_defconfig +++ b/configs/inet9f_rev03_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=408 @@ -13,11 +12,6 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet9f-rev03" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/inet_q972_defconfig b/configs/inet_q972_defconfig index 280158f81b9..83dc7f89988 100644 --- a/configs/inet_q972_defconfig +++ b/configs/inet_q972_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_CLK=384 @@ -15,13 +14,8 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-inet-q972" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig index 7be441837b4..06357ed7b44 100644 --- a/configs/jesurun_q5_defconfig +++ b/configs/jesurun_q5_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=312 @@ -8,15 +7,10 @@ CONFIG_MACPWR="PH19" CONFIG_USB0_VBUS_PIN="PB9" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_MII=y CONFIG_SUN4I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/libretech_all_h3_cc_h2_plus_defconfig b/configs/libretech_all_h3_cc_h2_plus_defconfig index f648b7d516b..c9a1708ebd3 100644 --- a/configs/libretech_all_h3_cc_h2_plus_defconfig +++ b/configs/libretech_all_h3_cc_h2_plus_defconfig @@ -1,17 +1,11 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-libretech-all-h3-cc" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/libretech_all_h3_cc_h3_defconfig b/configs/libretech_all_h3_cc_h3_defconfig index c39a1168509..71751238726 100644 --- a/configs/libretech_all_h3_cc_h3_defconfig +++ b/configs/libretech_all_h3_cc_h3_defconfig @@ -1,17 +1,11 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-libretech-all-h3-cc" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/libretech_all_h3_cc_h5_defconfig b/configs/libretech_all_h3_cc_h5_defconfig index aac3d0626a4..b70b13f4250 100644 --- a/configs/libretech_all_h3_cc_h5_defconfig +++ b/configs/libretech_all_h3_cc_h5_defconfig @@ -1,17 +1,11 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-libretech-all-h3-cc" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/libretech_all_h3_it_h5_defconfig b/configs/libretech_all_h3_it_h5_defconfig index 76cee85c96f..159eb38d700 100644 --- a/configs/libretech_all_h3_it_h5_defconfig +++ b/configs/libretech_all_h3_it_h5_defconfig @@ -1,21 +1,15 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-libretech-all-h3-it" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_XMC=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/libretech_all_h5_cc_h5_defconfig b/configs/libretech_all_h5_cc_h5_defconfig index 9ccb29d0766..ddbd1b51c4b 100644 --- a/configs/libretech_all_h5_cc_h5_defconfig +++ b/configs/libretech_all_h5_cc_h5_defconfig @@ -1,17 +1,12 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-libretech-all-h5-cc" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_XMC=y CONFIG_SUN8I_EMAC=y @@ -19,4 +14,3 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig index 620dac67746..829491fa8e6 100644 --- a/configs/mixtile_loftq_defconfig +++ b/configs/mixtile_loftq_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_ZQ=251 @@ -9,11 +8,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PH24" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y CONFIG_MII=y @@ -21,4 +16,3 @@ CONFIG_SUN7I_GMAC=y CONFIG_AXP_ALDO1_VOLT=3300 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig index cf6b11a451b..3ffbef09ea0 100644 --- a/configs/mk802_a10s_defconfig +++ b/configs/mk802_a10s_defconfig @@ -1,20 +1,14 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 CONFIG_DRAM_EMR1=0 CONFIG_USB1_VBUS_PIN="PB10" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-mk802" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP152_POWER=y CONFIG_CONS_INDEX=2 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig index 472758cb04d..077c21f4224 100644 --- a/configs/mk802_defconfig +++ b/configs/mk802_defconfig @@ -1,16 +1,10 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_USB2_VBUS_PIN="PH12" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUNXI_NO_PMIC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig index ec76622966f..17042afdcd4 100644 --- a/configs/mk802ii_defconfig +++ b/configs/mk802ii_defconfig @@ -1,15 +1,9 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/nanopi_a64_defconfig b/configs/nanopi_a64_defconfig index dedb389d3d9..0d46b332b1f 100644 --- a/configs/nanopi_a64_defconfig +++ b/configs/nanopi_a64_defconfig @@ -1,16 +1,10 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-nanopi-a64" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/nanopi_m1_defconfig b/configs/nanopi_m1_defconfig index 00f8678f539..2b55853bcaf 100644 --- a/configs/nanopi_m1_defconfig +++ b/configs/nanopi_m1_defconfig @@ -1,15 +1,9 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig index b3e14605112..398fd9969af 100644 --- a/configs/nanopi_m1_plus_defconfig +++ b/configs/nanopi_m1_plus_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 @@ -8,12 +7,7 @@ CONFIG_MACPWR="PD6" CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1-plus" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig index cbac2a9ff4b..753a305356f 100644 --- a/configs/nanopi_neo2_defconfig +++ b/configs/nanopi_neo2_defconfig @@ -1,18 +1,12 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo2" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig index 01bf61d4c6b..baaccf145e2 100644 --- a/configs/nanopi_neo_air_defconfig +++ b/configs/nanopi_neo_air_defconfig @@ -1,17 +1,11 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo-air" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig index a29922d6983..d115d84ba9c 100644 --- a/configs/nanopi_neo_defconfig +++ b/configs/nanopi_neo_defconfig @@ -1,18 +1,12 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig index 65f971eb36b..a852388edf4 100644 --- a/configs/nanopi_neo_plus2_defconfig +++ b/configs/nanopi_neo_plus2_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=408 @@ -9,11 +8,7 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo-plus2" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/oceanic_5205_5inmfd_defconfig b/configs/oceanic_5205_5inmfd_defconfig index f71be7f1273..5ce0693480c 100644 --- a/configs/oceanic_5205_5inmfd_defconfig +++ b/configs/oceanic_5205_5inmfd_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y @@ -10,12 +9,7 @@ CONFIG_DRAM_ZQ=3881949 CONFIG_MMC0_CD_PIN="" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-oceanic-5205-5inmfd" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig index 6c02949c863..ba161e56650 100644 --- a/configs/orangepi_2_defconfig +++ b/configs/orangepi_2_defconfig @@ -1,20 +1,14 @@ CONFIG_ARM=y # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-2" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_lite2_defconfig b/configs/orangepi_lite2_defconfig index c0826c09461..35ebf38300e 100644 --- a/configs/orangepi_lite2_defconfig +++ b/configs/orangepi_lite2_defconfig @@ -1,16 +1,11 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H6=y CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC0_CD_PIN="PF6" # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-lite2" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig index f6319023a20..51afd7f0653 100644 --- a/configs/orangepi_lite_defconfig +++ b/configs/orangepi_lite_defconfig @@ -1,15 +1,9 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-lite" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig index ea74e22451e..75bccd03b99 100644 --- a/configs/orangepi_one_defconfig +++ b/configs/orangepi_one_defconfig @@ -1,16 +1,10 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_one_plus_defconfig b/configs/orangepi_one_plus_defconfig index 5e8117c50d4..d97b2172dec 100644 --- a/configs/orangepi_one_plus_defconfig +++ b/configs/orangepi_one_plus_defconfig @@ -1,16 +1,11 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H6=y CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC0_CD_PIN="PF6" # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-one-plus" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig index 20209ec41b9..8cb3b2b7bda 100644 --- a/configs/orangepi_pc2_defconfig +++ b/configs/orangepi_pc2_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=672 @@ -9,13 +8,8 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MACPWR="PD6" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-pc2" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig index 216b4e8733c..a676294a8bd 100644 --- a/configs/orangepi_pc_defconfig +++ b/configs/orangepi_pc_defconfig @@ -1,18 +1,12 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=624 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_pc_plus_defconfig b/configs/orangepi_pc_plus_defconfig index edd2db13208..97221f71558 100644 --- a/configs/orangepi_pc_plus_defconfig +++ b/configs/orangepi_pc_plus_defconfig @@ -1,19 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=624 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc-plus" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig index 8eba1c394bf..72862f22766 100644 --- a/configs/orangepi_plus2e_defconfig +++ b/configs/orangepi_plus2e_defconfig @@ -1,20 +1,14 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus2e" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig index 48e5140dc86..025b9f69c55 100644 --- a/configs/orangepi_plus_defconfig +++ b/configs/orangepi_plus_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 @@ -9,14 +8,9 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PG13" CONFIG_SATAPWR="PG11" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig index 5f671230ddf..fa7672a23ea 100644 --- a/configs/orangepi_prime_defconfig +++ b/configs/orangepi_prime_defconfig @@ -1,19 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-prime" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_r1_defconfig b/configs/orangepi_r1_defconfig index 0431fecb523..6f770fa018a 100644 --- a/configs/orangepi_r1_defconfig +++ b/configs/orangepi_r1_defconfig @@ -1,17 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=624 # CONFIG_VIDEO_DE2 is not set CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-r1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig index bcf74580b5d..047a6b7d846 100644 --- a/configs/orangepi_win_defconfig +++ b/configs/orangepi_win_defconfig @@ -1,19 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MACPWR="PD14" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig index 51d8ec001e3..c989f0dcf7a 100644 --- a/configs/orangepi_zero_defconfig +++ b/configs/orangepi_zero_defconfig @@ -1,17 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=624 # CONFIG_VIDEO_DE2 is not set CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_zero_plus2_defconfig b/configs/orangepi_zero_plus2_defconfig index 3d560241d5a..a38c9beb3ec 100644 --- a/configs/orangepi_zero_plus2_defconfig +++ b/configs/orangepi_zero_plus2_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=672 @@ -9,12 +8,7 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-zero-plus2" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_zero_plus2_h3_defconfig b/configs/orangepi_zero_plus2_h3_defconfig index d40f4f2006e..6b50ff9ca0d 100644 --- a/configs/orangepi_zero_plus2_h3_defconfig +++ b/configs/orangepi_zero_plus2_h3_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 @@ -8,11 +7,7 @@ CONFIG_DRAM_CLK=672 CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-zero-plus2" CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_zero_plus_defconfig b/configs/orangepi_zero_plus_defconfig index 22ffbdf2e89..77c7bdb25a5 100644 --- a/configs/orangepi_zero_plus_defconfig +++ b/configs/orangepi_zero_plus_defconfig @@ -1,18 +1,12 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=624 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-zero-plus" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/parrot_r16_defconfig b/configs/parrot_r16_defconfig index 08163bbe791..2c2edbc2b6d 100644 --- a/configs/parrot_r16_defconfig +++ b/configs/parrot_r16_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_A33=y CONFIG_DRAM_CLK=600 @@ -12,15 +11,11 @@ CONFIG_USB0_ID_DET="PD10" CONFIG_USB1_VBUS_PIN="PD12" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-parrot" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_CONS_INDEX=5 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y CONFIG_USB_FUNCTION_MASS_STORAGE=y diff --git a/configs/pine64-lts_defconfig b/configs/pine64-lts_defconfig index 6e2c247c1a4..ef108a1a318 100644 --- a/configs/pine64-lts_defconfig +++ b/configs/pine64-lts_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I=y CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y @@ -10,12 +9,7 @@ CONFIG_MMC0_CD_PIN="" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-lts" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig index 9c347881cc7..a03757704a8 100644 --- a/configs/pine64_plus_defconfig +++ b/configs/pine64_plus_defconfig @@ -1,20 +1,14 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_PINE64_DT_SELECTION=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus" CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_PHY_REALTEK=y CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index c0adbf3dd0f..cb5e624a3d6 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H6=y CONFIG_SUNXI_DRAM_H6_LPDDR3=y @@ -9,11 +8,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB3_VBUS_PIN="PL5" # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_SPL_SPI_SUNXI=y diff --git a/configs/pinebook_defconfig b/configs/pinebook_defconfig index 929434e25a4..43df3f3c82e 100644 --- a/configs/pinebook_defconfig +++ b/configs/pinebook_defconfig @@ -7,18 +7,13 @@ CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_R_I2C_ENABLE=y -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinebook" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_PWM=y CONFIG_PWM_SUNXI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y # CONFIG_USB_GADGET is not set CONFIG_VIDEO_BRIDGE=y CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345=y diff --git a/configs/polaroid_mid2407pxe03_defconfig b/configs/polaroid_mid2407pxe03_defconfig index c3c7855c4d3..712451a14b3 100644 --- a/configs/polaroid_mid2407pxe03_defconfig +++ b/configs/polaroid_mid2407pxe03_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_A23=y CONFIG_DRAM_CLK=432 @@ -16,12 +15,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-polaroid-mid2407pxe03" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig index a6f519ea6e8..2aaf784988c 100644 --- a/configs/polaroid_mid2809pxe04_defconfig +++ b/configs/polaroid_mid2809pxe04_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_A23=y CONFIG_DRAM_CLK=432 @@ -16,12 +15,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-polaroid-mid2809pxe04" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig index b002edb8c68..f21ae9d42bc 100644 --- a/configs/pov_protab2_ips9_defconfig +++ b/configs/pov_protab2_ips9_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=432 @@ -14,11 +13,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pov-protab2-ips9" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig index eb650201176..f07d136a7fe 100644 --- a/configs/q8_a13_tablet_defconfig +++ b/configs/q8_a13_tablet_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=384 @@ -15,12 +14,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-q8-tablet" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig index f2c2248a8a7..05a76044364 100644 --- a/configs/q8_a23_tablet_800x480_defconfig +++ b/configs/q8_a23_tablet_800x480_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_A23=y CONFIG_DRAM_CLK=432 @@ -16,12 +15,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-q8-tablet" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig index 803c46e0045..1c88e5fe0e9 100644 --- a/configs/q8_a33_tablet_1024x600_defconfig +++ b/configs/q8_a33_tablet_1024x600_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_A33=y CONFIG_DRAM_CLK=456 @@ -16,12 +15,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig index 20450ebc9e8..581117a92a8 100644 --- a/configs/q8_a33_tablet_800x480_defconfig +++ b/configs/q8_a33_tablet_800x480_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_A33=y CONFIG_DRAM_CLK=456 @@ -16,12 +15,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig index 1317d8749e4..057f29b6d2a 100644 --- a/configs/r7-tv-dongle_defconfig +++ b/configs/r7-tv-dongle_defconfig @@ -1,19 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=384 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-r7-tv-dongle" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AXP152_POWER=y CONFIG_CONS_INDEX=2 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig index 87ed55264d5..98278bbc732 100644 --- a/configs/sopine_baseboard_defconfig +++ b/configs/sopine_baseboard_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y @@ -11,13 +10,8 @@ CONFIG_MMC0_CD_PIN="" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-sopine-baseboard" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/sun8i_a23_evb_defconfig b/configs/sun8i_a23_evb_defconfig index eba05cfff20..1045caf47ad 100644 --- a/configs/sun8i_a23_evb_defconfig +++ b/configs/sun8i_a23_evb_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_A23=y CONFIG_DRAM_CLK=552 @@ -9,12 +8,7 @@ CONFIG_USB0_VBUS_PIN="axp_drivebus" CONFIG_USB0_VBUS_DET="axp_vbus_detect" CONFIG_USB1_VBUS_PIN="PH7" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-evb" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_CONS_INDEX=5 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig index 5d10532703c..427a29caec6 100644 --- a/configs/sunxi_Gemei_G9_defconfig +++ b/configs/sunxi_Gemei_G9_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=432 @@ -11,12 +10,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-gemei-g9" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/tbs_a711_defconfig b/configs/tbs_a711_defconfig index a961e6baaf0..509a87d41ef 100644 --- a/configs/tbs_a711_defconfig +++ b/configs/tbs_a711_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_A83T=y CONFIG_DRAM_TYPE=7 @@ -13,11 +12,7 @@ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH11" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-tbs-a711" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_AXP_DCDC5_VOLT=1200 CONFIG_USB_EHCI_HCD=y diff --git a/configs/teres_i_defconfig b/configs/teres_i_defconfig index 1019dab54a4..1eba20e5f5d 100644 --- a/configs/teres_i_defconfig +++ b/configs/teres_i_defconfig @@ -7,17 +7,12 @@ CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PL7" CONFIG_I2C0_ENABLE=y -CONFIG_USE_PREBOOT=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-teres-i" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_PWM=y CONFIG_PWM_SUNXI=y CONFIG_USB_EHCI_HCD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y # CONFIG_USB_GADGET is not set CONFIG_VIDEO_BRIDGE=y CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345=y -- cgit v1.2.3 From 5721df32a37acb04c380a4f1d564f40f0b236e60 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sat, 28 Mar 2020 10:41:20 +0100 Subject: test/py: UEFI helloworld requires OF_CONTROL With CONFIG_OF_CONTROL environment variable $fdtcontroladdr is not defined and test_efi_helloworld_net() fails. Signed-off-by: Heinrich Schuchardt --- test/py/tests/test_efi_loader.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/test/py/tests/test_efi_loader.py b/test/py/tests/test_efi_loader.py index adf9d774529..e105645484f 100644 --- a/test/py/tests/test_efi_loader.py +++ b/test/py/tests/test_efi_loader.py @@ -141,12 +141,13 @@ def fetch_tftp_file(u_boot_console, env_conf): return addr +@pytest.mark.buildconfigspec('of_control') @pytest.mark.buildconfigspec('cmd_bootefi_hello_compile') def test_efi_helloworld_net(u_boot_console): """Run the helloworld.efi binary via TFTP. - The helloworld.efi file is downloaded from the TFTP server and gets - executed. + The helloworld.efi file is downloaded from the TFTP server and is executed + using the fallback device tree at $fdtcontroladdr. """ addr = fetch_tftp_file(u_boot_console, 'env__efi_loader_helloworld_file') -- cgit v1.2.3 From 6c0ef35cdc3164fda9c7ddd15db58793b1bd3263 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Fri, 27 Mar 2020 04:33:17 +0000 Subject: cmd: efidebug: fix int to pointer cast On 32 bit systems fix warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Fixes: a415d61eac26 ("cmd: map addresses to sysmem in efidebug memmap") Signed-off-by: Heinrich Schuchardt --- cmd/efidebug.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/cmd/efidebug.c b/cmd/efidebug.c index bb7c13d6a1c..c1bb76477a6 100644 --- a/cmd/efidebug.c +++ b/cmd/efidebug.c @@ -489,10 +489,12 @@ static int do_efi_show_memmap(cmd_tbl_t *cmdtp, int flag, printf("%-16s %.*llx-%.*llx", type, EFI_PHYS_ADDR_WIDTH, - (u64)map_to_sysmem((void *)map->physical_start), + (u64)map_to_sysmem((void *)(uintptr_t) + map->physical_start), EFI_PHYS_ADDR_WIDTH, - (u64)map_to_sysmem((void *)map->physical_start + - map->num_pages * EFI_PAGE_SIZE)); + (u64)map_to_sysmem((void *)(uintptr_t) + (map->physical_start + + map->num_pages * EFI_PAGE_SIZE))); print_memory_attributes(map->attribute); putc('\n'); -- cgit v1.2.3 From 4ef2b0d5512857c1af1110a0b23744c00a585cb2 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 24 Mar 2020 07:37:52 +0100 Subject: efi_loader: only reserve memory if fdt node enabled Sub-nodes of /reserved-memory may be disabled. In this case we should not reserve memory in the memory map. Reported-by: Patrick DELAUNAY Fixes: fef907b2e440 ("efi_loader: create reservations after ft_board_setup") Signed-off-by: Heinrich Schuchardt Reviewed-by: Atish Patra --- cmd/bootefi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 3bbe2d6a1a4..aaed5755059 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -199,7 +199,8 @@ static void efi_carve_out_dt_rsv(void *fdt) * The /reserved-memory node may have children with * a size instead of a reg property. */ - if (addr != FDT_ADDR_T_NONE) + if (addr != FDT_ADDR_T_NONE && + fdtdec_get_is_enabled(fdt, subnode)) efi_reserve_memory(addr, size); subnode = fdt_next_subnode(fdt, subnode); } -- cgit v1.2.3 From d4babee087f24a60d910659cb4367a077bad87a0 Mon Sep 17 00:00:00 2001 From: Kristian Amlie Date: Tue, 25 Feb 2020 18:22:16 +0100 Subject: vexpress_ca9x4: Enable use of correct DTB file and restore EFI loader. EFI was disabled in f95b8a4b5f64f because of the missing DTB file, and indeed, the DTB file is required to load recent versions of GRUB (2.04) correctly. Signed-off-by: Kristian Amlie --- configs/vexpress_ca9x4_defconfig | 2 +- include/configs/vexpress_common.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig index 2119df6b10e..6bd1f253b6a 100644 --- a/configs/vexpress_ca9x4_defconfig +++ b/configs/vexpress_ca9x4_defconfig @@ -34,4 +34,4 @@ CONFIG_SMC911X_32_BIT=y CONFIG_BAUDRATE=38400 CONFIG_CONS_INDEX=0 CONFIG_OF_LIBFDT=y -# CONFIG_EFI_LOADER is not set +CONFIG_DEFAULT_FDT_FILE="vexpress-v2p-ca9.dtb" diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 7f215a67077..e73658a9e6e 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -207,7 +207,8 @@ "devtmpfs.mount=0 vmalloc=256M\0" \ "bootflash=run flashargs; " \ "cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \ - "bootm ${kernel_addr} ${ramdisk_addr_r}\0" + "bootm ${kernel_addr} ${ramdisk_addr_r}\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" /* FLASH and environment organization */ #define PHYS_FLASH_SIZE 0x04000000 /* 64MB */ -- cgit v1.2.3 From b8c0d4cc6655327a6998043ed0ee27d235625922 Mon Sep 17 00:00:00 2001 From: Petr Štetiar Date: Sat, 28 Mar 2020 20:08:33 +0530 Subject: configs: a64-olinuxino-emmc: add eMMC boot part config commands mmc bootbus and partconf commands are needed in order to be able to configure booting from separate boot0/boot1 eMMC partitions. Signed-off-by: Petr Štetiar [jagan: rebase on master] Signed-off-by: Jagan Teki --- configs/a64-olinuxino-emmc_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/a64-olinuxino-emmc_defconfig b/configs/a64-olinuxino-emmc_defconfig index d2618d5e577..08687cb61a0 100644 --- a/configs/a64-olinuxino-emmc_defconfig +++ b/configs/a64-olinuxino-emmc_defconfig @@ -7,5 +7,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-olinuxino-emmc" CONFIG_SUN8I_EMAC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -- cgit v1.2.3 From f455d78a197d7d30b0ffe2c5a94878d9e3abc782 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 1 Dec 2019 02:33:40 +0100 Subject: ARM: rmobile: Convert Gen2 Blanche to DM_SPI{,_FLASH} Enable DM_SPI and DM_SPI_FLASH in U-Boot on V2H Blanche. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- configs/blanche_defconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig index 5c7b517e7c8..64b7bccfb45 100644 --- a/configs/blanche_defconfig +++ b/configs/blanche_defconfig @@ -24,7 +24,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_SDRAM=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y @@ -53,7 +52,7 @@ CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SMC911X=y CONFIG_SMC911X_BASE=0x18000000 @@ -68,6 +67,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_SH_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y -- cgit v1.2.3 From 061ef41fcf7744a56e0778f16e390fc8323e3383 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 21 Mar 2020 16:45:29 +0100 Subject: clk: renesas: Switch to fdtdec_get_addr_size_auto_noparent() on Gen2 The fdtdec_get_addr() does not take into account values set in #address-cells and #size-cells , but assumes them to be 1 for 32bit systems and 2 for 64bit systems. This is true for most DTs, however there are exceptions. Switch to fdtdec_get_addr_size_auto_noparent(), which takes the #address/size-cells values into consideration, otherwise the reset controller node register offset is incorrectly parsed. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- drivers/clk/renesas/clk-rcar-gen2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c index 13111b341af..bfd7620dae1 100644 --- a/drivers/clk/renesas/clk-rcar-gen2.c +++ b/drivers/clk/renesas/clk-rcar-gen2.c @@ -291,7 +291,8 @@ int gen2_clk_probe(struct udevice *dev) if (ret < 0) return ret; - rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg"); + rst_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, ret, "reg", + 0, NULL, false); if (rst_base == FDT_ADDR_T_NONE) return -EINVAL; -- cgit v1.2.3 From fd2657314f6e06c7713967e380b5951abca86f6f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 21 Mar 2020 16:57:38 +0100 Subject: ARM: dts: rmobile: Add IIC3 node on Gen2 R8A7792 V2H Add IIC3 node from mainline Linux DT. This will be further updated in subsequent DT sync, however adding this node for now is sufficient and minimal change. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/dts/r8a7792.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/dts/r8a7792.dtsi b/arch/arm/dts/r8a7792.dtsi index 8e9eb4b704d..6fd80e35415 100644 --- a/arch/arm/dts/r8a7792.dtsi +++ b/arch/arm/dts/r8a7792.dtsi @@ -444,6 +444,23 @@ status = "disabled"; }; + iic3: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7792", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a7792", "renesas,rcar-dmac"; -- cgit v1.2.3 From 9cf09c799a389c07d26104bb6ca2079dcc835f37 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 21 Mar 2020 16:57:50 +0100 Subject: ARM: dts: rmobile: Enable IIC3 on V2H Blanche Enable IIC3 to permit access to the PMIC. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/dts/r8a7792-blanche-u-boot.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/r8a7792-blanche-u-boot.dts b/arch/arm/dts/r8a7792-blanche-u-boot.dts index 3555663d647..30b27040f5a 100644 --- a/arch/arm/dts/r8a7792-blanche-u-boot.dts +++ b/arch/arm/dts/r8a7792-blanche-u-boot.dts @@ -8,6 +8,10 @@ #include "r8a7792-blanche.dts" #include "r8a7792-u-boot.dtsi" +&iic3 { + status = "okay"; +}; + &scif0 { u-boot,dm-pre-reloc; }; -- cgit v1.2.3 From c463eeb4b61308a3998726a3d063019184d1ab3e Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Mon, 3 Feb 2020 15:25:19 +0800 Subject: ls1021a: Set CONFIG_SYS_BOOTMAPSZ to the memory for relocation This patch sets CONFIG_SYS_BOOTMAPSZ to the amount of memory available to safely contain a kernel, device tree and initrd for relocation. The way to set fdt_high as 0xffffffff to disable device tree relocation is removed. Signed-off-by: Alison Wang Reviewed-by: Tom Rini Reviewed-by: Priyanka Jain --- include/configs/ls1021aiot.h | 5 +++-- include/configs/ls1021aqds.h | 3 +-- include/configs/ls1021atsn.h | 3 ++- include/configs/ls1021atwr.h | 3 +-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 1d218aa703d..7821e98a270 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -207,12 +207,13 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ -"initrd_high=0xffffffff\0" \ -"fdt_high=0xffffffff\0" +"initrd_high=0xffffffff\0" /* * Miscellaneous configurable options */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) + #define CONFIG_CMD_GREPENV #define CONFIG_CMD_MEMINFO diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 8bac2d25612..5a2bd754c4f 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -460,13 +460,11 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_LPUART #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ - "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" #else #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ - "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" #endif @@ -474,6 +472,7 @@ unsigned long get_board_ddr_clk(void); /* * Miscellaneous configurable options */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 984df6249f9..46c60aaf5cb 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -154,7 +154,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "initrd_high=0xffffffff\0" \ - "fdt_high=0xffffffff\0" \ "fdt_addr=0x64f00000\0" \ "kernel_addr=0x61000000\0" \ "kernelheader_addr=0x60800000\0" \ @@ -216,6 +215,8 @@ "bootm $load_addr#$board\0" /* Miscellaneous configurable options */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) + #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE \ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 8e2784b14bf..6a6cdd19cca 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -299,7 +299,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ "initrd_high=0xffffffff\0" \ - "fdt_high=0xffffffff\0" \ "fdt_addr=0x64f00000\0" \ "kernel_addr=0x65000000\0" \ "scriptaddr=0x80000000\0" \ @@ -357,7 +356,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "initrd_high=0xffffffff\0" \ - "fdt_high=0xffffffff\0" \ "fdt_addr=0x64f00000\0" \ "kernel_addr=0x61000000\0" \ "kernelheader_addr=0x60800000\0" \ @@ -441,6 +439,7 @@ /* * Miscellaneous configurable options */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff -- cgit v1.2.3 From 297d48857ac72c0ae303210e03e31b2e23bc7a93 Mon Sep 17 00:00:00 2001 From: Vikas Singh Date: Wed, 12 Feb 2020 13:47:09 +0530 Subject: board: lx2160a: Correct board fixup for PCIe nodes Update "board_fix_fdt" with correct counter value "i". This will fix the issue while fetching the "reg_names" resource from fdt after fixup. Signed-off-by: Vikas Singh Reviewed-by: Priyanka Jain --- board/freescale/lx2160a/lx2160a.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 103b0cc6591..cdacbbd43ba 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -149,6 +149,7 @@ int board_fix_fdt(void *fdt) reg_name = reg_names; remaining_names_len = names_len - (reg_name - reg_names); + i = 0; while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) { old_name_len = strlen(reg_names_map[i].old_str); new_name_len = strlen(reg_names_map[i].new_str); -- cgit v1.2.3 From a4625d494bf5972746ea6bddcc2c72915fb7c815 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Fri, 14 Feb 2020 11:04:34 +0530 Subject: board: fsl: lx2160a: Program GIC LPI configuration table Program GIC LPI configuration table: 1. Redistributor PROCBASER configuration table (which is common for all redistributors) 2. Redistributor pending table (PENDBASER), for all the available redistributors. Signed-off-by: Manish Tomar Signed-off-by: Wasim Khan Reviewed-by: Priyanka Jain --- board/freescale/lx2160a/lx2160a.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index cdacbbd43ba..7ccd2483fb4 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -29,11 +29,14 @@ #include "../common/vid.h" #include #include +#include +#include #ifdef CONFIG_EMC2305 #include "../common/emc2305.h" #endif +#define GIC_LPI_SIZE 0x200000 #ifdef CONFIG_TARGET_LX2160AQDS #define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value) #define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f) @@ -629,7 +632,6 @@ void board_quiesce_devices(void) #endif #ifdef CONFIG_OF_BOARD_SETUP - int ft_board_setup(void *blob, bd_t *bd) { int i; @@ -640,6 +642,7 @@ int ft_board_setup(void *blob, bd_t *bd) u64 mc_memory_base = 0; u64 mc_memory_size = 0; u16 total_memory_banks; + u64 gic_lpi_base; ft_cpu_setup(blob, bd); @@ -659,6 +662,11 @@ int ft_board_setup(void *blob, bd_t *bd) size[i] = gd->bd->bi_dram[i].size; } +#ifdef CONFIG_GIC_V3_ITS + gic_lpi_base = gd->arch.resv_ram - GIC_LPI_SIZE; + gic_lpi_tables_init(gic_lpi_base, cpu_numcores()); +#endif + #ifdef CONFIG_RESV_RAM /* reduce size if reserved memory is within this bank */ if (gd->arch.resv_ram >= base[0] && -- cgit v1.2.3 From e07f30f681b2d6abeaf110094af5da7f6cc3c5c9 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Fri, 14 Feb 2020 11:04:35 +0530 Subject: configs: lx2160a: Enable GIC_V3_ITS config Enable GIC_V3_ITS config to program GIC LPI configuration table. Signed-off-by: Wasim Khan Reviewed-by: Priyanka Jain --- configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index 7c3b82700da..41fc40fc9ad 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -73,3 +73,4 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_GIC_V3_ITS=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index 449b3cbcf1c..6af20808e01 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -70,3 +70,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_GIC_V3_ITS=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index d1fffb399e9..00fb53133d0 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -68,3 +68,4 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_GIC_V3_ITS=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 93f3e200c03..101bf8b6507 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -69,3 +69,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_GIC_V3_ITS=y -- cgit v1.2.3 From 8cf113f473fdb60b62f939a21bc7f51795b168d8 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Fri, 14 Feb 2020 11:04:36 +0530 Subject: board: fsl: lx2160a: Add GIC LPI memory reserve fixup Reserve DDR memory region used for GIC LPI configuration table. Signed-off-by: Wasim Khan Reviewed-by: Priyanka Jain --- board/freescale/lx2160a/lx2160a.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 7ccd2483fb4..8e22689ec77 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -631,6 +631,21 @@ void board_quiesce_devices(void) } #endif +#ifdef CONFIG_GIC_V3_ITS +void fdt_fixup_gic_lpi_memory(void *blob, u64 gic_lpi_base) +{ + u32 phandle; + int err; + struct fdt_memory gic_lpi; + + gic_lpi.start = gic_lpi_base; + gic_lpi.end = gic_lpi_base + GIC_LPI_SIZE - 1; + err = fdtdec_add_reserved_memory(blob, "gic-lpi", &gic_lpi, &phandle); + if (err < 0) + debug("failed to add reserved memory: %d\n", err); +} +#endif + #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { @@ -665,6 +680,7 @@ int ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_GIC_V3_ITS gic_lpi_base = gd->arch.resv_ram - GIC_LPI_SIZE; gic_lpi_tables_init(gic_lpi_base, cpu_numcores()); + fdt_fixup_gic_lpi_memory(blob, gic_lpi_base); #endif #ifdef CONFIG_RESV_RAM -- cgit v1.2.3 From 395b52127a8d46f890217eaaeab4ed54f65478a0 Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Wed, 19 Feb 2020 17:02:21 +0800 Subject: arm64: ls1028a: remove fdt_high environment variable Setting fdt_high and initrd_high to 0xffffffffffffffff leads to various difficulty to resolve bugs. Remove them and use bootm_size instead to safely contain a kernel, device tree and initrd for relocation. Signed-off-by: Yuantian Tang Reviewed-by: Priyanka Jain --- include/configs/ls1028a_common.h | 3 +-- include/configs/ls1028aqds.h | 2 -- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 05b8cf00ee1..1c7680c2347 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -79,8 +79,7 @@ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ + "bootm_size=0x10000000\0" \ "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "scriptaddr=0x80000000\0" \ diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index 982df07bb01..fca0a3af190 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -90,8 +90,6 @@ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "scriptaddr=0x80000000\0" \ -- cgit v1.2.3 From e9d9c2e57391d38b4d62643dacaa4764db57cae9 Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Wed, 19 Feb 2020 17:02:22 +0800 Subject: arm64: ls1046a: remove fdt_high environment variable Setting fdt_high and initrd_high to 0xffffffffffffffff leads to various difficulty to resolve bugs. Remove them and use bootm_size instead to safely contain a kernel, device tree and initrd for relocation. Signed-off-by: Yuantian Tang Reviewed-by: Priyanka Jain --- include/configs/ls1046a_common.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 3944f877942..978df3c9473 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -217,8 +217,7 @@ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ + "bootm_size=0x10000000\0" \ "fdt_addr=0x64f00000\0" \ "kernel_addr=0x65000000\0" \ "scriptaddr=0x80000000\0" \ -- cgit v1.2.3 From b7e7a46e1007a362be05c76efb3a2ee69e50880d Mon Sep 17 00:00:00 2001 From: Meenakshi Aggarwal Date: Wed, 19 Feb 2020 23:30:45 +0530 Subject: lx2160a : Add emmc in boot_targets environment variable Add emmc in supported boot_targets and Add bootcmd environment variable for emmc boot. Signed-off-by: Meenakshi Aggarwal Reviewed-by: Priyanka Jain --- include/configs/lx2160a_common.h | 11 +++++++++++ include/configs/lx2160aqds.h | 7 +++++++ include/configs/lx2160ardb.h | 7 +++++++ 3 files changed, 25 insertions(+) diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 373daebfbc4..fe0db770e86 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -266,9 +266,20 @@ unsigned long get_board_ddr_clk(void); "run distro_bootcmd;run sd_bootcmd;" \ "env exists secureboot && esbc_halt;" +#define SD2_BOOTCOMMAND \ + "env exists mcinitcmd && mmcinfo; " \ + "mmc read 0x80d00000 0x6800 0x800; " \ + "env exists mcinitcmd && env exists secureboot " \ + " && mmc read 0x80780000 0x3C00 0x20 " \ + "&& esbc_validate 0x80780000;env exists mcinitcmd " \ + "&& fsl_mc lazyapply dpl 0x80d00000;" \ + "run distro_bootcmd;run sd2_bootcmd;" \ + "env exists secureboot && esbc_halt;" + #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) \ func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ func(SCSI, scsi, 0) #include diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index 1eb63d826f9..e9e1770c949 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -137,6 +137,13 @@ u8 qixis_esdhc_detect_quirk(void); "env exists secureboot && mmc read $kernelheader_addr_r "\ "$kernelhdr_addr_sd $kernelhdr_size_sd " \ " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$BOARD\0" \ + "sd2_bootcmd=echo Trying load from emmc card..;" \ + "mmc dev 1; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ "bootm $load_addr#$BOARD\0" #include diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index 82d49e53abd..63d77c5fc4a 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -107,6 +107,13 @@ "env exists secureboot && mmc read $kernelheader_addr_r "\ "$kernelhdr_addr_sd $kernelhdr_size_sd " \ " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$BOARD\0" \ + "sd2_bootcmd=echo Trying load from emmc card..;" \ + "mmc dev 1; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ "bootm $load_addr#$BOARD\0" #include -- cgit v1.2.3 From 160e2b88dfacc19de46098951a1961ab25115645 Mon Sep 17 00:00:00 2001 From: Priyanka Singh Date: Fri, 21 Feb 2020 05:57:03 +0530 Subject: armv8: ls1028a: Update secure boot headers offset Update the secure boot headers offsets of Kernel and other firmware images for SD and XSPI boot sources used by esbc_validate command. Signed-off-by: Priyanka Singh Reviewed-by: Priyanka Jain --- include/configs/ls1028a_common.h | 8 ++++---- include/configs/ls1028aqds.h | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 1c7680c2347..818bd710c6f 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ #ifndef __L1028A_COMMON_H @@ -91,14 +91,14 @@ "fdt_addr_r=0x90000000\0" \ "ramdisk_addr_r=0xa0000000\0" \ "kernel_start=0x1000000\0" \ - "kernelheader_start=0x800000\0" \ + "kernelheader_start=0x600000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "kernelheader_size=0x40000\0" \ "kernel_addr_sd=0x8000\0" \ "kernel_size_sd=0x14000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ - "kernelhdr_size_sd=0x10\0" \ + "kernelhdr_addr_sd=0x3000\0" \ + "kernelhdr_size_sd=0x20\0" \ "console=ttyS0,115200\0" \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ BOOTENV \ diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index fca0a3af190..977c5da4485 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ #ifndef __LS1028A_QDS_H @@ -101,13 +101,13 @@ "fdt_addr_r=0x90000000\0" \ "ramdisk_addr_r=0xa0000000\0" \ "kernel_start=0x1000000\0" \ - "kernelheader_start=0x800000\0" \ + "kernelheader_start=0x600000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "kernelheader_size=0x40000\0" \ "kernel_addr_sd=0x8000\0" \ "kernel_size_sd=0x14000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_addr_sd=0x3000\0" \ "kernelhdr_size_sd=0x10\0" \ "console=ttyS0,115200\0" \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ -- cgit v1.2.3 From 224899d273e1426cc18be317744be2c03798c41f Mon Sep 17 00:00:00 2001 From: Meenakshi Aggarwal Date: Wed, 26 Feb 2020 16:46:48 +0530 Subject: lx2160a : Remove default VID setting Set VID to 800 mV for Rev1 and set VID as per switch settings for Rev2. Signed-off-by: Meenakshi Aggarwal Reviewed-by: Priyanka Jain --- board/freescale/lx2160a/lx2160a.c | 9 ++++++++- include/configs/lx2160aqds.h | 1 - include/configs/lx2160ardb.h | 1 - 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 8e22689ec77..971c76bf504 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -278,7 +278,14 @@ int i2c_multiplexer_select_vid_channel(u8 channel) int init_func_vid(void) { - if (adjust_vdd(0) < 0) + int set_vid; + + if (IS_SVR_REV(get_svr(), 1, 0)) + set_vid = adjust_vdd(800); + else + set_vid = adjust_vdd(0); + + if (set_vid < 0) printf("core voltage not adjusted\n"); return 0; diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index e9e1770c949..3dd071fa25a 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -121,7 +121,6 @@ u8 qixis_esdhc_detect_quirk(void); /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ EXTRA_ENV_SETTINGS \ - "lx2160aqds_vdd_mv=800\0" \ "boot_scripts=lx2160aqds_boot.scr\0" \ "boot_script_hdr=hdr_lx2160aqds_bs.out\0" \ "BOARD=lx2160aqds\0" \ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index 63d77c5fc4a..f54edf356a2 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -93,7 +93,6 @@ EXTRA_ENV_SETTINGS \ "boot_scripts=lx2160ardb_boot.scr\0" \ "boot_script_hdr=hdr_lx2160ardb_bs.out\0" \ - "lx2160ardb_vdd_mv=800\0" \ "BOARD=lx2160ardb\0" \ "xspi_bootcmd=echo Trying load from flexspi..;" \ "sf probe 0:0 && sf read $load_addr " \ -- cgit v1.2.3 From c40ebf7e43fb4bf36559aa69d9a9d63a3ce1830b Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Mon, 9 Mar 2020 14:10:07 +0800 Subject: board: ls1028ardb: add BOARD_LATE_INIT config Select BOARD_LATE_INIT config so that many board works can be done in late init stage. Signed-off-by: Yuantian Tang Reviewed-by: Priyanka Jain --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5d367888d8a..8c3b9b3bf76 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1366,6 +1366,7 @@ config TARGET_LS1028ARDB select ARM64 select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT + select BOARD_LATE_INIT help Support for Freescale LS1028ARDB platform The LS1028A Development System (RDB) is a high-performance -- cgit v1.2.3 From 81d9e55097ee8c495a74ae3d2ffa7f182e2e1ef8 Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Tue, 10 Mar 2020 11:31:05 +0800 Subject: armv8: ls1028a: add dhcp boot target device Add DHCP boot target device to enable command bootcmd_dhcp. Signed-off-by: Yuantian Tang Reviewed-by: Priyanka Jain --- include/configs/ls1028a_common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 818bd710c6f..2a38e9106e3 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -70,7 +70,8 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ - func(USB, usb, 0) + func(USB, usb, 0) \ + func(DHCP, dhcp, na) #include /* Initial environment variables */ -- cgit v1.2.3 From c5076a021eaa221e70b87fbf3a38744bf29419c3 Mon Sep 17 00:00:00 2001 From: Meenakshi Aggarwal Date: Wed, 11 Mar 2020 20:51:47 +0530 Subject: lx2160a: Add dhcp in boot_targets Add dhcp in supported boot_targets for lx2160. Signed-off-by: Meenakshi Aggarwal Signed-off-by: Priyanka Jain --- include/configs/lx2160a_common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index fe0db770e86..7adb31d81d5 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -280,7 +280,8 @@ unsigned long get_board_ddr_clk(void); func(USB, usb, 0) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ - func(SCSI, scsi, 0) + func(SCSI, scsi, 0) \ + func(DHCP, dhcp, na) #include #endif /* __LX2_COMMON_H */ -- cgit v1.2.3 From e219d7d0f1dbf16ec2547a9f7136cf0a9d642402 Mon Sep 17 00:00:00 2001 From: Madalin Bucur Date: Thu, 12 Mar 2020 14:53:44 +0200 Subject: net: fman: add support for all RGMII delay modes The RGMII modes that include internal delay were not all properly treated in the memac code. Add support for all RGMII delay modes. Fixes: 111fd19e3b9e ("fm/mEMAC: add mEMAC frame work") Signed-off-by: Madalin Bucur Reviewed-by: Priyanka Jain --- drivers/net/fm/memac.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c index 2c499513f99..bed8f14aeec 100644 --- a/drivers/net/fm/memac.c +++ b/drivers/net/fm/memac.c @@ -83,6 +83,8 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac, if_mode |= IF_MODE_GMII; break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_TXID: if_mode |= (IF_MODE_GMII | IF_MODE_RG); break; @@ -107,6 +109,8 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac, if_mode |= IF_MODE_EN_AUTO; if (type == PHY_INTERFACE_MODE_RGMII || + type == PHY_INTERFACE_MODE_RGMII_ID || + type == PHY_INTERFACE_MODE_RGMII_RXID || type == PHY_INTERFACE_MODE_RGMII_TXID) { if_mode &= ~IF_MODE_EN_AUTO; if_mode &= ~IF_MODE_SETSP_MASK; -- cgit v1.2.3 From 00160cf32e6e3796afa6f74ec2a8e607cdbb8832 Mon Sep 17 00:00:00 2001 From: Madalin Bucur Date: Thu, 12 Mar 2020 14:53:45 +0200 Subject: armv8/ls1043ardb: RGMII ports require internal delay The correct setting for the RGMII ports on LS1043ARDB is to enable delay on both Rx and Tx so the interface mode used must be PHY_INTERFACE_MODE_RGMII_ID. There is a pull-up that turns on Rx internal delay by default and the u-boot does not override that (yet) so in u-boot the interface is functional. In Linux the PHY driver is clearing the Rx delay for the "rgmii-txid" mode and the reception does not work. Changing the RGMII mode to internal delay here ensures that device tree fix-ups for the PHY connection type turn on both Tx and Rx internal delay in Linux. Fixes: 5a78a472f666 ("armv8/ls1043a: RGMII PHY requires internal delay on Tx") Signed-off-by: Madalin Bucur Reviewed-by: Priyanka Jain --- drivers/net/fm/ls1043.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/fm/ls1043.c b/drivers/net/fm/ls1043.c index cd510f29559..ba4da69423a 100644 --- a/drivers/net/fm/ls1043.c +++ b/drivers/net/fm/ls1043.c @@ -65,12 +65,12 @@ phy_interface_t fman_port_enet_if(enum fm_port port) if (port == FM1_DTSEC3) if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) == FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) { - return PHY_INTERFACE_MODE_RGMII_TXID; + return PHY_INTERFACE_MODE_RGMII_ID; } if (port == FM1_DTSEC4) if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) == FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) { - return PHY_INTERFACE_MODE_RGMII_TXID; + return PHY_INTERFACE_MODE_RGMII_ID; } /* handle SGMII */ -- cgit v1.2.3 From 4fb2264b284899f837ebb93c2c64c0c92226de0a Mon Sep 17 00:00:00 2001 From: Madalin Bucur Date: Thu, 12 Mar 2020 14:53:46 +0200 Subject: armv8/ls1046ardb: RGMII ports require internal delay The correct setting for the RGMII ports on LS1046ARDB is to enable delay on both Rx and Tx so the interface mode used must be PHY_INTERFACE_MODE_RGMII_ID. There is a pull-up that turns on Rx internal delay by default and the u-boot does not override that (yet) so in u-boot the interface is functional. In Linux the PHY driver is clearing the Rx delay for the "rgmii-txid" mode and the reception does not work. Changing the RGMII mode to internal delay here ensures that device tree fix-ups for the PHY connection type turn on both Tx and Rx internal delay in Linux. Fixes: cc1aa218f510 ("armv8/ls1046a: RGMII PHY requires internal delay on Tx") Signed-off-by: Madalin Bucur Reviewed-by: Priyanka Jain --- drivers/net/fm/ls1046.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/fm/ls1046.c b/drivers/net/fm/ls1046.c index 3617ad93e4a..49b540bd30b 100644 --- a/drivers/net/fm/ls1046.c +++ b/drivers/net/fm/ls1046.c @@ -71,12 +71,12 @@ phy_interface_t fman_port_enet_if(enum fm_port port) if (port == FM1_DTSEC3) if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) == FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) - return PHY_INTERFACE_MODE_RGMII_TXID; + return PHY_INTERFACE_MODE_RGMII_ID; if (port == FM1_DTSEC4) if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) == FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) - return PHY_INTERFACE_MODE_RGMII_TXID; + return PHY_INTERFACE_MODE_RGMII_ID; /* handle SGMII, only MAC 2/5/6/9/10 available */ switch (port) { -- cgit v1.2.3 From 095b6be41ecf1cfef24d762ab9fdc062367ffeda Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 13 Mar 2020 10:26:29 +0800 Subject: include/configs: ls1012afrwy: fix load address of itb with bootm command The old load address of itb will overwrite uboots reserved memory on ls1012afrwy with 512 MiB ram Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- include/configs/ls1012afrwy.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index dde4369c97c..6ea524c5bb7 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -65,7 +65,7 @@ "kernelheader_size=0x40000\0" \ "kernel_addr_r=0x96000000\0" \ "fdt_addr_r=0x90000000\0" \ - "load_addr=0x96000000\0" \ + "load_addr=0x92000000\0" \ "kernel_size=0x2800000\0" \ "kernelheader_size=0x40000\0" \ "console=ttyS0,115200\0" \ -- cgit v1.2.3 From f83567e0c08e87e4aaeef80ce9ca45986977c451 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Fri, 13 Mar 2020 16:53:06 +0200 Subject: pci-host-ecam-generic: access config space independent of system-wide bus id The pci-host-ecam-generic code assumes that the ECAM is the first PCI bus in the system to be probed. Therefore, the system-wide bus number allocated by U-Boot in sequence for it is going to be zero, which corresponds to the memory-mapped config spaces found within it. Reuse the logic from other PCI bus drivers, and assume that U-Boot will allocate bus numbers in sequence for all buses within the current ECAM. So the base number of the bus needs to be subtracted when indexing the correct config space. Fixes: 3675cb044e68 ("PCI: Add driver for a 'pci-host-ecam-generic' host controller") Signed-off-by: Vladimir Oltean Reviewed-by: Alex Marginean Signed-off-by: Priyanka Jain --- drivers/pci/pcie_ecam_generic.c | 37 +++++++++++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pcie_ecam_generic.c b/drivers/pci/pcie_ecam_generic.c index c875f3a5b7d..890b6a8fb69 100644 --- a/drivers/pci/pcie_ecam_generic.c +++ b/drivers/pci/pcie_ecam_generic.c @@ -19,6 +19,8 @@ */ struct generic_ecam_pcie { void *cfg_base; + pci_size_t size; + int first_busno; }; /** @@ -43,7 +45,7 @@ static int pci_generic_ecam_conf_address(const struct udevice *bus, void *addr; addr = pcie->cfg_base; - addr += PCI_BUS(bdf) << 20; + addr += (PCI_BUS(bdf) - pcie->first_busno) << 20; addr += PCI_DEV(bdf) << 15; addr += PCI_FUNC(bdf) << 12; addr += offset; @@ -52,6 +54,16 @@ static int pci_generic_ecam_conf_address(const struct udevice *bus, return 0; } +static bool pci_generic_ecam_addr_valid(const struct udevice *bus, + pci_dev_t bdf) +{ + struct generic_ecam_pcie *pcie = dev_get_priv(bus); + int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16); + + return (PCI_BUS(bdf) >= pcie->first_busno && + PCI_BUS(bdf) < pcie->first_busno + num_buses); +} + /** * pci_generic_ecam_read_config() - Read from configuration space * @bus: Pointer to the PCI bus @@ -68,6 +80,11 @@ static int pci_generic_ecam_read_config(const struct udevice *bus, pci_dev_t bdf, uint offset, ulong *valuep, enum pci_size_t size) { + if (!pci_generic_ecam_addr_valid(bus, bdf)) { + *valuep = pci_get_ff(size); + return 0; + } + return pci_generic_mmap_read_config(bus, pci_generic_ecam_conf_address, bdf, offset, valuep, size); } @@ -88,6 +105,9 @@ static int pci_generic_ecam_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong value, enum pci_size_t size) { + if (!pci_generic_ecam_addr_valid(bus, bdf)) + return 0; + return pci_generic_mmap_write_config(bus, pci_generic_ecam_conf_address, bdf, offset, value, size); } @@ -116,9 +136,17 @@ static int pci_generic_ecam_ofdata_to_platdata(struct udevice *dev) return err; } - pcie->cfg_base = map_physmem(reg_res.start, - fdt_resource_size(®_res), - MAP_NOCACHE); + pcie->size = fdt_resource_size(®_res); + pcie->cfg_base = map_physmem(reg_res.start, pcie->size, MAP_NOCACHE); + + return 0; +} + +static int pci_generic_ecam_probe(struct udevice *dev) +{ + struct generic_ecam_pcie *pcie = dev_get_priv(dev); + + pcie->first_busno = dev->seq; return 0; } @@ -138,6 +166,7 @@ U_BOOT_DRIVER(pci_generic_ecam) = { .id = UCLASS_PCI, .of_match = pci_generic_ecam_ids, .ops = &pci_generic_ecam_ops, + .probe = pci_generic_ecam_probe, .ofdata_to_platdata = pci_generic_ecam_ofdata_to_platdata, .priv_auto_alloc_size = sizeof(struct generic_ecam_pcie), }; -- cgit v1.2.3 From 515f32973aa52ba75758b08606b447c82852cd80 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Thu, 19 Mar 2020 15:18:54 +0800 Subject: board: fsl: lx2160a: fix SDHC1_DAT4 signal routing The SDHC1_DAT4 signal could be routes to SDHC1_VS or SDHC1 adapter slot for SDHC1 usage. When SDHC1 is selected in RCW, do not force to route it to SDHC1 adapter slot if find it has already been configued for SDHC1_VS. Signed-off-by: Yangbo Lu Reviewed-by: Priyanka Jain --- board/freescale/lx2160a/lx2160a.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 971c76bf504..4b20bb440f7 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -480,10 +480,16 @@ int config_board_mux(void) reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01); QIXIS_WRITE(brdcfg[11], reg11); } else { - /* Routes {SDHC1_DAT4} to SDHC1 adapter slot */ + /* + * If {SDHC1_DAT4} has been configured to route to SDHC1_VS, + * do not change it. + * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot. + */ reg11 = QIXIS_READ(brdcfg[11]); - reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00); - QIXIS_WRITE(brdcfg[11], reg11); + if ((reg11 & 0x30) != 0x30) { + reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00); + QIXIS_WRITE(brdcfg[11], reg11); + } /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot. * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot. -- cgit v1.2.3 From 472dfe546c9c24c51f30763c2d232b9d12cf3719 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Thu, 19 Mar 2020 19:38:42 +0800 Subject: configs: ls1088aqds: support distro boot Add support of distro boot for ls1088aqds Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- include/configs/ls1088aqds.h | 63 +++++++++++++++++++++++++++++++++++--------- 1 file changed, 50 insertions(+), 13 deletions(-) diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 361c72fc8c9..4ac4a8d8568 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -443,19 +443,47 @@ unsigned long get_board_ddr_clk(void); "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ "sf read 0x80100000 0xE00000 0x100000;" \ "fsl_mc start mc 0x80000000 0x80100000\0" \ - "mcmemsize=0x70000000 \0" -#define QSPI_NOR_BOOTCOMMAND "sf probe 0:0;" \ - "sf read 0x80001000 0xd00000 0x100000;"\ - " fsl_mc lazyapply dpl 0x80001000 &&" \ - " sf read $kernel_load $kernel_start" \ - " $kernel_size && bootm $kernel_load" -#define SD_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\ - " fsl_mc lazyapply dpl 0x80001000 &&" \ - " mmc read $kernel_load $kernel_start_sd" \ - " $kernel_size_sd && bootm $kernel_load" -#define IFC_NOR_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \ - " cp.b $kernel_start $kernel_load" \ - " $kernel_size && bootm $kernel_load" + "mcmemsize=0x70000000 \0" \ + "BOARD=ls1088aqds\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + BOOTENV \ + "boot_scripts=ls1088aqds_boot.scr\0" \ + "boot_script_hdr=hdr_ls1088aqds_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr}; "\ + "env exists secureboot " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "qspi_bootcmd=echo Trying load from qspi..; " \ + "sf probe 0:0; " \ + "sf read 0x80001000 0xd00000 0x100000; " \ + "fsl_mc lazyapply dpl 0x80001000 && " \ + "sf read $kernel_load $kernel_start " \ + "$kernel_size && bootm $kernel_load#$BOARD\0" \ + "sd_bootcmd=echo Trying load from sd card..; " \ + "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\ + "fsl_mc lazyapply dpl 0x80001000 && " \ + "mmc read $kernel_load $kernel_start_sd " \ + "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \ + "nor_bootcmd=echo Trying load from nor..; " \ + "fsl_mc lazyapply dpl 0x580d00000 && " \ + "cp.b $kernel_start $kernel_load " \ + "$kernel_size && bootm $kernel_load#$BOARD\0" #else #if defined(CONFIG_QSPI_BOOT) #undef CONFIG_EXTRA_ENV_SETTINGS @@ -510,6 +538,15 @@ unsigned long get_board_ddr_clk(void); #endif /* CONFIG_TFABOOT */ #endif /* CONFIG_NXP_ESBC */ +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#endif + #ifdef CONFIG_FSL_MC_ENET #define CONFIG_FSL_MEMAC #define CONFIG_PHYLIB -- cgit v1.2.3 From 1a9ce6e0df0e5463a8804f64b0b58621d981c289 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Thu, 19 Mar 2020 20:01:07 +0800 Subject: configs: ls2080aqds: support distro boot Add support of distro boot for ls2080aqds Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- include/configs/ls2080aqds.h | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 88da69f36f0..e93faab9a46 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -383,7 +383,30 @@ unsigned long get_board_ddr_clk(void); "kernelheader_size=0x40000\0" \ "BOARD=ls2088aqds\0" \ "mcmemsize=0x70000000 \0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ IFC_MC_INIT_CMD \ + BOOTENV \ + "boot_scripts=ls2088aqds_boot.scr\0" \ + "boot_script_hdr=hdr_ls2088aqds_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr} " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ "nor_bootcmd=echo Trying load from nor..;" \ "cp.b $kernel_addr $load_addr " \ "$kernel_size ; env exists secureboot && " \ @@ -429,6 +452,13 @@ unsigned long get_board_ddr_clk(void); #endif /* CONFIG_NXP_ESBC */ #ifdef CONFIG_TFABOOT +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(MMC, mmc, 0) \ + func(SCSI, scsi, 0) \ + func(DHCP, dhcp, na) +#include + #define SD_BOOTCOMMAND \ "env exists mcinitcmd && env exists secureboot "\ "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \ @@ -436,14 +466,14 @@ unsigned long get_board_ddr_clk(void); "env exists mcinitcmd && run mcinitcmd " \ "&& mmc read 0x80d00000 0x6800 0x800 " \ "&& fsl_mc lazyapply dpl 0x80d00000; " \ - "run sd_bootcmd; " \ + "run distro_bootcmd;run sd_bootcmd; " \ "env exists secureboot && esbc_halt;" #define IFC_NOR_BOOTCOMMAND \ "env exists mcinitcmd && env exists secureboot "\ "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\ "&& fsl_mc lazyapply dpl 0x580d00000;" \ - "run nor_bootcmd; " \ + "run distro_bootcmd;run nor_bootcmd; " \ "env exists secureboot && esbc_halt;" #endif -- cgit v1.2.3 From 40ef9d16975ddfe502ab8db70336dd0fc0f13607 Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Fri, 20 Mar 2020 14:37:06 +0800 Subject: armv8: ls1028aqds: add some environments Add sd and emmc bootcmd environments to facilitate the boot process. Signed-off-by: Yuantian Tang Signed-off-by: Priyanka Jain --- include/configs/ls1028aqds.h | 39 ++++++++++++++++++++++++++++----------- 1 file changed, 28 insertions(+), 11 deletions(-) diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index 977c5da4485..818b994b907 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -99,6 +99,7 @@ "load_addr=0xa0000000\0" \ "kernel_addr_r=0x81000000\0" \ "fdt_addr_r=0x90000000\0" \ + "fdt2_addr_r=0x90010000\0" \ "ramdisk_addr_r=0xa0000000\0" \ "kernel_start=0x1000000\0" \ "kernelheader_start=0x600000\0" \ @@ -139,19 +140,35 @@ "${scripthdraddr} ${prefix}${boot_script_hdr} " \ "&& esbc_validate ${scripthdraddr};" \ "source ${scriptaddr}\0" \ - "sd_bootcmd=echo Trying load from SD ..;" \ - "mmcinfo; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ + "xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \ + "sf probe 0:0 && sf read $load_addr " \ + "$kernel_start $kernel_size ; env exists secureboot &&" \ + "sf read $kernelheader_addr_r $kernelheader_start " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + " bootm $load_addr#$board\0" \ + "xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \ + "sf probe 0:0 && sf read $load_addr 0x940000 0x30000 " \ + "&& hdp load $load_addr 0x2000\0" \ + "sd_bootcmd=echo Trying load from SD ...;" \ + "mmc dev 0; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ "env exists secureboot && mmc read $kernelheader_addr_r " \ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$board\0" \ - "emmc_bootcmd=echo Trying load from EMMC ..;" \ - "mmcinfo; mmc dev 1; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$board\0" \ + "sd_hdploadcmd=echo Trying load HDP firmware from SD..;" \ + "mmc dev 0;mmcinfo; mmc read $load_addr 0x4a00 0x200 " \ + "&& hdp load $load_addr 0x2000\0" \ + "emmc_bootcmd=echo Trying load from EMMC ..;" \ + "mmc dev 1; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ "env exists secureboot && mmc read $kernelheader_addr_r " \ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$board\0" + "bootm $load_addr#$board\0" \ + "emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;" \ + "mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \ + "&& hdp load $load_addr 0x2000\0" + #endif #endif /* __LS1028A_QDS_H */ -- cgit v1.2.3 From a023c3c2c8eb7afa7b1f0cea2690d9b02cf4cb1b Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Fri, 20 Mar 2020 14:37:07 +0800 Subject: armv8: ls1028a: clean up the environment variables Move the environment variables from command head file to ls1028ardb specific head file so that they will not mess up with ls1028aqds board. Also updated some variable slightly. There is no function change by this patch. Signed-off-by: Yuantian Tang Signed-off-by: Priyanka Jain --- include/configs/ls1028a_common.h | 86 --------------------------------------- include/configs/ls1028ardb.h | 88 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+), 86 deletions(-) diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 2a38e9106e3..6905694d102 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -74,92 +74,6 @@ func(DHCP, dhcp, na) #include -/* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "board=ls1028ardb\0" \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "bootm_size=0x10000000\0" \ - "fdt_addr=0x00f00000\0" \ - "kernel_addr=0x01000000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "load_addr=0xa0000000\0" \ - "kernel_addr_r=0x81000000\0" \ - "fdt_addr_r=0x90000000\0" \ - "ramdisk_addr_r=0xa0000000\0" \ - "kernel_start=0x1000000\0" \ - "kernelheader_start=0x600000\0" \ - "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "kernelheader_size=0x40000\0" \ - "kernel_addr_sd=0x8000\0" \ - "kernel_size_sd=0x14000\0" \ - "kernelhdr_addr_sd=0x3000\0" \ - "kernelhdr_size_sd=0x20\0" \ - "console=ttyS0,115200\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - BOOTENV \ - "boot_scripts=ls1028ardb_boot.scr\0" \ - "boot_script_hdr=hdr_ls1028ardb_bs.out\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "scan_dev_for_boot=" \ - "echo Scanning ${devtype} " \ - "${devnum}:${distro_bootpart}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "run scan_dev_for_scripts; " \ - "done;" \ - "\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "${scripthdraddr} ${prefix}${boot_script_hdr} " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" \ - "xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \ - "sf probe 0:0 && sf read $load_addr " \ - "$kernel_start $kernel_size ; env exists secureboot &&" \ - "sf read $kernelheader_addr_r $kernelheader_start " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ - " bootm $load_addr#$board\0" \ - "xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \ - "sf probe 0:0 && sf read $load_addr 0x940000 0x30000 " \ - "&& hdp load $load_addr 0x2000\0" \ - "sd_bootcmd=echo Trying load from SD ...;" \ - "mmcinfo; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ - "env exists secureboot && mmc read $kernelheader_addr_r " \ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$board\0" \ - "sd_hdploadcmd=echo Trying load HDP firmware from SD..;" \ - "mmcinfo;mmc read $load_addr 0x4a00 0x200 " \ - "&& hdp load $load_addr 0x2000\0" \ - "emmc_bootcmd=echo Trying load from EMMC ..;" \ - "mmcinfo; mmc dev 1; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ - "env exists secureboot && mmc read $kernelheader_addr_r " \ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$board\0" \ - "emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;" \ - "mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \ - "&& hdp load $load_addr 0x2000\0" - #undef CONFIG_BOOTCOMMAND #define XSPI_NOR_BOOTCOMMAND \ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index a4c3d73d2a1..0f289cb0780 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -72,4 +72,92 @@ #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 +/* Initial environment variables */ +#ifndef SPL_NO_ENV +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "board=ls1028ardb\0" \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "bootm_size=0x10000000\0" \ + "fdt_addr=0x00f00000\0" \ + "kernel_addr=0x01000000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "ramdisk_addr_r=0xa0000000\0" \ + "kernel_start=0x1000000\0" \ + "kernelheader_start=0x600000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernelheader_size=0x40000\0" \ + "kernel_addr_sd=0x8000\0" \ + "kernel_size_sd=0x14000\0" \ + "kernelhdr_addr_sd=0x3000\0" \ + "kernelhdr_size_sd=0x20\0" \ + "console=ttyS0,115200\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + BOOTENV \ + "boot_scripts=ls1028ardb_boot.scr\0" \ + "boot_script_hdr=hdr_ls1028ardb_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "scan_dev_for_boot=" \ + "echo Scanning ${devtype} " \ + "${devnum}:${distro_bootpart}...; " \ + "for prefix in ${boot_prefixes}; do " \ + "run scan_dev_for_scripts; " \ + "done;" \ + "\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr} " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \ + "sf probe 0:0 && sf read $load_addr " \ + "$kernel_start $kernel_size ; env exists secureboot &&" \ + "sf read $kernelheader_addr_r $kernelheader_start " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + " bootm $load_addr#$board\0" \ + "xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \ + "sf probe 0:0 && sf read $load_addr 0x940000 0x30000 " \ + "&& hdp load $load_addr 0x2000\0" \ + "sd_bootcmd=echo Trying load from SD ...;" \ + "mmc dev 0;mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "env exists secureboot && mmc read $kernelheader_addr_r " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$board\0" \ + "sd_hdploadcmd=echo Trying load HDP firmware from SD..;" \ + "mmc dev 0;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \ + "&& hdp load $load_addr 0x2000\0" \ + "emmc_bootcmd=echo Trying load from EMMC ..;" \ + "mmc dev 1;mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "env exists secureboot && mmc read $kernelheader_addr_r " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$board\0" \ + "emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;" \ + "mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \ + "&& hdp load $load_addr 0x2000\0" +#endif #endif /* __LS1028A_RDB_H */ -- cgit v1.2.3 From c8a7cadc81a064f1d00bb3255ee64a687ac73ebe Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 20 Mar 2020 17:05:51 +0800 Subject: configs: ls1012afrwy: fix wrong env of board Fix wrong environment variable of board for ls1012afrwy Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- include/configs/ls1012afrwy.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index 6ea524c5bb7..44b467aca54 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -8,6 +8,9 @@ #include "ls1012a_common.h" +#undef CONFIG_SYS_BOARD +#define CONFIG_SYS_BOARD "ls1012afrwy" + /* Board Rev*/ #define BOARD_REV_A_B 0x0 #define BOARD_REV_C 0x00080000 -- cgit v1.2.3 From fefac937fbd87f380042501c63b874994b3dccee Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Wed, 5 Feb 2020 22:02:16 +0800 Subject: dm: arm64: ls1043a: add i2c DM support This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1043A Signed-off-by: Biwen Li Signed-off-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 10 +-- arch/arm/include/asm/gpio.h | 3 +- board/freescale/ls1043aqds/ls1043aqds.c | 98 +++++++++++++++++++++++-- configs/ls1043aqds_defconfig | 2 + configs/ls1043aqds_lpuart_defconfig | 2 + configs/ls1043aqds_nand_defconfig | 2 + configs/ls1043aqds_nor_ddr3_defconfig | 2 + configs/ls1043aqds_qspi_defconfig | 2 + configs/ls1043aqds_sdcard_ifc_defconfig | 2 + configs/ls1043aqds_sdcard_qspi_defconfig | 2 + configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 2 + configs/ls1043aqds_tfa_defconfig | 2 + configs/ls1043ardb_SECURE_BOOT_defconfig | 2 + configs/ls1043ardb_defconfig | 2 + configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 2 + configs/ls1043ardb_nand_defconfig | 2 + configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 2 + configs/ls1043ardb_sdcard_defconfig | 2 + configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 2 + configs/ls1043ardb_tfa_defconfig | 2 + include/configs/ls1043a_common.h | 11 +++ 21 files changed, 144 insertions(+), 12 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 275c66d9929..760053e4012 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -74,11 +74,11 @@ config ARCH_LS1043A select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F - select SYS_I2C_MXC - select SYS_I2C_MXC_I2C1 - select SYS_I2C_MXC_I2C2 - select SYS_I2C_MXC_I2C3 - select SYS_I2C_MXC_I2C4 + select SYS_I2C_MXC if !DM_I2C + select SYS_I2C_MXC_I2C1 if !DM_I2C + select SYS_I2C_MXC_I2C2 if !DM_I2C + select SYS_I2C_MXC_I2C3 if !DM_I2C + select SYS_I2C_MXC_I2C4 if !DM_I2C imply CMD_PCI config ARCH_LS1046A diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 84e5cb46e5a..5d6b269deda 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -4,7 +4,8 @@ !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_LX2160A) && \ !defined(CONFIG_ARCH_LS1028A) && !defined(CONFIG_ARCH_LS2080A) && \ !defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \ - !defined(CONFIG_ARCH_LS1012A) && !defined(CONFIG_ARCH_U8500) && \ + !defined(CONFIG_ARCH_LS1012A) && !defined(CONFIG_ARCH_LS1043A) && \ + !defined(CONFIG_ARCH_U8500) && \ !defined(CONFIG_CORTINA_PLATFORM) #include #endif diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 8c96b962b78..2d4b18cdbcb 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #include @@ -271,11 +272,24 @@ unsigned long get_board_ddr_clk(void) return 66666666; } -int select_i2c_ch_pca9547(u8 ch) +int select_i2c_ch_pca9547(u8 ch, int bus_num) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + ret = dm_i2c_write(dev, 0, &ch, 1); +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -290,8 +304,10 @@ int dram_init(void) * When resuming from deep sleep, the I2C channel may not be * in the default channel. So, switch to the default channel * before accessing DDR SPD. + * + * PCA9547 mount on I2C1 bus */ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); fsl_initdram(); #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ defined(CONFIG_SPL_BUILD) @@ -304,16 +320,83 @@ int dram_init(void) int i2c_multiplexer_select_vid_channel(u8 channel) { - return select_i2c_ch_pca9547(channel); + return select_i2c_ch_pca9547(channel, 0); } void board_retimer_init(void) { u8 reg; + int bus_num = 0; /* Retimer is connected to I2C1_CH7_CH5 */ - select_i2c_ch_pca9547(I2C_MUX_CH7); + select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num); reg = I2C_MUX_CH5; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return; + } + dm_i2c_write(dev, 0, ®, 1); + + /* Access to Control/Shared register */ + ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return; + } + + reg = 0x0; + dm_i2c_write(dev, 0xff, ®, 1); + + /* Read device revision and ID */ + dm_i2c_read(dev, 1, ®, 1); + debug("Retimer version id = 0x%x\n", reg); + + /* Enable Broadcast. All writes target all channel register sets */ + reg = 0x0c; + dm_i2c_write(dev, 0xff, ®, 1); + + /* Reset Channel Registers */ + dm_i2c_read(dev, 0, ®, 1); + reg |= 0x4; + dm_i2c_write(dev, 0, ®, 1); + + /* Enable override divider select and Enable Override Output Mux */ + dm_i2c_read(dev, 9, ®, 1); + reg |= 0x24; + dm_i2c_write(dev, 9, ®, 1); + + /* Select VCO Divider to full rate (000) */ + dm_i2c_read(dev, 0x18, ®, 1); + reg &= 0x8f; + dm_i2c_write(dev, 0x18, ®, 1); + + /* Selects active PFD MUX Input as Re-timed Data (001) */ + dm_i2c_read(dev, 0x1e, ®, 1); + reg &= 0x3f; + reg |= 0x20; + dm_i2c_write(dev, 0x1e, ®, 1); + + /* Set data rate as 10.3125 Gbps */ + reg = 0x0; + dm_i2c_write(dev, 0x60, ®, 1); + reg = 0xb2; + dm_i2c_write(dev, 0x61, ®, 1); + reg = 0x90; + dm_i2c_write(dev, 0x62, ®, 1); + reg = 0xb3; + dm_i2c_write(dev, 0x63, ®, 1); + reg = 0xcd; + dm_i2c_write(dev, 0x64, ®, 1); +#else i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1); /* Access to Control/Shared register */ @@ -360,9 +443,10 @@ void board_retimer_init(void) i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); reg = 0xcd; i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); +#endif /* Return the default channel */ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num); } int board_early_init_f(void) @@ -375,8 +459,10 @@ int board_early_init_f(void) u8 uart; #endif +#ifdef CONFIG_SYS_I2C #ifdef CONFIG_SYS_I2C_EARLY_INIT i2c_early_init_f(); +#endif #endif fsl_lsch2_early_init_f(); @@ -457,7 +543,7 @@ int board_init(void) erratum_a010315(); #endif - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); board_retimer_init(); #ifdef CONFIG_SYS_FSL_SERDES diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 2885552ef34..93b86af6074 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -62,3 +62,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index 9d9229ac03a..f89c2ee3a4f 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -64,3 +64,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index c45eaea02a5..a169bfef8f6 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -78,3 +78,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 8d28fe1baff..01d0af30b17 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -63,3 +63,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 86b2eb56b84..65eff7c40b8 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -58,3 +58,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index bf3f0d09909..c5042a345d7 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -79,3 +79,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 0449469b895..12706a48dc8 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -72,3 +72,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index 0ece698350d..b7335bcd335 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -63,3 +63,5 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 24db72a39d2..6e594ed07c6 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -71,3 +71,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index 5e030e2586d..153a62866ff 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -55,3 +55,5 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 0676cbccdd6..d1e534388b9 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -55,3 +55,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index 1f4c5705d58..252c7c8313a 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -75,3 +75,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index e7fe2de309f..de18aaa0635 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -74,3 +74,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index 6529c7334c1..149b25ffe52 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -74,3 +74,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index 228262477cd..b386fc668cc 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -73,3 +73,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index 94ca502f3b5..36eb0fcff72 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -56,3 +56,5 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index 4154075986c..eaddbca79f8 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -59,3 +59,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index bf24d4036d2..985f40412c6 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2015 Freescale Semiconductor + * Copyright (C) 2019 NXP */ #ifndef __LS1043A_COMMON_H @@ -141,7 +142,17 @@ #endif /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif /* PCIe */ #ifndef SPL_NO_PCIE -- cgit v1.2.3 From bb1165f900088c796e254cc99c8f81d47e3d57c9 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Wed, 5 Feb 2020 22:02:17 +0800 Subject: dm: arm64: ls1046a: add i2c DM support This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1046A Signed-off-by: Biwen Li Signed-off-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 10 +++--- arch/arm/dts/fsl-ls1046a-frwy.dts | 3 ++ arch/arm/dts/fsl-ls1046a-qds.dtsi | 4 +++ arch/arm/dts/fsl-ls1046a-rdb.dts | 8 +++++ arch/arm/include/asm/gpio.h | 2 +- board/freescale/ls1046afrwy/ls1046afrwy.c | 17 +++++++-- board/freescale/ls1046aqds/ls1046aqds.c | 25 +++++++++++--- configs/ls1046afrwy_tfa_defconfig | 2 ++ configs/ls1046aqds_SECURE_BOOT_defconfig | 2 ++ configs/ls1046aqds_defconfig | 2 ++ configs/ls1046aqds_lpuart_defconfig | 2 ++ configs/ls1046aqds_nand_defconfig | 2 ++ configs/ls1046aqds_qspi_defconfig | 2 ++ configs/ls1046aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1046aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1046aqds_tfa_defconfig | 2 ++ configs/ls1046ardb_emmc_defconfig | 2 ++ configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1046ardb_qspi_defconfig | 2 ++ configs/ls1046ardb_qspi_spl_defconfig | 2 ++ configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 2 ++ configs/ls1046ardb_sdcard_defconfig | 2 ++ configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1046ardb_tfa_defconfig | 2 ++ drivers/power/power_i2c.c | 46 +++++++++++++++++++++++-- include/configs/ls1046a_common.h | 11 ++++++ 27 files changed, 148 insertions(+), 14 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 760053e4012..b25639183f8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -107,11 +107,11 @@ config ARCH_LS1046A select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F - select SYS_I2C_MXC - select SYS_I2C_MXC_I2C1 - select SYS_I2C_MXC_I2C2 - select SYS_I2C_MXC_I2C3 - select SYS_I2C_MXC_I2C4 + select SYS_I2C_MXC if !DM_I2C + select SYS_I2C_MXC_I2C1 if !DM_I2C + select SYS_I2C_MXC_I2C2 if !DM_I2C + select SYS_I2C_MXC_I2C3 if !DM_I2C + select SYS_I2C_MXC_I2C4 if !DM_I2C imply SCSI imply SCSI_AHCI diff --git a/arch/arm/dts/fsl-ls1046a-frwy.dts b/arch/arm/dts/fsl-ls1046a-frwy.dts index 3d41e3bd44f..d39159322a5 100644 --- a/arch/arm/dts/fsl-ls1046a-frwy.dts +++ b/arch/arm/dts/fsl-ls1046a-frwy.dts @@ -32,3 +32,6 @@ }; +&i2c0 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi b/arch/arm/dts/fsl-ls1046a-qds.dtsi index c95f44fc361..76dc397328a 100644 --- a/arch/arm/dts/fsl-ls1046a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi @@ -80,3 +80,7 @@ &sata { status = "okay"; }; + +&i2c0 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts index a05c9e9b9ea..83e34ab02ad 100644 --- a/arch/arm/dts/fsl-ls1046a-rdb.dts +++ b/arch/arm/dts/fsl-ls1046a-rdb.dts @@ -43,3 +43,11 @@ &sata { status = "okay"; }; + +&i2c0 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 5d6b269deda..333e407b666 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -5,7 +5,7 @@ !defined(CONFIG_ARCH_LS1028A) && !defined(CONFIG_ARCH_LS2080A) && \ !defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \ !defined(CONFIG_ARCH_LS1012A) && !defined(CONFIG_ARCH_LS1043A) && \ - !defined(CONFIG_ARCH_U8500) && \ + !defined(CONFIG_ARCH_LS1046A) && !defined(CONFIG_ARCH_U8500) && \ !defined(CONFIG_CORTINA_PLATFORM) #include #endif diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c index db8b3a5b921..8c0abb63a9d 100644 --- a/board/freescale/ls1046afrwy/ls1046afrwy.c +++ b/board/freescale/ls1046afrwy/ls1046afrwy.c @@ -36,11 +36,24 @@ DECLARE_GLOBAL_DATA_PTR; -int select_i2c_ch_pca9547(u8 ch) +int select_i2c_ch_pca9547(u8 ch, int bus_num) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + ret = dm_i2c_write(dev, 0, &ch, 1); +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -149,7 +162,7 @@ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); sec_init(); #endif - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); return 0; } diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index aac5d9aa848..cabd7ee648c 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #include @@ -269,11 +270,23 @@ u32 get_lpuart_clk(void) } #endif -int select_i2c_ch_pca9547(u8 ch) +int select_i2c_ch_pca9547(u8 ch, int bus_num) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + ret = dm_i2c_write(dev, 0, &ch, 1); +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -288,8 +301,10 @@ int dram_init(void) * When resuming from deep sleep, the I2C channel may not be * in the default channel. So, switch to the default channel * before accessing DDR SPD. + * + * PCA9547 mount on I2C1 bus */ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); fsl_initdram(); #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ defined(CONFIG_SPL_BUILD) @@ -302,7 +317,7 @@ int dram_init(void) int i2c_multiplexer_select_vid_channel(u8 channel) { - return select_i2c_ch_pca9547(channel); + return select_i2c_ch_pca9547(channel, 0); } int board_early_init_f(void) @@ -315,8 +330,10 @@ int board_early_init_f(void) u8 uart; #endif +#ifdef CONFIG_SYS_I2C #ifdef CONFIG_SYS_I2C_EARLY_INIT i2c_early_init_f(); +#endif #endif fsl_lsch2_early_init_f(); @@ -394,7 +411,7 @@ int misc_init_r(void) int board_init(void) { - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); #ifdef CONFIG_SYS_FSL_SERDES config_serdes_mux(); diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index 2c258785d1e..616984f7d75 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -62,3 +62,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index 6ea27c7ba42..ed25b7a680b 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -60,3 +60,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index 04c1176d858..0a50bb14c02 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -62,3 +62,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index b0a24f297ee..17d1685081f 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -64,3 +64,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index 3ffe6a6ef9c..0bafcbe168d 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -70,3 +70,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index d6253c790a5..ff0fd45c9ec 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -58,3 +58,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index fad33163b6b..78edb456b84 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -80,3 +80,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index 3571a6f9e96..d085daf384c 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -74,3 +74,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index e1737479231..6a9391478b4 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -61,3 +61,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 824fc518ca7..04e6b2392c2 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -71,3 +71,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index 768ce7a821b..bbb352db316 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -73,3 +73,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index aff9bf81fcd..b9c8a8822cf 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -55,3 +55,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index b482e73bef6..51edada3f86 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -57,3 +57,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index 1e2770a9c08..84e059671c2 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -77,3 +77,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_SPL_GZIP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 1f5fa8ff037..9954e894dac 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -70,3 +70,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index 197090474bc..35028097564 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -72,3 +72,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index 1dde0ae73b3..9e3042b797e 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -54,3 +54,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index 280ca83d424..2f7686bafd1 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -58,3 +58,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/drivers/power/power_i2c.c b/drivers/power/power_i2c.c index bcddff2d7a0..b30f223a5c2 100644 --- a/drivers/power/power_i2c.c +++ b/drivers/power/power_i2c.c @@ -7,6 +7,7 @@ * Stefano Babic, DENX Software Engineering, sbabic@denx.de * * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * (C) Copyright 2019 NXP */ #include @@ -21,8 +22,20 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val) if (check_reg(p, reg)) return -EINVAL; +#if defined(CONFIG_DM_I2C) + struct udevice *dev; + int ret; + ret = i2c_get_chip_for_busnum(p->bus, pmic_i2c_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + p->bus); + return -ENXIO; + } +#else /* Non DM I2C support - will be removed */ I2C_SET_BUS(p->bus); +#endif switch (pmic_i2c_tx_num) { case 3: @@ -53,7 +66,11 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val) return -EINVAL; } +#if defined(CONFIG_DM_I2C) + return dm_i2c_write(dev, reg, buf, pmic_i2c_tx_num); +#else return i2c_write(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num); +#endif } int pmic_reg_read(struct pmic *p, u32 reg, u32 *val) @@ -65,9 +82,21 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val) if (check_reg(p, reg)) return -EINVAL; - I2C_SET_BUS(p->bus); +#if defined(CONFIG_DM_I2C) + struct udevice *dev; + ret = i2c_get_chip_for_busnum(p->bus, pmic_i2c_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + p->bus); + return -ENXIO; + } + ret = dm_i2c_read(dev, reg, buf, pmic_i2c_tx_num); +#else /* Non DM I2C support - will be removed */ + I2C_SET_BUS(p->bus); ret = i2c_read(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num); +#endif if (ret) return ret; @@ -100,12 +129,25 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val) int pmic_probe(struct pmic *p) { - i2c_set_bus_num(p->bus); debug("Bus: %d PMIC:%s probed!\n", p->bus, p->name); +#if defined(CONFIG_DM_I2C) + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(p->bus, pmic_i2c_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + p->bus); + return -ENXIO; + } +#else /* Non DM I2C support - will be removed */ + i2c_set_bus_num(p->bus); if (i2c_probe(pmic_i2c_addr)) { printf("Can't find PMIC:%s\n", p->name); return -ENODEV; } +#endif return 0; } diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 978df3c9473..e80c2996ef9 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -16,6 +16,7 @@ #define SPL_NO_QSPI #define SPL_NO_USB #define SPL_NO_SATA +#undef CONFIG_DM_I2C #endif #if defined(CONFIG_SPL_BUILD) && \ (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT)) @@ -126,7 +127,17 @@ #endif /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif /* PCIe */ #define CONFIG_PCIE1 /* PCIE controller 1 */ -- cgit v1.2.3 From 45eaecc84d4fde426938011ef5b043cfe0df489a Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Fri, 7 Feb 2020 12:42:07 +0800 Subject: configs: arm64: ls1012afrdm Enable CONFIG_BLK With DM_USB enabled, enable CONFIG_BLK to remove this compile warning for ls1012afrdm based targets: ===================== WARNING ====================== This board does not use CONFIG_DM_USB. Please update the board to use CONFIG_DM_USB before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. ==================================================== Signed-off-by: Ran Wang Signed-off-by: Priyanka Jain --- configs/ls1012afrdm_qspi_defconfig | 1 + configs/ls1012afrdm_tfa_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index 11d0cee39a3..1e601484eee 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -5,6 +5,7 @@ CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_ENV_OFFSET=0x300000 CONFIG_DM_GPIO=y +CONFIG_BLK=y CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index 2818bdf0d21..420a2f416cb 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_ENV_OFFSET=0x500000 CONFIG_DM_GPIO=y +CONFIG_BLK=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -- cgit v1.2.3 From ba23bb073405e10216b6e6d03842ebc2b9e4366f Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Fri, 7 Feb 2020 12:42:08 +0800 Subject: configs: arm: ls1021aiot: enable CONFIG_DM_USB support Enable CONFIG_DM_USB to remove below compile warning: ===================== WARNING ====================== This board does not use CONFIG_DM_USB. Please update the board to use CONFIG_DM_USB before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. ==================================================== Signed-off-by: Ran Wang Signed-off-by: Priyanka Jain --- configs/ls1021aiot_qspi_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig index 7ba0c47a5bb..512f7753031 100644 --- a/configs/ls1021aiot_qspi_defconfig +++ b/configs/ls1021aiot_qspi_defconfig @@ -45,5 +45,6 @@ CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y CONFIG_FSL_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -- cgit v1.2.3 From 366b1473e81b2ef7878860f57661706ea4812ef5 Mon Sep 17 00:00:00 2001 From: Priyanka Singh Date: Fri, 21 Feb 2020 05:57:04 +0530 Subject: configs: ls1012ardb: secure boot: Add PFE config Add config to enable the PFE and ETH support. Also change the pfe secure boot header address. Signed-off-by: Priyanka Singh Signed-off-by: Priyanka Jain --- board/freescale/ls1012ardb/Kconfig | 2 +- configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig index 639353a94bb..5a2fa91f6be 100644 --- a/board/freescale/ls1012ardb/Kconfig +++ b/board/freescale/ls1012ardb/Kconfig @@ -35,7 +35,7 @@ config SYS_LS_PFE_FW_ADDR config SYS_LS_PFE_ESBC_ADDR hex "PFE Firmware HDR Addr" - default 0x40700000 + default 0x40640000 config DDR_PFE_PHYS_BASEADDR hex "PFE DDR physical base address" diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index 2f48da82e4d..4e937e53eef 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -60,3 +60,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y +CONFIG_FSL_PFE=y +CONFIG_DM_ETH=y -- cgit v1.2.3 From edb558c78feb69942e1a88389ea7b5654973c6b0 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Tue, 3 Mar 2020 10:32:51 +0800 Subject: configs: disable eMMC HS200 support on layerscape platforms The eMMC HS200 speed mode on Layerscape platforms has not been supported properly. The eSDHC clock tuning has not been implemented by now. So disable it until it is supported properly in case of any potential issues. Signed-off-by: Yangbo Lu Reviewed-by: Jaehoon Chung Signed-off-by: Priyanka Jain --- configs/ls1012ardb_tfa_defconfig | 1 - configs/ls1028ardb_tfa_defconfig | 1 - configs/lx2160ardb_tfa_defconfig | 1 - 3 files changed, 3 deletions(-) diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index 4dec4181b71..fdf2324a631 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -40,7 +40,6 @@ CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -CONFIG_MMC_HS200_SUPPORT=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 3ef5520969f..7ffd1c3bc6e 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -45,7 +45,6 @@ CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MMC=y -CONFIG_MMC_HS200_SUPPORT=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 101bf8b6507..3d469c97834 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -41,7 +41,6 @@ CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_DM_MMC=y -CONFIG_MMC_HS200_SUPPORT=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -- cgit v1.2.3 From f1573d842cfae38dc8c73c8a6201b79ced62ec5d Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Mon, 16 Mar 2020 15:59:06 +0800 Subject: configs: ls1021a: Append othbootargs to bootargs This patch appends othbootargs to bootargs for LS1021ATWR board. Signed-off-by: Alison Wang Signed-off-by: Priyanka Jain --- include/configs/ls1021atwr.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 6a6cdd19cca..a6289850ca1 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -297,7 +297,7 @@ #ifdef CONFIG_LPUART #define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ + "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 $othbootargs\0" \ "initrd_high=0xffffffff\0" \ "fdt_addr=0x64f00000\0" \ "kernel_addr=0x65000000\0" \ @@ -312,7 +312,6 @@ "kernel_size=0x2800000\0" \ "kernel_addr_sd=0x8000\0" \ "kernel_size_sd=0x14000\0" \ - "$othbootargs\0" \ "othbootargs=cma=64M@0x0-0xb0000000\0" \ BOOTENV \ "boot_scripts=ls1021atwr_boot.scr\0" \ @@ -354,7 +353,7 @@ "$kernel_size && bootm $load_addr#$board\0" #else #define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ + "bootargs=root=/dev/ram0 rw console=ttyS0,115200 $othbootargs\0" \ "initrd_high=0xffffffff\0" \ "fdt_addr=0x64f00000\0" \ "kernel_addr=0x61000000\0" \ @@ -373,7 +372,6 @@ "kernel_size_sd=0x14000\0" \ "kernelhdr_addr_sd=0x4000\0" \ "kernelhdr_size_sd=0x10\0" \ - "$othbootargs\0" \ "othbootargs=cma=64M@0x0-0xb0000000\0" \ BOOTENV \ "boot_scripts=ls1021atwr_boot.scr\0" \ -- cgit v1.2.3 From 1d0bb1b9d2928ba99464ee0ad4091554e731f640 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 20 Mar 2020 18:26:14 +0800 Subject: configs: ls1012afrwy: adjust env kernel_addr_r Adjust environment kernel_addr_r from 0x96000000 to 0x92000000 to fix a bug that failed to boot kernel for ls1012afrwy with 512MiB RAM, => tftpboot $kernel_addr_r Image (Image size is 36 MiB) TFTP error: trying to overwrite reserved memory... Signed-off-by: Biwen Li Signed-off-by: Priyanka Jain --- include/configs/ls1012afrwy.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index 44b467aca54..899dfdbdf1f 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -66,7 +66,7 @@ "fdtheader_addr_r=0x80100000\0" \ "kernelheader_addr_r=0x80200000\0" \ "kernelheader_size=0x40000\0" \ - "kernel_addr_r=0x96000000\0" \ + "kernel_addr_r=0x92000000\0" \ "fdt_addr_r=0x90000000\0" \ "load_addr=0x92000000\0" \ "kernel_size=0x2800000\0" \ -- cgit v1.2.3 From 4c1a52294f23e97c492bddff8987cd7290f6907c Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Mon, 2 Mar 2020 16:39:19 +0530 Subject: arm: dts: lx2160aqds: Add FSPI node properties lx2160a-qds has 2 micron "mt35xu512aba" flashes of size 64M each connected on A0 and B1 i.e on CS0 and CS3. Since flashes are connected on different buses, only one flash can be probed at a time. Add fspi node properties aligned with LX2160A-RDB fspi properties. Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-lx2160a-qds.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts index 34df0f51060..33bedae6553 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dts +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -13,6 +13,9 @@ / { model = "NXP Layerscape LX2160AQDS Board"; compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + aliases { + spi0 = &fspi; + }; }; &esdhc0 { @@ -46,6 +49,18 @@ }; }; +&fspi { + status = "okay"; + + mt35xu512aba0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; +}; + &sata0 { status = "okay"; }; -- cgit v1.2.3 From 0f0a906125e189a7bfcdf2916ea9bda96281f22b Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Sat, 14 Mar 2020 18:43:41 +0530 Subject: configs: lx2160a: Enable FSPI support Enable FSPI controller support. So, flash environment can now be used. Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160aqds_tfa_defconfig | 3 +++ configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 3 +++ 4 files changed, 8 insertions(+) diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index 41fc40fc9ad..319f7103829 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -65,6 +65,7 @@ CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_NXP_FSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index 6af20808e01..732a3bf1b14 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -4,6 +4,7 @@ CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_ENV_OFFSET=0x500000 CONFIG_DM_GPIO=y CONFIG_FSPI_AHB_EN_4BYTE=y @@ -32,6 +33,7 @@ CONFIG_OF_CONTROL=y CONFIG_OF_BOARD_FIXUP=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds" CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y @@ -65,6 +67,7 @@ CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index 00fb53133d0..10098ab5a9d 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -60,6 +60,7 @@ CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 3d469c97834..3574334eef0 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -4,6 +4,7 @@ CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_ENV_OFFSET=0x500000 CONFIG_DM_GPIO=y CONFIG_EMC2305=y @@ -33,6 +34,7 @@ CONFIG_OF_CONTROL=y CONFIG_OF_BOARD_FIXUP=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y @@ -63,6 +65,7 @@ CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y -- cgit v1.2.3 From 802dcce869867c76ddbf2c6b8a95221b5fc423b6 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Tue, 4 Feb 2020 12:02:36 +0530 Subject: configs: lx2160a: Define ENV_ADDR value CONFIG_ENV_ADDR helps in picking environment from flash before DDR init. Define the value as 0x20500000 for lx2160ardb and lx2160aqds. Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index 732a3bf1b14..0161dba9a72 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -34,6 +34,7 @@ CONFIG_OF_BOARD_FIXUP=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x20500000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 3574334eef0..c8582aa40d6 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -35,6 +35,7 @@ CONFIG_OF_BOARD_FIXUP=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x20500000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y -- cgit v1.2.3 From b9804c35a877b11d128262b968d0a9499584c339 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Thu, 12 Mar 2020 15:13:00 +0530 Subject: configs: lx2160a: Access flash memory as per spi-mem MC_INIT and BOOT command currently access spi-nor flash memory directly. As per spi-mem framework, flash memory access via absolute addresses is no more possible. Use flash APIs to access memory instead of directly using it. Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- include/configs/lx2160a_common.h | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 7adb31d81d5..d47abf6e657 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -187,11 +187,15 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* Initial environment variables */ -#define XSPI_MC_INIT_CMD \ - "env exists secureboot && " \ - "esbc_validate 0x20640000 && " \ - "esbc_validate 0x20680000 ;" \ - "fsl_mc start mc 0x20a00000 0x20e00000\0" +#define XSPI_MC_INIT_CMD \ + "sf probe 0:0 && " \ + "sf read 0x80640000 0x640000 0x80000 && " \ + "env exists secureboot && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000; " \ + "sf read 0x80a00000 0xa00000 0x300000 && " \ + "sf read 0x80e00000 0xe00000 0x100000; " \ + "fsl_mc start mc 0x80a00000 0x80e00000\0" #define SD_MC_INIT_CMD \ "mmc read 0x80a00000 0x5000 0x1200;" \ @@ -249,10 +253,13 @@ unsigned long get_board_ddr_clk(void); "source ${scriptaddr}\0" #define XSPI_NOR_BOOTCOMMAND \ - "env exists mcinitcmd && env exists secureboot "\ - "&& esbc_validate 0x206C0000; " \ + "sf probe 0:0; " \ + "sf read 0x806c0000 0x6c0000 0x40000; " \ + "env exists mcinitcmd && env exists secureboot" \ + " && esbc_validate 0x806c0000; " \ + "sf read 0x80d00000 0xd00000 0x100000; " \ "env exists mcinitcmd && " \ - "fsl_mc lazyapply dpl 0x20d00000; " \ + "fsl_mc lazyapply dpl 0x80d00000; " \ "run distro_bootcmd;run xspi_bootcmd; " \ "env exists secureboot && esbc_halt;" -- cgit v1.2.3 From bd294e43dc8233a875088bbf4dc89ceb43f5b777 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Sat, 14 Mar 2020 18:23:56 +0530 Subject: arm: dts: lx2160a: Use flexspi in octal I/O mode Configure RX and TX bus-width values to use flexspi in octal I/O mode. If bus-widths are not specified, then single I/O mode is set by default. Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-lx2160a-qds.dts | 2 ++ arch/arm/dts/fsl-lx2160a-rdb.dts | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts index 33bedae6553..592fd5977e2 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dts +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -58,6 +58,8 @@ compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <1>; }; }; diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts index e542c6992ab..87617ca51f6 100644 --- a/arch/arm/dts/fsl-lx2160a-rdb.dts +++ b/arch/arm/dts/fsl-lx2160a-rdb.dts @@ -39,6 +39,8 @@ compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <1>; }; mt35xu512aba1: flash@1 { @@ -47,6 +49,8 @@ compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <1>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <1>; }; }; -- cgit v1.2.3 From 3ec7900b230aed8c35209eeb162fa75f759db69c Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Sat, 14 Mar 2020 18:23:55 +0530 Subject: arm: dts: ls1028a: Use flexspi in octal I/O mode Configure RX and TX bus-width values to use flexspi in octal I/O mode. If bus-widths are not specified, then single I/O mode is set by default. Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a-qds.dts | 2 ++ arch/arm/dts/fsl-ls1028a-rdb.dts | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/dts/fsl-ls1028a-qds.dts b/arch/arm/dts/fsl-ls1028a-qds.dts index 3fd37beedf4..029a8e386b1 100644 --- a/arch/arm/dts/fsl-ls1028a-qds.dts +++ b/arch/arm/dts/fsl-ls1028a-qds.dts @@ -49,6 +49,8 @@ compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <1>; }; }; diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts index a8f40855b65..85b4815b2ed 100644 --- a/arch/arm/dts/fsl-ls1028a-rdb.dts +++ b/arch/arm/dts/fsl-ls1028a-rdb.dts @@ -48,6 +48,8 @@ compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <1>; }; }; -- cgit v1.2.3 From 4666521d19df4421be1b3c1042ac7ecfb351f884 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 21 Mar 2020 16:57:58 +0100 Subject: ARM: rmobile: Implement PMIC reset on V2H Blanche Add code to reset the board through PMIC, by writing the required PMIC registers in the CPU reset handler. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- board/renesas/blanche/blanche.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c index 7232370d6f4..471d80fc72f 100644 --- a/board/renesas/blanche/blanche.c +++ b/board/renesas/blanche/blanche.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -355,4 +356,23 @@ int dram_init_banksize(void) void reset_cpu(ulong addr) { + struct udevice *dev; + const u8 pmic_bus = 6; + const u8 pmic_addr = 0x58; + u8 data; + int ret; + + ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); + if (ret) + hang(); + + ret = dm_i2c_read(dev, 0x13, &data, 1); + if (ret) + hang(); + + data |= BIT(1); + + ret = dm_i2c_write(dev, 0x13, &data, 1); + if (ret) + hang(); } -- cgit v1.2.3 From 264398b2ec5dd5ee045939e11e14caeece4c8dde Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 21 Mar 2020 17:38:57 +0100 Subject: ARM: rmobile: Only register ethernet on V2H Blanche if not DM_ETH If the DM_ETH is enabled, the board-specific ethernet registeration should be disabled, make it so. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- board/renesas/blanche/blanche.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c index 471d80fc72f..c15387366c7 100644 --- a/board/renesas/blanche/blanche.c +++ b/board/renesas/blanche/blanche.c @@ -314,6 +314,7 @@ int board_init(void) } /* Added for BLANCHE(R-CarV2H board) */ +#ifndef CONFIG_DM_ETH int board_eth_init(bd_t *bis) { int rc = 0; @@ -338,6 +339,7 @@ int board_eth_init(bd_t *bis) return rc; } +#endif int dram_init(void) { -- cgit v1.2.3 From 67357553ad59eb9b4f412412252e02868ceb16dc Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 30 Mar 2020 20:27:42 +0200 Subject: test/py: test_efi_grub_net() requires OF_CONTROL With CONFIG_OF_CONTROL environment variable $fdtcontroladdr is not defined and test_efi_grub_net() fails. Signed-off-by: Heinrich Schuchardt --- test/py/tests/test_efi_loader.py | 1 + 1 file changed, 1 insertion(+) diff --git a/test/py/tests/test_efi_loader.py b/test/py/tests/test_efi_loader.py index e105645484f..9465c28fbc5 100644 --- a/test/py/tests/test_efi_loader.py +++ b/test/py/tests/test_efi_loader.py @@ -170,6 +170,7 @@ def test_efi_helloworld_builtin(u_boot_console): expected_text = 'Hello, world' assert expected_text in output +@pytest.mark.buildconfigspec('of_control') @pytest.mark.buildconfigspec('cmd_bootefi') def test_efi_grub_net(u_boot_console): """Run the grub.efi binary via TFTP. -- cgit v1.2.3 From 93330d4ce416208fe202e304e5a18166c57ac569 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 30 Mar 2020 19:29:27 -0400 Subject: Prepare v2020.04-rc4 Signed-off-by: Tom Rini --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index fa687f13a58..7fae3c2f643 100644 --- a/Makefile +++ b/Makefile @@ -3,7 +3,7 @@ VERSION = 2020 PATCHLEVEL = 04 SUBLEVEL = -EXTRAVERSION = -rc3 +EXTRAVERSION = -rc4 NAME = # *DOCUMENTATION* -- cgit v1.2.3 From 69f9c8bab83fff7228547f3cf01bf3c123faaaf4 Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Fri, 6 Mar 2020 16:55:18 +0800 Subject: arm: socfpga: Add onchip RAM size macro Add OCRAM size macro for Gen5 and Arria 10. Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 2 ++ arch/arm/mach-socfpga/include/mach/base_addr_ac5.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h index 929c413e039..b947cc07291 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h @@ -47,4 +47,6 @@ #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS 0xffd13400 #define SOCFPGA_NOC_FW_H2F_SCR_OFST 0xffd13500 +#define SOCFPGA_PHYS_OCRAM_SIZE 0x40000 + #endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h index 2725e9fcc34..da966fb4583 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h @@ -59,4 +59,6 @@ #define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000 #define SOCFPGA_DMASECURE_ADDRESS 0xffe01000 +#define SOCFPGA_PHYS_OCRAM_SIZE 0x10000 + #endif /* _SOCFPGA_BASE_ADDRS_H_ */ -- cgit v1.2.3 From 4f17f2966a8d7b624b5aff58ebe5a0245038c25a Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Fri, 6 Mar 2020 16:55:19 +0800 Subject: configs: socfpga: Change to use SOCFPGA_PHYS_OCRAM_SIZE macro Change to use SOCFPGA_PHYS_OCRAM_SIZE macro for onchip RAM size. Signed-off-by: Ley Foon Tan --- include/configs/socfpga_common.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index ec418436953..410ec80618f 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -21,14 +21,15 @@ #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE #if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 /* SPL memory allocation configuration, this is for FAT implementation */ #ifndef CONFIG_SYS_SPL_MALLOC_SIZE #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000 #endif -#define CONFIG_SYS_INIT_RAM_SIZE (0x40000 - CONFIG_SYS_SPL_MALLOC_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ + CONFIG_SYS_SPL_MALLOC_SIZE) #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE) #endif -- cgit v1.2.3 From 3d884ff470f7d26febbd90a52b4f7bdff47da796 Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Fri, 6 Mar 2020 16:55:20 +0800 Subject: arm: socfpga: arria10: Add save_boot_params() Add save_boot_params() to save reset status value from bootrom. Bootrom will clear the status register in reset manager and stores the reset status value in shared memory. Bootrom stores shared data at last 2KB of onchip RAM. This function save reset status provided by bootrom to rst_mgr_status. More information about reset status register value can be found in reset manager register description. When running in debugger without bootrom, r0 to r3 are random values. So, skip save the value when r0 is not bootrom shared data address. Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/spl_a10.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index d9ef851054d..b10be332680 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -33,6 +33,38 @@ DECLARE_GLOBAL_DATA_PTR; +#define BOOTROM_SHARED_MEM_SIZE 0x800 /* 2KB */ +#define BOOTROM_SHARED_MEM_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + SOCFPGA_PHYS_OCRAM_SIZE - \ + BOOTROM_SHARED_MEM_SIZE) +#define RST_STATUS_SHARED_ADDR (BOOTROM_SHARED_MEM_ADDR + 0x438) +static u32 rst_mgr_status __section(.data); + +/* + * Bootrom will clear the status register in reset manager and stores the + * reset status value in shared memory. Bootrom stores shared data at last + * 2KB of onchip RAM. + * This function save reset status provided by BootROM to rst_mgr_status. + * More information about reset status register value can be found in reset + * manager register description. + * When running in debugger without Bootrom, r0 to r3 are random values. + * So, skip save the value when r0 is not BootROM shared data address. + * + * r0 - Contains the pointer to the shared memory block. The shared + * memory block is located in the top 2 KB of on-chip RAM. + * r1 - contains the length of the shared memory. + * r2 - unused and set to 0x0. + * r3 - points to the version block. + */ +void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, + unsigned long r3) +{ + if (r0 == BOOTROM_SHARED_MEM_ADDR) + rst_mgr_status = readl(RST_STATUS_SHARED_ADDR); + + save_boot_params_ret(); +} + u32 spl_boot_device(void) { const u32 bsel = readl(socfpga_get_sysmgr_addr() + SYSMGR_A10_BOOTINFO); -- cgit v1.2.3 From df8e15af2bed62a5a93c5783ec9e32b9029bb010 Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Tue, 31 Mar 2020 08:45:25 +0800 Subject: arm: dts: agilex: Enable QSPI Enable QSPI for Agilex SoC devkit. Signed-off-by: Ley Foon Tan --- arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi index 1908be4b8b2..debeb8b239a 100644 --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -37,3 +37,6 @@ u-boot,dm-pre-reloc; }; +&qspi { + status = "okay"; +}; -- cgit v1.2.3 From 0df27d687c4639208d6e378907ca00f68cd06da6 Mon Sep 17 00:00:00 2001 From: Lihua Zhao Date: Wed, 18 Mar 2020 07:32:07 -0700 Subject: image-fit: Allow loading FIT image for VxWorks This adds the check against IH_OS_VXWORKS during FIT image load, to allow loading FIT image for VxWorks. Signed-off-by: Lihua Zhao Signed-off-by: Bin Meng Reviewed-by: Bin Meng --- common/image-fit.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/common/image-fit.c b/common/image-fit.c index 4435bc4f1d9..6da69d25ffe 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -2007,7 +2007,8 @@ int fit_image_load(bootm_headers_t *images, ulong addr, fit_image_check_os(fit, noffset, IH_OS_LINUX) || fit_image_check_os(fit, noffset, IH_OS_U_BOOT) || fit_image_check_os(fit, noffset, IH_OS_OPENRTOS) || - fit_image_check_os(fit, noffset, IH_OS_EFI); + fit_image_check_os(fit, noffset, IH_OS_EFI) || + fit_image_check_os(fit, noffset, IH_OS_VXWORKS); /* * If either of the checks fail, we should report an error, but -- cgit v1.2.3 From 71a3e5c51c96fe4011ef2cea8490e523786de863 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 29 Mar 2020 19:26:57 +0000 Subject: cmd: mmc: fix typo 'a EMMC' %s/a EMMC/an eMMC/g Signed-off-by: Heinrich Schuchardt Reviewed-by: Jaehoon Chung --- cmd/mmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cmd/mmc.c b/cmd/mmc.c index 6f3cb85cc04..1860a3f2e5d 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -264,7 +264,7 @@ static int do_mmcrpmb(cmd_tbl_t *cmdtp, int flag, return CMD_RET_FAILURE; if (!(mmc->version & MMC_VERSION_MMC)) { - printf("It is not a EMMC device\n"); + printf("It is not an eMMC device\n"); return CMD_RET_FAILURE; } if (mmc->version < MMC_VERSION_4_41) { @@ -718,7 +718,7 @@ static int do_mmc_boot_resize(cmd_tbl_t *cmdtp, int flag, return CMD_RET_FAILURE; if (IS_SD(mmc)) { - printf("It is not a EMMC device\n"); + printf("It is not an eMMC device\n"); return CMD_RET_FAILURE; } -- cgit v1.2.3 From 1d7ad9fa051e5b3057bccb6384ab62e4f9c206b2 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Tue, 28 Jan 2020 12:04:33 +0000 Subject: gpio: mpc8xxx: don't modify gpdat when setting gpio as input Since some chips don't support reading back the value of output gpios from the gpdat register, we should not do a RMW cycle (i.e., the clrbits_be32) on the gpdat register when setting a gpio as input, as that might accidentally change the value of some other (still configured as output) gpio. The extra indirection through mpc8xxx_gpio_set_in() does not help readability, so just fold the gpdir update into mpc8xxx_gpio_direction_input(). Signed-off-by: Rasmus Villemoes --- drivers/gpio/mpc8xxx_gpio.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c index c273c2c8a40..d4f3092df07 100644 --- a/drivers/gpio/mpc8xxx_gpio.c +++ b/drivers/gpio/mpc8xxx_gpio.c @@ -57,13 +57,6 @@ static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask) return in_be32(&base->gpdir) & mask; } -static inline void mpc8xxx_gpio_set_in(struct ccsr_gpio *base, u32 gpios) -{ - clrbits_be32(&base->gpdat, gpios); - /* GPDIR register 0 -> input */ - clrbits_be32(&base->gpdir, gpios); -} - static inline void mpc8xxx_gpio_set_low(struct ccsr_gpio *base, u32 gpios) { clrbits_be32(&base->gpdat, gpios); @@ -100,8 +93,11 @@ static inline void mpc8xxx_gpio_open_drain_off(struct ccsr_gpio *base, static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio) { struct mpc8xxx_gpio_data *data = dev_get_priv(dev); + u32 mask = gpio_mask(gpio); + + /* GPDIR register 0 -> input */ + clrbits_be32(&data->base->gpdir, mask); - mpc8xxx_gpio_set_in(data->base, gpio_mask(gpio)); return 0; } -- cgit v1.2.3 From dd4cf53f9864362d9e92472298ad60dcbb8b7e72 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Tue, 28 Jan 2020 12:04:34 +0000 Subject: gpio: mpc8xxx: don't do RMW on gpdat register when setting value The driver correctly handles reading back the value of an output gpio by reading from the shadow register for output, and from gpdat for inputs. Unfortunately, when setting the value of some gpio, we do a RMW cycle on the gpdat register without taking the shadow register into account, thus accidentally setting other output gpios (at least those whose value cannot be read back) to 0 at the same time. When changing a gpio from input to output, we still need to make sure it initially has the requested value. So, the procedure is - update the shadow register - compute the new gpdir register - write the bitwise and of the shadow and new gpdir register to gpdat - write the new gpdir register Signed-off-by: Rasmus Villemoes --- drivers/gpio/mpc8xxx_gpio.c | 29 +++++++++++------------------ 1 file changed, 11 insertions(+), 18 deletions(-) diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c index d4f3092df07..4b385b8b395 100644 --- a/drivers/gpio/mpc8xxx_gpio.c +++ b/drivers/gpio/mpc8xxx_gpio.c @@ -57,20 +57,6 @@ static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask) return in_be32(&base->gpdir) & mask; } -static inline void mpc8xxx_gpio_set_low(struct ccsr_gpio *base, u32 gpios) -{ - clrbits_be32(&base->gpdat, gpios); - /* GPDIR register 1 -> output */ - setbits_be32(&base->gpdir, gpios); -} - -static inline void mpc8xxx_gpio_set_high(struct ccsr_gpio *base, u32 gpios) -{ - setbits_be32(&base->gpdat, gpios); - /* GPDIR register 1 -> output */ - setbits_be32(&base->gpdir, gpios); -} - static inline int mpc8xxx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask) { return in_be32(&base->gpodr) & mask; @@ -104,14 +90,21 @@ static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio) static int mpc8xxx_gpio_set_value(struct udevice *dev, uint gpio, int value) { struct mpc8xxx_gpio_data *data = dev_get_priv(dev); + struct ccsr_gpio *base = data->base; + u32 mask = gpio_mask(gpio); + u32 gpdir; if (value) { - data->dat_shadow |= gpio_mask(gpio); - mpc8xxx_gpio_set_high(data->base, gpio_mask(gpio)); + data->dat_shadow |= mask; } else { - data->dat_shadow &= ~gpio_mask(gpio); - mpc8xxx_gpio_set_low(data->base, gpio_mask(gpio)); + data->dat_shadow &= ~mask; } + + gpdir = in_be32(&base->gpdir); + gpdir |= gpio_mask(gpio); + out_be32(&base->gpdat, gpdir & data->dat_shadow); + out_be32(&base->gpdir, gpdir); + return 0; } -- cgit v1.2.3 From 3fb22bc2f825ea1b3326edc5b32d711a759a265f Mon Sep 17 00:00:00 2001 From: Klaus H. Sorensen Date: Tue, 11 Feb 2020 15:20:22 +0000 Subject: gpio/mpc83xx_spisel_boot.c: gpio driver for SPISEL_BOOT signal Some SoCs in the mpc83xx family, e.g. mpc8309, have a dedicated spi chip select, SPISEL_BOOT, that is used by the boot code to boot from flash. This chip select will typically be used to select a SPI boot flash. The SPISEL_BOOT signal is controlled by a single bit in the SPI_CS register. Implement a gpio driver for the spi chip select register. This allows a spi driver capable of using gpios as chip select, to bind a chip select to SPISEL_BOOT. It may be a little odd to do this as a GPIO driver, since the signal is neither GP or I, but it is quite convenient to present it to the spi driver that way. The alternative it to teach mpc8xxx_spi to handle the SPISEL_BOOT signal itself (that is how it's done in the linux kernel, see commit 69b921acae8a) Signed-off-by: Klaus H. Sorensen Signed-off-by: Rasmus Villemoes --- .../gpio/fsl,mpc83xx-spisel-boot.txt | 22 +++ drivers/gpio/Kconfig | 8 ++ drivers/gpio/Makefile | 1 + drivers/gpio/mpc83xx_spisel_boot.c | 148 +++++++++++++++++++++ 4 files changed, 179 insertions(+) create mode 100644 doc/device-tree-bindings/gpio/fsl,mpc83xx-spisel-boot.txt create mode 100644 drivers/gpio/mpc83xx_spisel_boot.c diff --git a/doc/device-tree-bindings/gpio/fsl,mpc83xx-spisel-boot.txt b/doc/device-tree-bindings/gpio/fsl,mpc83xx-spisel-boot.txt new file mode 100644 index 00000000000..52d8bb0a5cb --- /dev/null +++ b/doc/device-tree-bindings/gpio/fsl,mpc83xx-spisel-boot.txt @@ -0,0 +1,22 @@ +MPC83xx SPISEL_BOOT gpio controller + +Provide access to MPC83xx SPISEL_BOOT signal as a gpio to allow it to be +easily bound as a SPI controller chip select. + +The SPISEL_BOOT signal is always an output. + +Required properties: + +- compatible: must be "fsl,mpc83xx-spisel-boot" or "fsl,mpc8309-spisel-boot". +- reg: must point to the SPI_CS register in the SoC register map. +- ngpios: number of gpios provided by driver, normally 1. + +Example: + + spisel_boot: spisel_boot@14c { + compatible = "fsl,mpc8309-spisel-boot"; + reg = <0x14c 0x04>; + #gpio-cells = <2>; + device_type = "gpio"; + ngpios = <1>; + }; diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index f751a8b9ea8..2081520f42e 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -423,6 +423,14 @@ config MPC8XXX_GPIO value setting, the open-drain feature, which can configure individual GPIOs to work as open-drain outputs, is supported. +config MPC83XX_SPISEL_BOOT + bool "Freescale MPC83XX SPISEL_BOOT driver" + depends on DM_GPIO && ARCH_MPC830X + help + GPIO driver to set/clear dedicated SPISEL_BOOT output on MPC83XX. + + This pin is typically used as spi chip select to a spi nor flash. + config MT7621_GPIO bool "MediaTek MT7621 GPIO driver" depends on DM_GPIO && SOC_MT7628 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 9dd5a583898..7638259007a 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o obj-$(CONFIG_ALTERA_PIO) += altera_pio.o obj-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o obj-$(CONFIG_MPC8XXX_GPIO) += mpc8xxx_gpio.o +obj-$(CONFIG_MPC83XX_SPISEL_BOOT) += mpc83xx_spisel_boot.o obj-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o obj-$(CONFIG_OMAP_GPIO) += omap_gpio.o obj-$(CONFIG_DB8500_GPIO) += db8500_gpio.o diff --git a/drivers/gpio/mpc83xx_spisel_boot.c b/drivers/gpio/mpc83xx_spisel_boot.c new file mode 100644 index 00000000000..c7b08404d93 --- /dev/null +++ b/drivers/gpio/mpc83xx_spisel_boot.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 DEIF A/S + * + * GPIO driver to set/clear SPISEL_BOOT pin on mpc83xx. + */ + +#include +#include +#include +#include + +struct mpc83xx_spisel_boot { + u32 __iomem *spi_cs; + ulong addr; + uint gpio_count; + ulong type; +}; + +static u32 gpio_mask(uint gpio) +{ + return (1U << (31 - (gpio))); +} + +static int mpc83xx_spisel_boot_direction_input(struct udevice *dev, uint gpio) +{ + return -EINVAL; +} + +static int mpc83xx_spisel_boot_set_value(struct udevice *dev, uint gpio, int value) +{ + struct mpc83xx_spisel_boot *data = dev_get_priv(dev); + + debug("%s: gpio=%d, value=%u, gpio_mask=0x%08x\n", __func__, + gpio, value, gpio_mask(gpio)); + + if (value) + setbits_be32(data->spi_cs, gpio_mask(gpio)); + else + clrbits_be32(data->spi_cs, gpio_mask(gpio)); + + return 0; +} + +static int mpc83xx_spisel_boot_direction_output(struct udevice *dev, uint gpio, int value) +{ + return 0; +} + +static int mpc83xx_spisel_boot_get_value(struct udevice *dev, uint gpio) +{ + struct mpc83xx_spisel_boot *data = dev_get_priv(dev); + + return !!(in_be32(data->spi_cs) & gpio_mask(gpio)); +} + +static int mpc83xx_spisel_boot_get_function(struct udevice *dev, uint gpio) +{ + return GPIOF_OUTPUT; +} + +#if CONFIG_IS_ENABLED(OF_CONTROL) +static int mpc83xx_spisel_boot_ofdata_to_platdata(struct udevice *dev) +{ + struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev); + fdt_addr_t addr; + u32 reg[2]; + + dev_read_u32_array(dev, "reg", reg, 2); + addr = dev_translate_address(dev, reg); + + plat->addr = addr; + plat->size = reg[1]; + plat->ngpios = dev_read_u32_default(dev, "ngpios", 1); + + return 0; +} +#endif + +static int mpc83xx_spisel_boot_platdata_to_priv(struct udevice *dev) +{ + struct mpc83xx_spisel_boot *priv = dev_get_priv(dev); + struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev); + unsigned long size = plat->size; + ulong driver_data = dev_get_driver_data(dev); + + if (size == 0) + size = 0x04; + + priv->addr = plat->addr; + priv->spi_cs = map_sysmem(plat->addr, size); + + if (!priv->spi_cs) + return -ENOMEM; + + priv->gpio_count = plat->ngpios; + + priv->type = driver_data; + + return 0; +} + +static int mpc83xx_spisel_boot_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct mpc83xx_spisel_boot *data = dev_get_priv(dev); + char name[32], *str; + + mpc83xx_spisel_boot_platdata_to_priv(dev); + + snprintf(name, sizeof(name), "MPC@%lx_", data->addr); + str = strdup(name); + + if (!str) + return -ENOMEM; + + uc_priv->bank_name = str; + uc_priv->gpio_count = data->gpio_count; + + return 0; +} + +static const struct dm_gpio_ops mpc83xx_spisel_boot_ops = { + .direction_input = mpc83xx_spisel_boot_direction_input, + .direction_output = mpc83xx_spisel_boot_direction_output, + .get_value = mpc83xx_spisel_boot_get_value, + .set_value = mpc83xx_spisel_boot_set_value, + .get_function = mpc83xx_spisel_boot_get_function, +}; + +static const struct udevice_id mpc83xx_spisel_boot_ids[] = { + { .compatible = "fsl,mpc8309-spisel-boot" }, + { .compatible = "fsl,mpc83xx-spisel-boot" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(spisel_boot_mpc83xx) = { + .name = "spisel_boot_mpc83xx", + .id = UCLASS_GPIO, + .ops = &mpc83xx_spisel_boot_ops, +#if CONFIG_IS_ENABLED(OF_CONTROL) + .ofdata_to_platdata = mpc83xx_spisel_boot_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct mpc8xxx_gpio_plat), + .of_match = mpc83xx_spisel_boot_ids, +#endif + .probe = mpc83xx_spisel_boot_probe, + .priv_auto_alloc_size = sizeof(struct mpc83xx_spisel_boot), +}; -- cgit v1.2.3 From 96e68c1621a416cf5b1e933206d23ff86b246fb4 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Tue, 11 Feb 2020 15:20:23 +0000 Subject: gazerbeam: add clocks property to SPI node Prepare for supporting setting different speeds in mpc8xxx_spi.c. Signed-off-by: Rasmus Villemoes --- arch/powerpc/dts/gdsys/mpc8308.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/powerpc/dts/gdsys/mpc8308.dtsi b/arch/powerpc/dts/gdsys/mpc8308.dtsi index 23e7403d911..1a319e23287 100644 --- a/arch/powerpc/dts/gdsys/mpc8308.dtsi +++ b/arch/powerpc/dts/gdsys/mpc8308.dtsi @@ -17,6 +17,7 @@ /dts-v1/; #include +#include / { compatible = "fsl,mpc8308rdb"; @@ -50,6 +51,11 @@ }; }; + socclocks: clocks { + compatible = "fsl,mpc8308-clk"; + #clock-cells = <1>; + }; + board_lbc: localbus@e0005000 { #address-cells = <2>; #size-cells = <1>; @@ -173,6 +179,7 @@ reg = <0x7000 0x1000>; interrupts = <16 0x8>; interrupt-parent = <&ipic>; + clocks = <&socclocks MPC83XX_CLK_CSB>; mode = "cpu"; }; -- cgit v1.2.3 From 1a7b462dee310e83b5ed45ff5a56aa348d07b03a Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Tue, 11 Feb 2020 15:20:24 +0000 Subject: mpc8xxx_spi: put max_cs to use Currently, max_cs is write-only; it's just set in mpc8xxx_spi_ofdata_to_platdata and not otherwise used. My mpc8309 was always resetting during an "sf probe 0". It turns out dm_gpio_set_dir_flags() was being called with garbage, since nothing had initialized priv->gpios[0] - our device tree used "cs-gpios" rather than "gpios", so gpio_request_list_by_name() had returned 0. That would have been a lot easier to figure out if the chip select index was sanity checked, so rename max_cs to cs_count, and reject a xfer with a too large cs index. Signed-off-by: Rasmus Villemoes --- drivers/spi/mpc8xxx_spi.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c index 1c7bf10f91e..ac4d0a9baef 100644 --- a/drivers/spi/mpc8xxx_spi.c +++ b/drivers/spi/mpc8xxx_spi.c @@ -35,7 +35,7 @@ enum { struct mpc8xxx_priv { spi8xxx_t *spi; struct gpio_desc gpios[16]; - int max_cs; + int cs_count; }; static inline u32 to_prescale_mod(u32 val) @@ -74,7 +74,7 @@ static int mpc8xxx_spi_ofdata_to_platdata(struct udevice *dev) if (ret < 0) return -EINVAL; - priv->max_cs = ret; + priv->cs_count = ret; return 0; } @@ -131,6 +131,11 @@ static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen, debug("%s: slave %s:%u dout %08X din %08X bitlen %u\n", __func__, bus->name, platdata->cs, *(uint *)dout, *(uint *)din, bitlen); + if (platdata->cs >= priv->cs_count) { + dev_err(dev, "chip select index %d too large (cs_count=%d)\n", + platdata->cs, priv->cs_count); + return -EINVAL; + } if (flags & SPI_XFER_BEGIN) mpc8xxx_spi_cs_activate(dev); -- cgit v1.2.3 From 391c40048b01dacd50243a594f74775a3ec60104 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Tue, 11 Feb 2020 15:20:25 +0000 Subject: mpc8xxx_spi: always use 8-bit characters, don't read or write garbage There are a few problems with the current driver. First, it unconditionally reads from dout/writes to din whether or not those pointers are NULL. So for example a simple "sf probe" ends up writing four bytes at address 0: => md.l 0x0 8 00000000: 45454545 45454545 05050505 05050505 EEEEEEEE........ 00000010: 00000000 00000000 07070707 07070707 ................ => sf probe 0 mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB53618 din 00000000 bitlen 8 mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 0FB536B8 bitlen 48 SF: Detected s25sl032p with page size 256 Bytes, erase size 64 KiB, total 4 MiB => md.l 0x0 8 00000000: ff000000 45454545 05050505 05050505 ....EEEE........ 00000010: 00000000 00000000 07070707 07070707 ................ (here I've change the first debug statement to a printf, and made it print the din/dout pointers rather than the uints they point at). Second, as we can also see above, it always writes a full 32 bits, even if a smaller amount was requested. So for example => mw.l $loadaddr 0xaabbccdd 8 => md.l $loadaddr 8 02000000: aabbccdd aabbccdd aabbccdd aabbccdd ................ 02000010: aabbccdd aabbccdd aabbccdd aabbccdd ................ => sf read $loadaddr 0x400 6 device 0 offset 0x400, size 0x6 mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40 mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 48 SF: 6 bytes @ 0x400 Read: OK => sf read 0x02000010 0x400 8 device 0 offset 0x400, size 0x8 mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB53848 din 00000000 bitlen 40 mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000010 bitlen 64 SF: 8 bytes @ 0x400 Read: OK => md.l $loadaddr 8 02000000: 45454545 45450000 aabbccdd aabbccdd EEEEEE.......... 02000010: 45454545 45454545 aabbccdd aabbccdd EEEEEEEE........ Finally, when the bitlen is 24 mod 32 (e.g. requesting to read 3 or 7 bytes), the last three bytes and up being the wrong ones, since the driver does a full 32 bit read and then shifts the wrong byte out: => mw.l $loadaddr 0xaabbccdd 4 => md.l $loadaddr 4 02000000: aabbccdd aabbccdd aabbccdd aabbccdd ................ => sf read $loadaddr 0x444 10 device 0 offset 0x444, size 0x10 mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40 mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 128 SF: 16 bytes @ 0x444 Read: OK => md.l $loadaddr 4 02000000: 552d426f 6f742032 3031392e 30342d30 U-Boot 2019.04-0 => mw.l $loadaddr 0xaabbccdd 4 => sf read $loadaddr 0x444 0xb device 0 offset 0x444, size 0xb mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40 mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 88 SF: 11 bytes @ 0x444 Read: OK => md.l $loadaddr 4 02000000: 552d426f 6f742032 31392e00 aabbccdd U-Boot 219...... Fix all of that by always using a character size of 8, and reject transfers that are not a whole number of bytes. While it ends being more work for the CPU, we're mostly bounded by the speed of the SPI bus, and we avoid writing to the mode register in every loop. Based on work by Klaus H. Sørensen. Cc: Klaus H. Sorensen Signed-off-by: Rasmus Villemoes --- drivers/spi/mpc8xxx_spi.c | 80 ++++++++++++++++------------------------------- 1 file changed, 27 insertions(+), 53 deletions(-) diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c index ac4d0a9baef..8ef24514112 100644 --- a/drivers/spi/mpc8xxx_spi.c +++ b/drivers/spi/mpc8xxx_spi.c @@ -27,6 +27,7 @@ enum { SPI_MODE_EN = BIT(31 - 7), /* Enable interface */ SPI_MODE_LEN_MASK = 0xf00000, + SPI_MODE_LEN_SHIFT = 20, SPI_MODE_PM_MASK = 0xf0000, SPI_COM_LST = BIT(31 - 9), @@ -43,23 +44,8 @@ static inline u32 to_prescale_mod(u32 val) return (min(val, (u32)15) << 16); } -static void set_char_len(spi8xxx_t *spi, u32 val) -{ - clrsetbits_be32(&spi->mode, SPI_MODE_LEN_MASK, (val << 20)); -} - #define SPI_TIMEOUT 1000 -static int __spi_set_speed(spi8xxx_t *spi, uint speed) -{ - /* TODO(mario.six@gdsys.cc): This only ever sets one fixed speed */ - - /* Use SYSCLK / 8 (16.67MHz typ.) */ - clrsetbits_be32(&spi->mode, SPI_MODE_PM_MASK, to_prescale_mod(1)); - - return 0; -} - static int mpc8xxx_spi_ofdata_to_platdata(struct udevice *dev) { struct mpc8xxx_priv *priv = dev_get_priv(dev); @@ -82,14 +68,22 @@ static int mpc8xxx_spi_ofdata_to_platdata(struct udevice *dev) static int mpc8xxx_spi_probe(struct udevice *dev) { struct mpc8xxx_priv *priv = dev_get_priv(dev); + spi8xxx_t *spi = priv->spi; /* * SPI pins on the MPC83xx are not muxed, so all we do is initialize * some registers */ - out_be32(&priv->spi->mode, SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN); + out_be32(&priv->spi->mode, SPI_MODE_REV | SPI_MODE_MS); + + /* set len to 8 bits */ + setbits_be32(&spi->mode, (8 - 1) << SPI_MODE_LEN_SHIFT); - __spi_set_speed(priv->spi, 16666667); + /* TODO(mario.six@gdsys.cc): This only ever sets one fixed speed */ + /* Use SYSCLK / 8 (16.67MHz typ.) */ + clrsetbits_be32(&spi->mode, SPI_MODE_PM_MASK, to_prescale_mod(1)); + + setbits_be32(&spi->mode, SPI_MODE_EN); /* Clear all SPI events */ setbits_be32(&priv->spi->event, 0xffffffff); @@ -126,50 +120,35 @@ static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen, struct mpc8xxx_priv *priv = dev_get_priv(bus); spi8xxx_t *spi = priv->spi; struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev); - u32 tmpdin = 0; - int num_blks = DIV_ROUND_UP(bitlen, 32); + u32 tmpdin = 0, tmpdout = 0, n; + const u8 *cout = dout; + u8 *cin = din; debug("%s: slave %s:%u dout %08X din %08X bitlen %u\n", __func__, - bus->name, platdata->cs, *(uint *)dout, *(uint *)din, bitlen); + bus->name, platdata->cs, (uint)dout, (uint)din, bitlen); if (platdata->cs >= priv->cs_count) { dev_err(dev, "chip select index %d too large (cs_count=%d)\n", platdata->cs, priv->cs_count); return -EINVAL; } + if (bitlen % 8) { + printf("*** spi_xfer: bitlen must be multiple of 8\n"); + return -ENOTSUPP; + } if (flags & SPI_XFER_BEGIN) mpc8xxx_spi_cs_activate(dev); /* Clear all SPI events */ setbits_be32(&spi->event, 0xffffffff); + n = bitlen / 8; - /* Handle data in 32-bit chunks */ - while (num_blks--) { - u32 tmpdout = 0; - uchar xfer_bitlen = (bitlen >= 32 ? 32 : bitlen); + /* Handle data in 8-bit chunks */ + while (n--) { ulong start; - clrbits_be32(&spi->mode, SPI_MODE_EN); - - /* Set up length for this transfer */ - - if (bitlen <= 4) /* 4 bits or less */ - set_char_len(spi, 3); - else if (bitlen <= 16) /* at most 16 bits */ - set_char_len(spi, bitlen - 1); - else /* more than 16 bits -> full 32 bit transfer */ - set_char_len(spi, 0); - - setbits_be32(&spi->mode, SPI_MODE_EN); - - /* Shift data so it's msb-justified */ - tmpdout = *(u32 *)dout >> (32 - xfer_bitlen); - - if (bitlen > 32) { - /* Set up the next iteration if sending > 32 bits */ - bitlen -= 32; - dout += 4; - } + if (cout) + tmpdout = *cout++; /* Write the data out */ out_be32(&spi->tx, tmpdout); @@ -193,11 +172,8 @@ static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen, tmpdin = in_be32(&spi->rx); setbits_be32(&spi->event, SPI_EV_NE); - *(u32 *)din = (tmpdin << (32 - xfer_bitlen)); - if (xfer_bitlen == 32) { - /* Advance output buffer by 32 bits */ - din += 4; - } + if (cin) + *cin++ = tmpdin; /* * Only bail when we've had both NE and NF events. @@ -228,9 +204,7 @@ static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen, static int mpc8xxx_spi_set_speed(struct udevice *dev, uint speed) { - struct mpc8xxx_priv *priv = dev_get_priv(dev); - - return __spi_set_speed(priv->spi, speed); + return 0; } static int mpc8xxx_spi_set_mode(struct udevice *dev, uint mode) -- cgit v1.2.3 From 4856cc7a972a7679cdbb33532ad932a3e865b18e Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Tue, 11 Feb 2020 15:20:25 +0000 Subject: mpc8xxx_spi: implement real ->set_speed Not all boards have the same CSB frequency, nor do every SPI slave necessarily support running at 16.7 MHz. So implement ->set_speed; that also allows using a smaller PM (i.e., 0) for slaves that do support a higher speed. Based on work by Klaus H. Sørensen. Cc: Klaus H. Sorensen Signed-off-by: Rasmus Villemoes --- drivers/spi/mpc8xxx_spi.c | 64 +++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 53 insertions(+), 11 deletions(-) diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c index 8ef24514112..1bde31ad349 100644 --- a/drivers/spi/mpc8xxx_spi.c +++ b/drivers/spi/mpc8xxx_spi.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -28,6 +29,7 @@ enum { SPI_MODE_LEN_MASK = 0xf00000, SPI_MODE_LEN_SHIFT = 20, + SPI_MODE_PM_SHIFT = 16, SPI_MODE_PM_MASK = 0xf0000, SPI_COM_LST = BIT(31 - 9), @@ -37,24 +39,19 @@ struct mpc8xxx_priv { spi8xxx_t *spi; struct gpio_desc gpios[16]; int cs_count; + ulong clk_rate; }; -static inline u32 to_prescale_mod(u32 val) -{ - return (min(val, (u32)15) << 16); -} - #define SPI_TIMEOUT 1000 static int mpc8xxx_spi_ofdata_to_platdata(struct udevice *dev) { struct mpc8xxx_priv *priv = dev_get_priv(dev); + struct clk clk; int ret; priv->spi = (spi8xxx_t *)dev_read_addr(dev); - /* TODO(mario.six@gdsys.cc): Read clock and save the value */ - ret = gpio_request_list_by_name(dev, "gpios", priv->gpios, ARRAY_SIZE(priv->gpios), GPIOD_IS_OUT | GPIOD_ACTIVE_LOW); if (ret < 0) @@ -62,6 +59,18 @@ static int mpc8xxx_spi_ofdata_to_platdata(struct udevice *dev) priv->cs_count = ret; + ret = clk_get_by_index(dev, 0, &clk); + if (ret) { + dev_err(dev, "%s: clock not defined\n", __func__); + return ret; + } + + priv->clk_rate = clk_get_rate(&clk); + if (!priv->clk_rate) { + dev_err(dev, "%s: failed to get clock rate\n", __func__); + return -EINVAL; + } + return 0; } @@ -79,10 +88,6 @@ static int mpc8xxx_spi_probe(struct udevice *dev) /* set len to 8 bits */ setbits_be32(&spi->mode, (8 - 1) << SPI_MODE_LEN_SHIFT); - /* TODO(mario.six@gdsys.cc): This only ever sets one fixed speed */ - /* Use SYSCLK / 8 (16.67MHz typ.) */ - clrsetbits_be32(&spi->mode, SPI_MODE_PM_MASK, to_prescale_mod(1)); - setbits_be32(&spi->mode, SPI_MODE_EN); /* Clear all SPI events */ @@ -204,6 +209,43 @@ static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen, static int mpc8xxx_spi_set_speed(struct udevice *dev, uint speed) { + struct mpc8xxx_priv *priv = dev_get_priv(dev); + spi8xxx_t *spi = priv->spi; + u32 bits, mask, div16, pm; + u32 mode; + ulong clk; + + clk = priv->clk_rate; + if (clk / 64 > speed) { + div16 = SPI_MODE_DIV16; + clk /= 16; + } else { + div16 = 0; + } + pm = (clk - 1)/(4*speed) + 1; + if (pm > 16) { + dev_err(dev, "requested speed %u too small\n", speed); + return -EINVAL; + } + pm--; + + bits = div16 | (pm << SPI_MODE_PM_SHIFT); + mask = SPI_MODE_DIV16 | SPI_MODE_PM_MASK; + mode = in_be32(&spi->mode); + if ((mode & mask) != bits) { + /* Must clear mode[EN] while changing speed. */ + mode &= ~(mask | SPI_MODE_EN); + out_be32(&spi->mode, mode); + mode |= bits; + out_be32(&spi->mode, mode); + mode |= SPI_MODE_EN; + out_be32(&spi->mode, mode); + } + + debug("requested speed %u, set speed to %lu/(%s4*%u) == %lu\n", + speed, priv->clk_rate, div16 ? "16*" : "", pm + 1, + clk/(4*(pm + 1))); + return 0; } -- cgit v1.2.3 From 7f6b0f3357bd25c7ed23f8f5a76a99ab9a0fd398 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Mar 2020 15:01:29 +0100 Subject: net: macb: Fix incorrect write function name when MACB_ZYNQ is enabled. When MACB_ZYNQ is enabled there is compilation warnings drivers/net/macb.c: In function ‘_macb_init’: drivers/net/macb.h:675:33: error: ‘MACB_DMACFG’ undeclared (first use in this function); did you mean ‘MACB_MCF’? writel((value), (port)->regs + MACB_##reg) ^~~~~ It has been caused by changing macros name by commit below. Fixes: 6c636514d499 ("net: macb: sync header definitions as taken from Linux") Signed-off-by: Michal Simek Acked-by: Joe Hershberger --- drivers/net/macb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 631b53b0930..bd588cab06b 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -807,7 +807,7 @@ static int _macb_init(struct macb_device *macb, const char *name) macb->next_rx_tail = 0; #ifdef CONFIG_MACB_ZYNQ - macb_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT); + gem_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT); #endif macb_writel(macb, RBQP, macb->rx_ring_dma); -- cgit v1.2.3 From 7e5702282374138507ab3c08dfc1b28dd9ec2bd7 Mon Sep 17 00:00:00 2001 From: Eugeniy Paltsev Date: Mon, 30 Mar 2020 22:44:43 +0300 Subject: ARC: IO: add volatile to accessors We must use 'volatile' in C-version read/write IO accessors implementation to avoid merging several reads (writes) into one read (write), or optimizing them out by compiler. Fixes commit 07906b3dad15 ("ARC: Switch to generic accessors") Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin --- arch/arc/include/asm/io.h | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h index 70d050590de..1f1ae889f3a 100644 --- a/arch/arc/include/asm/io.h +++ b/arch/arc/include/asm/io.h @@ -54,15 +54,21 @@ static inline void sync(void) /* Not yet implemented */ } -#define __arch_getb(a) (*(unsigned char *)(a)) -#define __arch_getw(a) (*(unsigned short *)(a)) -#define __arch_getl(a) (*(unsigned int *)(a)) -#define __arch_getq(a) (*(unsigned long long *)(a)) - -#define __arch_putb(v, a) (*(unsigned char *)(a) = (v)) -#define __arch_putw(v, a) (*(unsigned short *)(a) = (v)) -#define __arch_putl(v, a) (*(unsigned int *)(a) = (v)) -#define __arch_putq(v, a) (*(unsigned long long *)(a) = (v)) +/* + * We must use 'volatile' in C-version read/write IO accessors implementation + * to avoid merging several reads (writes) into one read (write), or optimizing + * them out by compiler. + */ +#define __arch_getb(a) (*(volatile u8 *)(a)) +#define __arch_getw(a) (*(volatile u16 *)(a)) +#define __arch_getl(a) (*(volatile u32 *)(a)) +#define __arch_getq(a) (*(volatile u64 *)(a)) + +#define __arch_putb(v, a) (*(volatile u8 *)(a) = (v)) +#define __arch_putw(v, a) (*(volatile u16 *)(a) = (v)) +#define __arch_putl(v, a) (*(volatile u32 *)(a) = (v)) +#define __arch_putq(v, a) (*(volatile u64 *)(a) = (v)) + #define __raw_writeb(v, a) __arch_putb(v, a) #define __raw_writew(v, a) __arch_putw(v, a) -- cgit v1.2.3 From e9a23c98c9dc8eccc696e5ca6ccd94bacdb32c7d Mon Sep 17 00:00:00 2001 From: Eugeniy Paltsev Date: Mon, 30 Mar 2020 22:44:44 +0300 Subject: ARC: IO: add compiler barriers to IO accessors We must use compiler barriers in C-version read/write IO accessors before and after operation (read or write) so it won't be reordered by compiler. Fixes commit 07906b3dad15 ("ARC: Switch to generic accessors") Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin --- arch/arc/include/asm/io.h | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h index 1f1ae889f3a..a4171a3e5cc 100644 --- a/arch/arc/include/asm/io.h +++ b/arch/arc/include/asm/io.h @@ -9,6 +9,12 @@ #include #include +/* + * Compiler barrier. It prevents compiler from reordering instructions before + * and after it. It doesn't prevent HW (CPU) from any reordering though. + */ +#define __comp_b() asm volatile("" : : : "memory") + #ifdef __ARCHS__ /* @@ -45,8 +51,8 @@ #define __iormb() rmb() #define __iowmb() wmb() #else -#define __iormb() asm volatile("" : : : "memory") -#define __iowmb() asm volatile("" : : : "memory") +#define __iormb() __comp_b() +#define __iowmb() __comp_b() #endif static inline void sync(void) @@ -58,16 +64,18 @@ static inline void sync(void) * We must use 'volatile' in C-version read/write IO accessors implementation * to avoid merging several reads (writes) into one read (write), or optimizing * them out by compiler. + * We must use compiler barriers before and after operation (read or write) so + * it won't be reordered by compiler. */ -#define __arch_getb(a) (*(volatile u8 *)(a)) -#define __arch_getw(a) (*(volatile u16 *)(a)) -#define __arch_getl(a) (*(volatile u32 *)(a)) -#define __arch_getq(a) (*(volatile u64 *)(a)) - -#define __arch_putb(v, a) (*(volatile u8 *)(a) = (v)) -#define __arch_putw(v, a) (*(volatile u16 *)(a) = (v)) -#define __arch_putl(v, a) (*(volatile u32 *)(a) = (v)) -#define __arch_putq(v, a) (*(volatile u64 *)(a) = (v)) +#define __arch_getb(a) ({ u8 __v; __comp_b(); __v = *(volatile u8 *)(a); __comp_b(); __v; }) +#define __arch_getw(a) ({ u16 __v; __comp_b(); __v = *(volatile u16 *)(a); __comp_b(); __v; }) +#define __arch_getl(a) ({ u32 __v; __comp_b(); __v = *(volatile u32 *)(a); __comp_b(); __v; }) +#define __arch_getq(a) ({ u64 __v; __comp_b(); __v = *(volatile u64 *)(a); __comp_b(); __v; }) + +#define __arch_putb(v, a) ({ __comp_b(); *(volatile u8 *)(a) = (v); __comp_b(); }) +#define __arch_putw(v, a) ({ __comp_b(); *(volatile u16 *)(a) = (v); __comp_b(); }) +#define __arch_putl(v, a) ({ __comp_b(); *(volatile u32 *)(a) = (v); __comp_b(); }) +#define __arch_putq(v, a) ({ __comp_b(); *(volatile u64 *)(a) = (v); __comp_b(); }) #define __raw_writeb(v, a) __arch_putb(v, a) -- cgit v1.2.3 From 45bd649511155b5b5a40851ca96036636cb95e23 Mon Sep 17 00:00:00 2001 From: Eugeniy Paltsev Date: Mon, 30 Mar 2020 22:44:45 +0300 Subject: ARC: IO: add MB for __raw_* memory accessors We add memory barriers for __raw_readX / __raw_writeX accessors same way as it is done for readX and writeX accessors as lots of U-boot driver uses __raw_readX / __raw_writeX instead of proper accessor with barrier. It will save us from lot's of debugging in the future and it is OK as U-Boot is not that performance oriented as real run-time software like OS or user bare-metal app so we may afford being not super fast as we only being executed once. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin --- arch/arc/include/asm/io.h | 58 ++++++++++++++++++++++++++++------------------- 1 file changed, 35 insertions(+), 23 deletions(-) diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h index a4171a3e5cc..6adc0ed42ba 100644 --- a/arch/arc/include/asm/io.h +++ b/arch/arc/include/asm/io.h @@ -78,21 +78,29 @@ static inline void sync(void) #define __arch_putq(v, a) ({ __comp_b(); *(volatile u64 *)(a) = (v); __comp_b(); }) -#define __raw_writeb(v, a) __arch_putb(v, a) -#define __raw_writew(v, a) __arch_putw(v, a) -#define __raw_writel(v, a) __arch_putl(v, a) -#define __raw_writeq(v, a) __arch_putq(v, a) +/* + * We add memory barriers for __raw_readX / __raw_writeX accessors same way as + * it is done for readX and writeX accessors as lots of U-boot driver uses + * __raw_readX / __raw_writeX instead of proper accessor with barrier. + */ +#define __raw_writeb(v, c) ({ __iowmb(); __arch_putb(v, c); }) +#define __raw_writew(v, c) ({ __iowmb(); __arch_putw(v, c); }) +#define __raw_writel(v, c) ({ __iowmb(); __arch_putl(v, c); }) +#define __raw_writeq(v, c) ({ __iowmb(); __arch_putq(v, c); }) + +#define __raw_readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; }) +#define __raw_readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; }) +#define __raw_readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; }) +#define __raw_readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; }) -#define __raw_readb(a) __arch_getb(a) -#define __raw_readw(a) __arch_getw(a) -#define __raw_readl(a) __arch_getl(a) -#define __raw_readq(a) __arch_getq(a) static inline void __raw_writesb(unsigned long addr, const void *data, int bytelen) { u8 *buf = (uint8_t *)data; + __iowmb(); + while (bytelen--) __arch_putb(*buf++, addr); } @@ -102,6 +110,8 @@ static inline void __raw_writesw(unsigned long addr, const void *data, { u16 *buf = (uint16_t *)data; + __iowmb(); + while (wordlen--) __arch_putw(*buf++, addr); } @@ -111,6 +121,8 @@ static inline void __raw_writesl(unsigned long addr, const void *data, { u32 *buf = (uint32_t *)data; + __iowmb(); + while (longlen--) __arch_putl(*buf++, addr); } @@ -121,6 +133,8 @@ static inline void __raw_readsb(unsigned long addr, void *data, int bytelen) while (bytelen--) *buf++ = __arch_getb(addr); + + __iormb(); } static inline void __raw_readsw(unsigned long addr, void *data, int wordlen) @@ -129,6 +143,8 @@ static inline void __raw_readsw(unsigned long addr, void *data, int wordlen) while (wordlen--) *buf++ = __arch_getw(addr); + + __iormb(); } static inline void __raw_readsl(unsigned long addr, void *data, int longlen) @@ -137,6 +153,8 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) while (longlen--) *buf++ = __arch_getl(addr); + + __iormb(); } /* @@ -144,21 +162,15 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) * ordering rules but do not guarantee any ordering relative to Normal memory * accesses. */ -#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; }) -#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \ - __raw_readw(c)); __r; }) -#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ - __raw_readl(c)); __r; }) -#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \ - __raw_readq(c)); __r; }) - -#define writeb_relaxed(v, c) ((void)__raw_writeb((v), (c))) -#define writew_relaxed(v, c) ((void)__raw_writew((__force u16) \ - cpu_to_le16(v), (c))) -#define writel_relaxed(v, c) ((void)__raw_writel((__force u32) \ - cpu_to_le32(v), (c))) -#define writeq_relaxed(v, c) ((void)__raw_writeq((__force u64) \ - cpu_to_le64(v), (c))) +#define readb_relaxed(c) ({ u8 __r = __arch_getb(c); __r; }) +#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16)__arch_getw(c)); __r; }) +#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__arch_getl(c)); __r; }) +#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__arch_getq(c)); __r; }) + +#define writeb_relaxed(v, c) ((void)__arch_putb((v), (c))) +#define writew_relaxed(v, c) ((void)__arch_putw((__force u16)cpu_to_le16(v), (c))) +#define writel_relaxed(v, c) ((void)__arch_putl((__force u32)cpu_to_le32(v), (c))) +#define writeq_relaxed(v, c) ((void)__arch_putq((__force u64)cpu_to_le64(v), (c))) /* * MMIO can also get buffered/optimized in micro-arch, so barriers needed -- cgit v1.2.3 From 81169ca3cc32733214c14b8751e049b345b6280f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 31 Mar 2020 19:51:23 +0200 Subject: ARM: dts: stm32: Repair SD1 pre-reloc pinmux DT node on AV96 The sdmmc1_dir_pins_a: sdmmc1-dir-0 layout changed in commit 35a54d41d9d4 ("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") such that pins{}; became pins1{};pins2{};, however the SPL extras were not updated to reflect that change. Fix this. This fixes booting from SD1 X9 slot on the AV96 board. Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay Fixes: 35a54d41d9d4 ("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") Signed-off-by: Marek Vasut Cc: Manivannan Sadhasivam Cc: Patrick Delaunay Cc: Patrice Chotard --- arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi index d6dc7463653..8dcd8866e8d 100644 --- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi @@ -152,7 +152,10 @@ &sdmmc1_dir_pins_a { u-boot,dm-spl; - pins { + pins1 { + u-boot,dm-spl; + }; + pins2 { u-boot,dm-spl; }; }; -- cgit v1.2.3 From 4fdbe6487daace57fc3caa71ea848a71136548b3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 31 Mar 2020 19:51:24 +0200 Subject: ARM: dts: stm32: Add alternate pinmux for SDMMC1 direction pins Add another mux option for SDMMC1 direction pins, in particular SDMMC1_D123DIR, this is used on AV96 board. Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay Signed-off-by: Marek Vasut Cc: Manivannan Sadhasivam Cc: Patrick Delaunay Cc: Patrice Chotard --- arch/arm/dts/stm32mp157-pinctrl.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi index 81a363d93db..6842d4cdca9 100644 --- a/arch/arm/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi @@ -832,6 +832,30 @@ }; }; + sdmmc1_dir_pins_b: sdmmc1-dir-1 { + pins1 { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + ; /* SDMMC1_CDIR */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2{ + pinmux = ; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 { + pins { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + , /* SDMMC1_CDIR */ + ; /* SDMMC1_CKIN */ + }; + }; + sdmmc2_b4_pins_a: sdmmc2-b4-0 { pins1 { pinmux = , /* SDMMC2_D0 */ -- cgit v1.2.3 From 45fa59b407163abbb553d7cd333b1302e878683a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 31 Mar 2020 19:51:25 +0200 Subject: ARM: dts: stm32: Repair SDMMC1 operation on AV96 The SD uses different pinmux for the D123DIRline, use such a pinmux, otherwise there is a pinmux collision on the AV96. Add missing SD voltage regulator switch and enable SDR104 operation. Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay Signed-off-by: Marek Vasut Cc: Manivannan Sadhasivam Cc: Patrick Delaunay Cc: Patrice Chotard --- arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 2 +- arch/arm/dts/stm32mp157a-avenger96.dts | 25 +++++++++++++++++++++---- 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi index 8dcd8866e8d..47bfbb8d77c 100644 --- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi @@ -150,7 +150,7 @@ }; }; -&sdmmc1_dir_pins_a { +&sdmmc1_dir_pins_b { u-boot,dm-spl; pins1 { u-boot,dm-spl; diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 3065593bf2a..1e9b45b69da 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -76,6 +76,20 @@ default-state = "off"; }; }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; }; ðernet0 { @@ -296,15 +310,18 @@ &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - broken-cd; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>; + disable-wp; st,sig-dir; st,neg-edge; st,use-ckin; + sd-uhs-sdr104; bus-width = <4>; vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; status = "okay"; }; -- cgit v1.2.3 From 5fdcba64027fade59dd8ec5b2dd54b1294b3fd76 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 31 Mar 2020 19:51:26 +0200 Subject: ARM: dts: stm32: Add alternate pinmux for SDMMC2 pins 4-7 Add another mux option for SDMMC2 pins 4..7, this is used on AV96 board. Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay Signed-off-by: Marek Vasut Cc: Manivannan Sadhasivam Cc: Patrick Delaunay Cc: Patrice Chotard --- arch/arm/dts/stm32mp157-pinctrl.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi index 6842d4cdca9..964e4910ec3 100644 --- a/arch/arm/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi @@ -931,6 +931,27 @@ }; }; + sdmmc2_d47_pins_b: sdmmc2-d47-1 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + spdifrx_pins_a: spdifrx-0 { pins { pinmux = ; /* SPDIF_IN1 */ -- cgit v1.2.3 From df7f49ca27b8951e440a36dd0ef10b1af2a68c6a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 31 Mar 2020 19:51:27 +0200 Subject: ARM: dts: stm32: Repair SDMMC2 operation The eMMC uses different pinmux for the top four data lines, use such a pinmux, otherwise it takes a very long time until the test for 8bit operation times out. And this is the correct pinmux per schematic too. Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay Signed-off-by: Marek Vasut Cc: Manivannan Sadhasivam Cc: Patrick Delaunay Cc: Patrice Chotard --- arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 2 +- arch/arm/dts/stm32mp157a-avenger96.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi index 47bfbb8d77c..2c7dc509a33 100644 --- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi @@ -174,7 +174,7 @@ }; }; -&sdmmc2_d47_pins_a { +&sdmmc2_d47_pins_b { u-boot,dm-spl; pins { u-boot,dm-spl; diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 1e9b45b69da..3fca1ed56d7 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -327,7 +327,7 @@ &sdmmc2 { pinctrl-names = "default"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; non-removable; no-sd; no-sdio; -- cgit v1.2.3 From 2f0b5d930d3b2100917077ef7217e77c3c9ae956 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 31 Mar 2020 19:51:28 +0200 Subject: ARM: dts: stm32: Add QSPI NOR on AV96 The DH Electronics DHCOR SOM has QSPI NOR on the SoM itself, add it into the DT. Signed-off-by: Marek Vasut Reviewed-by: Patrick Delaunay Cc: Manivannan Sadhasivam Cc: Patrick Delaunay Cc: Patrice Chotard Change-Id: Ia7c454c496f50e3fc4851ec1154f3641c416e98e --- arch/arm/dts/stm32mp157a-avenger96.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 3fca1ed56d7..023390a6622 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -20,6 +20,7 @@ mmc0 = &sdmmc1; serial0 = &uart4; serial1 = &uart7; + spi0 = &qspi; }; chosen { @@ -300,6 +301,25 @@ vdd_3v3_usbfs-supply = <&vdd_usb>; }; +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x200000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + &rng1 { status = "okay"; }; -- cgit v1.2.3 From f19312e5f400b1eb23252fa6d9e49a1e5512b448 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 31 Mar 2020 19:51:29 +0200 Subject: ARM: dts: stm32: Use DT alias for the configuration EEPROM Use DT /aliases node to establish a stable phandle to the configuration EEPROM. This permits the configuration EEPROM to be moved e.g. to a different address or a different bus. Adjust the board code to handle new phandle lookup. Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay Signed-off-by: Marek Vasut Cc: Manivannan Sadhasivam Cc: Patrick Delaunay Cc: Patrice Chotard --- arch/arm/dts/stm32mp15xx-dhcom.dtsi | 6 +++++- board/dhelectronics/dh_stm32mp1/board.c | 15 +++++++-------- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi index bed69c97b6b..e5be0a79ac5 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi @@ -10,6 +10,10 @@ #include / { + aliases { + eeprom0 = &eeprom0; + }; + memory@c0000000 { device_type = "memory"; reg = <0xC0000000 0x40000000>; @@ -187,7 +191,7 @@ }; }; - eeprom@50 { + eeprom0: eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; pagesize = <16>; diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index b6636969839..7bcd713a862 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -78,22 +78,21 @@ DECLARE_GLOBAL_DATA_PTR; int setup_mac_address(void) { - struct udevice *dev; - ofnode eeprom; unsigned char enetaddr[6]; - int ret; + struct udevice *dev; + int off, ret; ret = eth_env_get_enetaddr("ethaddr", enetaddr); if (ret) /* ethaddr is already set */ return 0; - eeprom = ofnode_path("/soc/i2c@5c002000/eeprom@50"); - if (!ofnode_valid(eeprom)) { - printf("Invalid hardware path to EEPROM!\n"); - return -ENODEV; + off = fdt_path_offset(gd->fdt_blob, "eeprom0"); + if (off < 0) { + printf("%s: No eeprom0 path offset\n", __func__); + return off; } - ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev); + ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev); if (ret) { printf("Cannot find EEPROM!\n"); return ret; -- cgit v1.2.3 From e182dcaa1ba8ff3e81a185d194b0f59b5a256072 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 31 Mar 2020 19:51:30 +0200 Subject: ARM: dts: stm32: Add configuration EEPROM on AV96 The board has an EEPROM on the same I2C bus as PMIC, at address 0x53. The EEPROM contains the board MAC address. Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay Signed-off-by: Marek Vasut Cc: Manivannan Sadhasivam Cc: Patrick Delaunay Cc: Patrice Chotard Change-Id: I340a0675c11e4599968b2e3ef0515fb8da8d7b42 --- arch/arm/dts/stm32mp157a-avenger96.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 023390a6622..4dbabb3a0d8 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -16,6 +16,7 @@ compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157"; aliases { + eeprom0 = &eeprom0; ethernet0 = ðernet0; mmc0 = &sdmmc1; serial0 = &uart4; @@ -289,6 +290,12 @@ status = "disabled"; }; }; + + eeprom0: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; }; &iwdg2 { -- cgit v1.2.3 From 955de5111112fb72f08b4c1914429c703138a6ab Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 31 Mar 2020 19:51:31 +0200 Subject: ARM: dts: stm32: Add alternate pinmux for ethernet RGMII Add another mux option for DWMAC RGMII, this is used on AV96 board. Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay Signed-off-by: Marek Vasut Cc: Manivannan Sadhasivam Cc: Patrick Delaunay Cc: Patrice Chotard --- arch/arm/dts/stm32mp157-pinctrl.dtsi | 51 ++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi index 964e4910ec3..422dad1ddd2 100644 --- a/arch/arm/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi @@ -288,6 +288,57 @@ }; }; + ethernet0_rgmii_pins_b: rgmii-1 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = ; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_pins_sleep_b: rgmii-sleep-1 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + }; + }; + fmc_pins_a: fmc-0 { pins1 { pinmux = , /* FMC_NOE */ -- cgit v1.2.3 From 6bb45d08cbce1375925a6babef0fa9c7d905cc23 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 31 Mar 2020 19:51:32 +0200 Subject: ARM: dts: stm32: Repair ethernet operation on AV96 The AV96 RGMII uses different pinmux for ETH_RGMII_TXD0, ETH_RGMII_RXD2 and ETH_RGMII_TX_CTL. Use the correct pinmux to make ethernet operational. Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay Signed-off-by: Marek Vasut Cc: Manivannan Sadhasivam Cc: Patrick Delaunay Cc: Patrice Chotard --- arch/arm/dts/stm32mp157a-avenger96.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 4dbabb3a0d8..e3f2952c829 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -96,8 +96,8 @@ ðernet0 { status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; + pinctrl-0 = <ðernet0_rgmii_pins_b>; + pinctrl-1 = <ðernet0_rgmii_pins_sleep_b>; pinctrl-names = "default", "sleep"; phy-mode = "rgmii"; max-speed = <1000>; -- cgit v1.2.3 From 4c8e4c615280b91b76bb0fec3f6707b84e467267 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 31 Mar 2020 19:51:33 +0200 Subject: ARM: dts: stm32: Add missing ethernet PHY reset on AV96 Add PHY reset GPIO on AV96 ethernet PHY. Signed-off-by: Marek Vasut Cc: Manivannan Sadhasivam Cc: Patrick Delaunay Cc: Patrice Chotard --- arch/arm/dts/stm32mp157a-avenger96.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index e3f2952c829..27d407a867e 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -102,6 +102,7 @@ phy-mode = "rgmii"; max-speed = <1000>; phy-handle = <&phy0>; + phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; mdio0 { #address-cells = <1>; -- cgit v1.2.3 From 2f3c4b8a0f303edbea9fc112a49e546cf03776b0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 31 Mar 2020 19:51:34 +0200 Subject: ARM: dts: stm32: Repair PMIC configuration on AV96 The core and vdd PMIC buck regulators were misconfigured, which caused instability of the board and malfunction of high-speed interfaces, like the RGMII. Configure the PMIC correctly to repair these problems. Also, model the missing Enpirion EP53A8LQI on the DHCOR SoM as a fixed regulator. Reviewed-by: Patrice Chotard Signed-off-by: Marek Vasut Cc: Manivannan Sadhasivam Cc: Patrick Delaunay Cc: Patrice Chotard --- arch/arm/dts/stm32mp157a-avenger96.dts | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 27d407a867e..1f32395e71a 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -92,6 +92,17 @@ states = <1800000 0x1>, <2900000 0x0>; }; + + /* Enpirion EP3A8LQI U2 on the DHCOR */ + vdd_io: regulator-buck-io { + compatible = "regulator-fixed"; + regulator-name = "buck-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd>; + }; }; ðernet0 { @@ -168,7 +179,7 @@ vddcore: buck1 { regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <1350000>; regulator-always-on; regulator-initial-mode = <0>; @@ -186,8 +197,8 @@ vdd: buck3 { regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; regulator-always-on; st,mask_reset; regulator-initial-mode = <0>; @@ -269,6 +280,7 @@ regulator-name = "vbus_otg"; interrupts = ; interrupt-parent = <&pmic>; + regulator-active-discharge = <1>; }; vbus_sw: pwr_sw2 { @@ -305,7 +317,7 @@ }; &pwr_regulators { - vdd-supply = <&vdd>; + vdd-supply = <&vdd_io>; vdd_3v3_usbfs-supply = <&vdd_usb>; }; -- cgit v1.2.3 From 390b26dc270aa3159df0c31775f91cd374a3dd3a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 18 Mar 2020 11:43:55 -0600 Subject: image: Correct comment for fit_conf_get_node() This should mention that conf_uname can be NULL and should be in the header file. Fix this. Signed-off-by: Simon Glass --- common/image-fit.c | 18 ------------------ include/image.h | 20 ++++++++++++++++++++ 2 files changed, 20 insertions(+), 18 deletions(-) diff --git a/common/image-fit.c b/common/image-fit.c index 6da69d25ffe..3d0cd564d83 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -1712,24 +1712,6 @@ int fit_conf_find_compat(const void *fit, const void *fdt) return best_match_offset; } -/** - * fit_conf_get_node - get node offset for configuration of a given unit name - * @fit: pointer to the FIT format image header - * @conf_uname: configuration node unit name - * - * fit_conf_get_node() finds a configuration (within the '/configurations' - * parent node) of a provided unit name. If configuration is found its node - * offset is returned to the caller. - * - * When NULL is provided in second argument fit_conf_get_node() will search - * for a default configuration node instead. Default configuration node unit - * name is retrieved from FIT_DEFAULT_PROP property of the '/configurations' - * node. - * - * returns: - * configuration node offset when found (>=0) - * negative number on failure (FDT_ERR_* code) - */ int fit_conf_get_node(const void *fit, const char *conf_uname) { int noffset, confs_noffset; diff --git a/include/image.h b/include/image.h index b316d167d8d..512243f159a 100644 --- a/include/image.h +++ b/include/image.h @@ -1092,7 +1092,27 @@ int fit_image_check_comp(const void *fit, int noffset, uint8_t comp); int fit_check_format(const void *fit); int fit_conf_find_compat(const void *fit, const void *fdt); + +/** + * fit_conf_get_node - get node offset for configuration of a given unit name + * @fit: pointer to the FIT format image header + * @conf_uname: configuration node unit name (NULL to use default) + * + * fit_conf_get_node() finds a configuration (within the '/configurations' + * parent node) of a provided unit name. If configuration is found its node + * offset is returned to the caller. + * + * When NULL is provided in second argument fit_conf_get_node() will search + * for a default configuration node instead. Default configuration node unit + * name is retrieved from FIT_DEFAULT_PROP property of the '/configurations' + * node. + * + * returns: + * configuration node offset when found (>=0) + * negative number on failure (FDT_ERR_* code) + */ int fit_conf_get_node(const void *fit, const char *conf_uname); + int fit_conf_get_prop_node_count(const void *fit, int noffset, const char *prop_name); int fit_conf_get_prop_node_index(const void *fit, int noffset, -- cgit v1.2.3 From 382cf62039f775a1aec771645e3cbc32e1e2f0e3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 18 Mar 2020 11:43:56 -0600 Subject: image: Be a little more verbose when checking signatures It is useful to be a little more specific about what is being checked. Update a few messages to help with this. Signed-off-by: Simon Glass --- common/image-fit.c | 2 +- tools/image-host.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/common/image-fit.c b/common/image-fit.c index 3d0cd564d83..47fc84aa4e3 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -1951,7 +1951,7 @@ int fit_image_load(bootm_headers_t *images, ulong addr, fit_uname = fit_get_name(fit, noffset, NULL); } if (noffset < 0) { - puts("Could not find subimage node\n"); + printf("Could not find subimage node type '%s'\n", prop_name); bootstage_error(bootstage_id + BOOTSTAGE_SUB_SUBNODE); return -ENOENT; } diff --git a/tools/image-host.c b/tools/image-host.c index 76a361b9d67..b3ec197dc9c 100644 --- a/tools/image-host.c +++ b/tools/image-host.c @@ -1034,7 +1034,8 @@ int fit_check_sign(const void *fit, const void *key) if (!cfg_noffset) return -1; - printf("Verifying Hash Integrity ... "); + printf("Verifying Hash Integrity for node '%s'... ", + fdt_get_name(fit, cfg_noffset, NULL)); ret = fit_config_verify(fit, cfg_noffset); if (ret) return ret; -- cgit v1.2.3 From 472f9113dbbbed88345f3d38de3ff37ca163508e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 18 Mar 2020 11:43:57 -0600 Subject: image: Return an error message from fit_config_verify_sig() This function only returns an error message sometimes. Update it to always return an error message if one is available. This makes it easier to see what went wrong. Signed-off-by: Simon Glass --- common/image-sig.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/common/image-sig.c b/common/image-sig.c index 639a1124504..13ccd50bc50 100644 --- a/common/image-sig.c +++ b/common/image-sig.c @@ -499,13 +499,14 @@ static int fit_config_verify_sig(const void *fit, int conf_noffset, goto error; } - return verified ? 0 : -EPERM; + if (verified) + return 0; error: printf(" error!\n%s for '%s' hash node in '%s' config node\n", err_msg, fit_get_name(fit, noffset, NULL), fit_get_name(fit, conf_noffset, NULL)); - return -1; + return -EPERM; } int fit_config_verify_required_sigs(const void *fit, int conf_noffset, -- cgit v1.2.3 From 477f559edf1144f95e29173d290818250aa57ef8 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 18 Mar 2020 11:43:58 -0600 Subject: test: vboot: Drop unnecessary parameter for fit_check_sign This tool only uses the last -k parameter provided. Drop the earlier one since it has no effect. Signed-off-by: Simon Glass --- test/py/tests/test_vboot.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py index 9c41ee56b15..3dd8e3cb664 100644 --- a/test/py/tests/test_vboot.py +++ b/test/py/tests/test_vboot.py @@ -180,8 +180,7 @@ def test_vboot(u_boot_console): cons.log.action('%s: Check signed config on the host' % sha_algo) - util.run_and_log(cons, [fit_check_sign, '-f', fit, '-k', tmpdir, - '-k', dtb]) + util.run_and_log(cons, [fit_check_sign, '-f', fit, '-k', dtb]) # Replace header bytes bcfg = u_boot_console.config.buildconfig -- cgit v1.2.3 From c021971e132234667eb80bc29bdd4ad6c8d04458 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 18 Mar 2020 11:43:59 -0600 Subject: test: vboot: Add a test for a forged configuration Add a check to make sure that it is not possible to add a new configuration and use the hashed nodes and hash of another configuration. Signed-off-by: Simon Glass --- test/py/tests/test_vboot.py | 18 +- test/py/tests/vboot_forge.py | 423 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 440 insertions(+), 1 deletion(-) create mode 100644 test/py/tests/vboot_forge.py diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py index 3dd8e3cb664..22c79ef3136 100644 --- a/test/py/tests/test_vboot.py +++ b/test/py/tests/test_vboot.py @@ -28,6 +28,7 @@ import pytest import sys import struct import u_boot_utils as util +import vboot_forge @pytest.mark.boardspec('sandbox') @pytest.mark.buildconfigspec('fit_signature') @@ -182,7 +183,22 @@ def test_vboot(u_boot_console): util.run_and_log(cons, [fit_check_sign, '-f', fit, '-k', dtb]) - # Replace header bytes + # Make sure that U-Boot checks that the config is in the list of hashed + # nodes. If it isn't, a security bypass is possible. + with open(fit, 'rb') as fp: + root, strblock = vboot_forge.read_fdt(fp) + root, strblock = vboot_forge.manipulate(root, strblock) + with open(fit, 'w+b') as fp: + vboot_forge.write_fdt(root, strblock, fp) + util.run_and_log_expect_exception(cons, + [fit_check_sign, '-f', fit, '-k', dtb], + 1, 'Failed to verify required signature') + + run_bootm(sha_algo, 'forged config', 'Bad Data Hash', False) + + # Create a new properly signed fit and replace header bytes + make_fit('sign-configs-%s%s.its' % (sha_algo, padding)) + sign_fit(sha_algo) bcfg = u_boot_console.config.buildconfig max_size = int(bcfg.get('config_fit_signature_max_size', 0x10000000), 0) existing_size = replace_fit_totalsize(max_size + 1) diff --git a/test/py/tests/vboot_forge.py b/test/py/tests/vboot_forge.py new file mode 100644 index 00000000000..0fb7ef40247 --- /dev/null +++ b/test/py/tests/vboot_forge.py @@ -0,0 +1,423 @@ +#!/usr/bin/python3 +# SPDX-License-Identifier: GPL-2.0 +# Copyright (c) 2020, F-Secure Corporation, https://foundry.f-secure.com +# +# pylint: disable=E1101,W0201,C0103 + +""" +Verified boot image forgery tools and utilities + +This module provides services to both take apart and regenerate FIT images +in a way that preserves all existing verified boot signatures, unless you +manipulate nodes in the process. +""" + +import struct +import binascii +from io import BytesIO + +# +# struct parsing helpers +# + +class BetterStructMeta(type): + """ + Preprocesses field definitions and creates a struct.Struct instance from them + """ + def __new__(cls, clsname, superclasses, attributedict): + if clsname != 'BetterStruct': + fields = attributedict['__fields__'] + field_types = [_[0] for _ in fields] + field_names = [_[1] for _ in fields if _[1] is not None] + attributedict['__names__'] = field_names + s = struct.Struct(attributedict.get('__endian__', '') + ''.join(field_types)) + attributedict['__struct__'] = s + attributedict['size'] = s.size + return type.__new__(cls, clsname, superclasses, attributedict) + +class BetterStruct(metaclass=BetterStructMeta): + """ + Base class for better structures + """ + def __init__(self): + for t, n in self.__fields__: + if 's' in t: + setattr(self, n, '') + elif t in ('Q', 'I', 'H', 'B'): + setattr(self, n, 0) + + @classmethod + def unpack_from(cls, buffer, offset=0): + """ + Unpack structure instance from a buffer + """ + fields = cls.__struct__.unpack_from(buffer, offset) + instance = cls() + for n, v in zip(cls.__names__, fields): + setattr(instance, n, v) + return instance + + def pack(self): + """ + Pack structure instance into bytes + """ + return self.__struct__.pack(*[getattr(self, n) for n in self.__names__]) + + def __str__(self): + items = ["'%s': %s" % (n, repr(getattr(self, n))) for n in self.__names__ if n is not None] + return '(' + ', '.join(items) + ')' + +# +# some defs for flat DT data +# + +class HeaderV17(BetterStruct): + __endian__ = '>' + __fields__ = [ + ('I', 'magic'), + ('I', 'totalsize'), + ('I', 'off_dt_struct'), + ('I', 'off_dt_strings'), + ('I', 'off_mem_rsvmap'), + ('I', 'version'), + ('I', 'last_comp_version'), + ('I', 'boot_cpuid_phys'), + ('I', 'size_dt_strings'), + ('I', 'size_dt_struct'), + ] + +class RRHeader(BetterStruct): + __endian__ = '>' + __fields__ = [ + ('Q', 'address'), + ('Q', 'size'), + ] + +class PropHeader(BetterStruct): + __endian__ = '>' + __fields__ = [ + ('I', 'value_size'), + ('I', 'name_offset'), + ] + +# magical constants for DTB format +OF_DT_HEADER = 0xd00dfeed +OF_DT_BEGIN_NODE = 1 +OF_DT_END_NODE = 2 +OF_DT_PROP = 3 +OF_DT_END = 9 + +class StringsBlock: + """ + Represents a parsed device tree string block + """ + def __init__(self, values=None): + if values is None: + self.values = [] + else: + self.values = values + + def __getitem__(self, at): + if isinstance(at, str): + offset = 0 + for value in self.values: + if value == at: + break + offset += len(value) + 1 + else: + self.values.append(at) + return offset + + if isinstance(at, int): + offset = 0 + for value in self.values: + if offset == at: + return value + offset += len(value) + 1 + raise IndexError('no string found corresponding to the given offset') + + raise TypeError('only strings and integers are accepted') + +class Prop: + """ + Represents a parsed device tree property + """ + def __init__(self, name=None, value=None): + self.name = name + self.value = value + + def clone(self): + return Prop(self.name, self.value) + + def __repr__(self): + return "" % (self.name, repr(self.value)) + +class Node: + """ + Represents a parsed device tree node + """ + def __init__(self, name=None): + self.name = name + self.props = [] + self.children = [] + + def clone(self): + o = Node(self.name) + o.props = [x.clone() for x in self.props] + o.children = [x.clone() for x in self.children] + return o + + def __getitem__(self, index): + return self.children[index] + + def __repr__(self): + return "" % (self.name, repr(self.props), repr(self.children)) + +# +# flat DT to memory +# + +def parse_strings(strings): + """ + Converts the bytes into a StringsBlock instance so it is convenient to work with + """ + strings = strings.split(b'\x00') + return StringsBlock(strings) + +def parse_struct(stream): + """ + Parses DTB structure(s) into a Node or Prop instance + """ + tag = bytearray(stream.read(4))[3] + if tag == OF_DT_BEGIN_NODE: + name = b'' + while b'\x00' not in name: + name += stream.read(4) + name = name.rstrip(b'\x00') + node = Node(name) + + item = parse_struct(stream) + while item is not None: + if isinstance(item, Node): + node.children.append(item) + elif isinstance(item, Prop): + node.props.append(item) + item = parse_struct(stream) + + return node + + if tag == OF_DT_PROP: + h = PropHeader.unpack_from(stream.read(PropHeader.size)) + length = (h.value_size + 3) & (~3) + value = stream.read(length)[:h.value_size] + prop = Prop(h.name_offset, value) + return prop + + if tag in (OF_DT_END_NODE, OF_DT_END): + return None + + raise ValueError('unexpected tag value') + +def read_fdt(fp): + """ + Reads and parses the flattened device tree (or derivatives like FIT) + """ + header = HeaderV17.unpack_from(fp.read(HeaderV17.size)) + if header.magic != OF_DT_HEADER: + raise ValueError('invalid magic value %08x; expected %08x' % (header.magic, OF_DT_HEADER)) + # TODO: read/parse reserved regions + fp.seek(header.off_dt_struct) + structs = fp.read(header.size_dt_struct) + fp.seek(header.off_dt_strings) + strings = fp.read(header.size_dt_strings) + strblock = parse_strings(strings) + root = parse_struct(BytesIO(structs)) + + return root, strblock + +# +# memory to flat DT +# + +def compose_structs_r(item): + """ + Recursive part of composing Nodes and Props into a bytearray + """ + t = bytearray() + + if isinstance(item, Node): + t.extend(struct.pack('>I', OF_DT_BEGIN_NODE)) + if isinstance(item.name, str): + item.name = bytes(item.name, 'utf-8') + name = item.name + b'\x00' + if len(name) & 3: + name += b'\x00' * (4 - (len(name) & 3)) + t.extend(name) + for p in item.props: + t.extend(compose_structs_r(p)) + for c in item.children: + t.extend(compose_structs_r(c)) + t.extend(struct.pack('>I', OF_DT_END_NODE)) + + elif isinstance(item, Prop): + t.extend(struct.pack('>I', OF_DT_PROP)) + value = item.value + h = PropHeader() + h.name_offset = item.name + if value: + h.value_size = len(value) + t.extend(h.pack()) + if len(value) & 3: + value += b'\x00' * (4 - (len(value) & 3)) + t.extend(value) + else: + h.value_size = 0 + t.extend(h.pack()) + + return t + +def compose_structs(root): + """ + Composes the parsed Nodes into a flat bytearray instance + """ + t = compose_structs_r(root) + t.extend(struct.pack('>I', OF_DT_END)) + return t + +def compose_strings(strblock): + """ + Composes the StringsBlock instance back into a bytearray instance + """ + b = bytearray() + for s in strblock.values: + b.extend(s) + b.append(0) + return bytes(b) + +def write_fdt(root, strblock, fp): + """ + Writes out a complete flattened device tree (or FIT) + """ + header = HeaderV17() + header.magic = OF_DT_HEADER + header.version = 17 + header.last_comp_version = 16 + fp.write(header.pack()) + + header.off_mem_rsvmap = fp.tell() + fp.write(RRHeader().pack()) + + structs = compose_structs(root) + header.off_dt_struct = fp.tell() + header.size_dt_struct = len(structs) + fp.write(structs) + + strings = compose_strings(strblock) + header.off_dt_strings = fp.tell() + header.size_dt_strings = len(strings) + fp.write(strings) + + header.totalsize = fp.tell() + + fp.seek(0) + fp.write(header.pack()) + +# +# pretty printing / converting to DT source +# + +def as_bytes(value): + return ' '.join(["%02X" % x for x in value]) + +def prety_print_value(value): + """ + Formats a property value as appropriate depending on the guessed data type + """ + if not value: + return '""' + if value[-1] == b'\x00': + printable = True + for x in value[:-1]: + x = ord(x) + if x != 0 and (x < 0x20 or x > 0x7F): + printable = False + break + if printable: + value = value[:-1] + return ', '.join('"' + x + '"' for x in value.split(b'\x00')) + if len(value) > 0x80: + return '[' + as_bytes(value[:0x80]) + ' ... ]' + return '[' + as_bytes(value) + ']' + +def pretty_print_r(node, strblock, indent=0): + """ + Prints out a single node, recursing further for each of its children + """ + spaces = ' ' * indent + print((spaces + '%s {' % (node.name.decode('utf-8') if node.name else '/'))) + for p in node.props: + print((spaces + ' %s = %s;' % (strblock[p.name].decode('utf-8'), prety_print_value(p.value)))) + for c in node.children: + pretty_print_r(c, strblock, indent+1) + print((spaces + '};')) + +def pretty_print(node, strblock): + """ + Generates an almost-DTS formatted printout of the parsed device tree + """ + print('/dts-v1/;') + pretty_print_r(node, strblock, 0) + +# +# manipulating the DT structure +# + +def manipulate(root, strblock): + """ + Maliciously manipulates the structure to create a crafted FIT file + """ + # locate /images/kernel@1 (frankly, it just expects it to be the first one) + kernel_node = root[0][0] + # clone it to save time filling all the properties + fake_kernel = kernel_node.clone() + # rename the node + fake_kernel.name = b'kernel@2' + # get rid of signatures/hashes + fake_kernel.children = [] + # NOTE: this simply replaces the first prop... either description or data + # should be good for testing purposes + fake_kernel.props[0].value = b'Super 1337 kernel\x00' + # insert the new kernel node under /images + root[0].children.append(fake_kernel) + + # modify the default configuration + root[1].props[0].value = b'conf@2\x00' + # clone the first (only?) configuration + fake_conf = root[1][0].clone() + # rename and change kernel and fdt properties to select the crafted kernel + fake_conf.name = b'conf@2' + fake_conf.props[0].value = b'kernel@2\x00' + fake_conf.props[1].value = b'fdt@1\x00' + # insert the new configuration under /configurations + root[1].children.append(fake_conf) + + return root, strblock + +def main(argv): + with open(argv[1], 'rb') as fp: + root, strblock = read_fdt(fp) + + print("Before:") + pretty_print(root, strblock) + + root, strblock = manipulate(root, strblock) + print("After:") + pretty_print(root, strblock) + + with open('blah', 'w+b') as fp: + write_fdt(root, strblock, fp) + +if __name__ == '__main__': + import sys + main(sys.argv) +# EOF -- cgit v1.2.3 From 1b090032029b35080a5a87c9f1047882d894ab37 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 18 Mar 2020 11:44:00 -0600 Subject: test: vboot: Parameterise the test This test is actually made up of five separate tests. Split them out so that they appear as separate tests. Unfortunately this restarts U-Boot multiple times which adds about a second to the already-long vboot test, about 8 seconds total on my machine. We could add a special 'teardown' test afterwards but if the tests are executed out of order that would not work. Changing test_vboot into a class causes it not to be discovered and makes it different from all other tests. Signed-off-by: Simon Glass --- test/py/tests/test_vboot.py | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py index 22c79ef3136..b1badaad737 100644 --- a/test/py/tests/test_vboot.py +++ b/test/py/tests/test_vboot.py @@ -30,13 +30,22 @@ import struct import u_boot_utils as util import vboot_forge +TESTDATA = [ + ['sha1', '', False], + ['sha1', '-pss', False], + ['sha256', '', False], + ['sha256', '-pss', False], + ['sha256', '-pss', True], +] + @pytest.mark.boardspec('sandbox') @pytest.mark.buildconfigspec('fit_signature') @pytest.mark.requiredtool('dtc') @pytest.mark.requiredtool('fdtget') @pytest.mark.requiredtool('fdtput') @pytest.mark.requiredtool('openssl') -def test_vboot(u_boot_console): +@pytest.mark.parametrize("sha_algo,padding,required", TESTDATA) +def test_vboot(u_boot_console, sha_algo, padding, required): """Test verified boot signing with mkimage and verification with 'bootm'. This works using sandbox only as it needs to update the device tree used @@ -297,11 +306,10 @@ def test_vboot(u_boot_console): # afterwards. old_dtb = cons.config.dtb cons.config.dtb = dtb - test_with_algo('sha1','') - test_with_algo('sha1','-pss') - test_with_algo('sha256','') - test_with_algo('sha256','-pss') - test_required_key('sha256','-pss') + if required: + test_required_key(sha_algo, padding) + else: + test_with_algo(sha_algo, padding) finally: # Go back to the original U-Boot with the correct dtb. cons.config.dtb = old_dtb -- cgit v1.2.3 From 67acad3db71bb372458fbb8a77749f5eb88aa324 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 18 Mar 2020 11:44:01 -0600 Subject: image: Check hash-nodes when checking configurations It is currently possible to use a different configuration's signature and thus bypass the configuration check. Make sure that the configuration node that was hashed matches the one being checked, to catch this problem. Also add a proper function comment to fit_config_check_sig() and make it static. Signed-off-by: Simon Glass --- common/image-sig.c | 36 +++++++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/common/image-sig.c b/common/image-sig.c index 13ccd50bc50..03143a40401 100644 --- a/common/image-sig.c +++ b/common/image-sig.c @@ -359,20 +359,39 @@ int fit_image_verify_required_sigs(const void *fit, int image_noffset, return 0; } -int fit_config_check_sig(const void *fit, int noffset, int required_keynode, - char **err_msgp) +/** + * fit_config_check_sig() - Check the signature of a config + * + * @fit: FIT to check + * @noffset: Offset of configuration node (e.g. /configurations/conf-1) + * @required_keynode: Offset in the control FDT of the required key node, + * if any. If this is given, then the configuration wil not + * pass verification unless that key is used. If this is + * -1 then any signature will do. + * @conf_noffset: Offset of the configuration subnode being checked (e.g. + * /configurations/conf-1/kernel) + * @err_msgp: In the event of an error, this will be pointed to a + * help error string to display to the user. + * @return 0 if all verified ok, <0 on error + */ +static int fit_config_check_sig(const void *fit, int noffset, + int required_keynode, int conf_noffset, + char **err_msgp) { char * const exc_prop[] = {"data"}; const char *prop, *end, *name; struct image_sign_info info; const uint32_t *strings; + const char *config_name; uint8_t *fit_value; int fit_value_len; + bool found_config; int max_regions; int i, prop_len; char path[200]; int count; + config_name = fit_get_name(fit, conf_noffset, NULL); debug("%s: fdt=%p, conf='%s', sig='%s'\n", __func__, gd_fdt_blob(), fit_get_name(fit, noffset, NULL), fit_get_name(gd_fdt_blob(), required_keynode, NULL)); @@ -413,9 +432,20 @@ int fit_config_check_sig(const void *fit, int noffset, int required_keynode, char *node_inc[count]; debug("Hash nodes (%d):\n", count); + found_config = false; for (name = prop, i = 0; name < end; name += strlen(name) + 1, i++) { debug(" '%s'\n", name); node_inc[i] = (char *)name; + if (!strncmp(FIT_CONFS_PATH, name, strlen(FIT_CONFS_PATH)) && + name[sizeof(FIT_CONFS_PATH) - 1] == '/' && + !strcmp(name + sizeof(FIT_CONFS_PATH), config_name)) { + debug(" (found config node %s)", config_name); + found_config = true; + } + } + if (!found_config) { + *err_msgp = "Selected config not in hashed nodes"; + return -1; } /* @@ -483,7 +513,7 @@ static int fit_config_verify_sig(const void *fit, int conf_noffset, if (!strncmp(name, FIT_SIG_NODENAME, strlen(FIT_SIG_NODENAME))) { ret = fit_config_check_sig(fit, noffset, sig_offset, - &err_msg); + conf_noffset, &err_msg); if (ret) { puts("- "); } else { -- cgit v1.2.3 From 8a9d03732e6d0f68107c80919096e7cf956dcb3d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 18 Mar 2020 11:44:02 -0600 Subject: image: Load the correct configuration in fit_check_sign At present bootm_host_load_images() is passed the configuration that has been verified, but ignores it and just uses the default configuration. This may not be the same. Update this function to use the selected configuration. Signed-off-by: Simon Glass --- common/bootm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/common/bootm.c b/common/bootm.c index 902c13880dd..db4362a6430 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -819,7 +819,8 @@ void __weak switch_to_non_secure_mode(void) #else /* USE_HOSTCC */ #if defined(CONFIG_FIT_SIGNATURE) -static int bootm_host_load_image(const void *fit, int req_image_type) +static int bootm_host_load_image(const void *fit, int req_image_type, + int cfg_noffset) { const char *fit_uname_config = NULL; ulong data, len; @@ -831,6 +832,7 @@ static int bootm_host_load_image(const void *fit, int req_image_type) void *load_buf; int ret; + fit_uname_config = fdt_get_name(fit, cfg_noffset, NULL); memset(&images, '\0', sizeof(images)); images.verify = 1; noffset = fit_image_load(&images, (ulong)fit, @@ -878,7 +880,7 @@ int bootm_host_load_images(const void *fit, int cfg_noffset) for (i = 0; i < ARRAY_SIZE(image_types); i++) { int ret; - ret = bootm_host_load_image(fit, image_types[i]); + ret = bootm_host_load_image(fit, image_types[i], cfg_noffset); if (!err && ret && ret != -ENOENT) err = ret; } -- cgit v1.2.3 From c3aa81e35cc53fcd825e89510cd648288e0b6b92 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 18 Mar 2020 11:44:03 -0600 Subject: fit_check_sign: Allow selecting the configuration to verify This tool always verifies the default configuration. It is useful to be able to verify a specific one. Add a command-line flag for this and plumb the logic through. Signed-off-by: Simon Glass --- tools/fdt_host.h | 3 ++- tools/fit_check_sign.c | 8 ++++++-- tools/image-host.c | 6 ++++-- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/tools/fdt_host.h b/tools/fdt_host.h index 99b009b2210..15c07c7a96e 100644 --- a/tools/fdt_host.h +++ b/tools/fdt_host.h @@ -27,6 +27,7 @@ */ int fdt_remove_unused_strings(const void *old, void *new); -int fit_check_sign(const void *working_fdt, const void *key); +int fit_check_sign(const void *fit, const void *key, + const char *fit_uname_config); #endif /* __FDT_HOST_H__ */ diff --git a/tools/fit_check_sign.c b/tools/fit_check_sign.c index 45287437928..9375d5cf72d 100644 --- a/tools/fit_check_sign.c +++ b/tools/fit_check_sign.c @@ -41,6 +41,7 @@ int main(int argc, char **argv) void *fit_blob; char *fdtfile = NULL; char *keyfile = NULL; + char *config_name = NULL; char cmdname[256]; int ret; void *key_blob; @@ -48,7 +49,7 @@ int main(int argc, char **argv) strncpy(cmdname, *argv, sizeof(cmdname) - 1); cmdname[sizeof(cmdname) - 1] = '\0'; - while ((c = getopt(argc, argv, "f:k:")) != -1) + while ((c = getopt(argc, argv, "f:k:c:")) != -1) switch (c) { case 'f': fdtfile = optarg; @@ -56,6 +57,9 @@ int main(int argc, char **argv) case 'k': keyfile = optarg; break; + case 'c': + config_name = optarg; + break; default: usage(cmdname); break; @@ -78,7 +82,7 @@ int main(int argc, char **argv) return EXIT_FAILURE; image_set_host_blob(key_blob); - ret = fit_check_sign(fit_blob, key_blob); + ret = fit_check_sign(fit_blob, key_blob, config_name); if (!ret) { ret = EXIT_SUCCESS; fprintf(stderr, "Signature check OK\n"); diff --git a/tools/image-host.c b/tools/image-host.c index b3ec197dc9c..dfea48e894f 100644 --- a/tools/image-host.c +++ b/tools/image-host.c @@ -1025,12 +1025,13 @@ int fit_add_verification_data(const char *keydir, void *keydest, void *fit, } #ifdef CONFIG_FIT_SIGNATURE -int fit_check_sign(const void *fit, const void *key) +int fit_check_sign(const void *fit, const void *key, + const char *fit_uname_config) { int cfg_noffset; int ret; - cfg_noffset = fit_conf_get_node(fit, NULL); + cfg_noffset = fit_conf_get_node(fit, fit_uname_config); if (!cfg_noffset) return -1; @@ -1039,6 +1040,7 @@ int fit_check_sign(const void *fit, const void *key) ret = fit_config_verify(fit, cfg_noffset); if (ret) return ret; + printf("Verified OK, loading images\n"); ret = bootm_host_load_images(fit, cfg_noffset); return ret; -- cgit v1.2.3 From 3156ee35a3f11e578442ec7f2f3b96179cb07c94 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 18 Mar 2020 11:44:04 -0600 Subject: test: vboot: Tidy up the code a little Fix some long lines and comments. Use a distinct name for the 'required key' test. Signed-off-by: Simon Glass --- test/py/tests/test_vboot.py | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py index b1badaad737..817f2a99d2c 100644 --- a/test/py/tests/test_vboot.py +++ b/test/py/tests/test_vboot.py @@ -91,7 +91,8 @@ def test_vboot(u_boot_console, sha_algo, padding, required): if boots: assert('sandbox: continuing, as we cannot run' in ''.join(output)) else: - assert('sandbox: continuing, as we cannot run' not in ''.join(output)) + assert('sandbox: continuing, as we cannot run' + not in ''.join(output)) def make_fit(its): """Make a new FIT from the .its source file. @@ -211,7 +212,8 @@ def test_vboot(u_boot_console, sha_algo, padding, required): bcfg = u_boot_console.config.buildconfig max_size = int(bcfg.get('config_fit_signature_max_size', 0x10000000), 0) existing_size = replace_fit_totalsize(max_size + 1) - run_bootm(sha_algo, 'Signed config with bad hash', 'Bad Data Hash', False) + run_bootm(sha_algo, 'Signed config with bad hash', 'Bad Data Hash', + False) cons.log.action('%s: Check overflowed FIT header totalsize' % sha_algo) # Replace with existing header bytes @@ -229,7 +231,8 @@ def test_vboot(u_boot_console, sha_algo, padding, required): util.run_and_log(cons, 'fdtput -t bx %s %s value %s' % (fit, sig_node, sig)) - run_bootm(sha_algo, 'Signed config with bad hash', 'Bad Data Hash', False) + run_bootm(sha_algo, 'Signed config with bad hash', 'Bad Data Hash', + False) cons.log.action('%s: Check bad config on the host' % sha_algo) util.run_and_log_expect_exception(cons, [fit_check_sign, '-f', fit, @@ -238,12 +241,11 @@ def test_vboot(u_boot_console, sha_algo, padding, required): def test_required_key(sha_algo, padding): """Test verified boot with the given hash algorithm. - This function test if u-boot reject an image when a required - key isn't used to sign a FIT. + This function tests if U-Boot rejects an image when a required key isn't + used to sign a FIT. Args: - sha_algo: Either 'sha1' or 'sha256', to select the algorithm to - use. + sha_algo: Either 'sha1' or 'sha256', to select the algorithm to use """ # Compile our device tree files for kernel and U-Boot. These are # regenerated here since mkimage will modify them (by adding a @@ -251,18 +253,24 @@ def test_vboot(u_boot_console, sha_algo, padding, required): dtc('sandbox-kernel.dts') dtc('sandbox-u-boot.dts') - # Build the FIT with prod key (keys required) - # Build the FIT with dev key (keys NOT required) - # The dtb contain the key prod and dev and the key prod are set as required. - # Then try to boot the FIT with dev key - # This FIT should not be accepted by u-boot because the key prod is required cons.log.action('%s: Test FIT with configs images' % sha_algo) + + # Build the FIT with prod key (keys required) and sign it. This puts the + # signature into sandbox-u-boot.dtb, marked 'required' make_fit('sign-configs-%s%s-prod.its' % (sha_algo , padding)) sign_fit(sha_algo) + + # Build the FIT with dev key (keys NOT required). This adds the + # signature into sandbox-u-boot.dtb, NOT marked 'required'. make_fit('sign-configs-%s%s.its' % (sha_algo , padding)) sign_fit(sha_algo) - run_bootm(sha_algo, 'signed configs', '', False) + # So now sandbox-u-boot.dtb two signatures, for the prod and dev keys. + # Only the prod key is set as 'required'. But FIT we just built has + # a dev signature only (sign_fit() overwrites the FIT). + # Try to boot the FIT with dev key. This FIT should not be accepted by + # U-Boot because the prod key is required. + run_bootm(sha_algo, 'required key', '', False) cons = u_boot_console tmpdir = cons.config.result_dir + '/' -- cgit v1.2.3 From b008677daf2a9dc0335260c7c4e24390487fe0ca Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 18 Mar 2020 11:44:05 -0600 Subject: test: vboot: Fix pylint errors Fix various minor things noticed by pylint. Signed-off-by: Simon Glass --- test/py/tests/test_vboot.py | 53 ++++++++++++++++----------------------------- 1 file changed, 19 insertions(+), 34 deletions(-) diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py index 817f2a99d2c..0b8bd9ac0b0 100644 --- a/test/py/tests/test_vboot.py +++ b/test/py/tests/test_vboot.py @@ -24,9 +24,8 @@ For configuration verification: Tests run with both SHA1 and SHA256 hashing. """ -import pytest -import sys import struct +import pytest import u_boot_utils as util import vboot_forge @@ -85,11 +84,11 @@ def test_vboot(u_boot_console, sha_algo, padding, required): with cons.log.section('Verified boot %s %s' % (sha_algo, test_type)): output = cons.run_command_list( ['host load hostfs - 100 %stest.fit' % tmpdir, - 'fdt addr 100', - 'bootm 100']) - assert(expect_string in ''.join(output)) + 'fdt addr 100', + 'bootm 100']) + assert expect_string in ''.join(output) if boots: - assert('sandbox: continuing, as we cannot run' in ''.join(output)) + assert 'sandbox: continuing, as we cannot run' in ''.join(output) else: assert('sandbox: continuing, as we cannot run' not in ''.join(output)) @@ -119,20 +118,6 @@ def test_vboot(u_boot_console, sha_algo, padding, required): util.run_and_log(cons, [mkimage, '-F', '-k', tmpdir, '-K', dtb, '-r', fit]) - def sign_fit_norequire(sha_algo): - """Sign the FIT - - Signs the FIT and writes the signature into it. It also writes the - public key into the dtb. - - Args: - sha_algo: Either 'sha1' or 'sha256', to select the algorithm to - use. - """ - cons.log.action('%s: Sign images' % sha_algo) - util.run_and_log(cons, [mkimage, '-F', '-k', tmpdir, '-K', dtb, - fit]) - def replace_fit_totalsize(size): """Replace FIT header's totalsize with something greater. @@ -171,7 +156,7 @@ def test_vboot(u_boot_console, sha_algo, padding, required): # Build the FIT, but don't sign anything yet cons.log.action('%s: Test FIT with signed images' % sha_algo) - make_fit('sign-images-%s%s.its' % (sha_algo , padding)) + make_fit('sign-images-%s%s.its' % (sha_algo, padding)) run_bootm(sha_algo, 'unsigned images', 'dev-', True) # Sign images with our dev keys @@ -182,7 +167,7 @@ def test_vboot(u_boot_console, sha_algo, padding, required): dtc('sandbox-u-boot.dts') cons.log.action('%s: Test FIT with signed configuration' % sha_algo) - make_fit('sign-configs-%s%s.its' % (sha_algo , padding)) + make_fit('sign-configs-%s%s.its' % (sha_algo, padding)) run_bootm(sha_algo, 'unsigned config', '%s+ OK' % sha_algo, True) # Sign images with our dev keys @@ -195,14 +180,14 @@ def test_vboot(u_boot_console, sha_algo, padding, required): # Make sure that U-Boot checks that the config is in the list of hashed # nodes. If it isn't, a security bypass is possible. - with open(fit, 'rb') as fp: - root, strblock = vboot_forge.read_fdt(fp) + with open(fit, 'rb') as fd: + root, strblock = vboot_forge.read_fdt(fd) root, strblock = vboot_forge.manipulate(root, strblock) - with open(fit, 'w+b') as fp: - vboot_forge.write_fdt(root, strblock, fp) - util.run_and_log_expect_exception(cons, - [fit_check_sign, '-f', fit, '-k', dtb], - 1, 'Failed to verify required signature') + with open(fit, 'w+b') as fd: + vboot_forge.write_fdt(root, strblock, fd) + util.run_and_log_expect_exception( + cons, [fit_check_sign, '-f', fit, '-k', dtb], + 1, 'Failed to verify required signature') run_bootm(sha_algo, 'forged config', 'Bad Data Hash', False) @@ -235,8 +220,9 @@ def test_vboot(u_boot_console, sha_algo, padding, required): False) cons.log.action('%s: Check bad config on the host' % sha_algo) - util.run_and_log_expect_exception(cons, [fit_check_sign, '-f', fit, - '-k', dtb], 1, 'Failed to verify required signature') + util.run_and_log_expect_exception( + cons, [fit_check_sign, '-f', fit, '-k', dtb], + 1, 'Failed to verify required signature') def test_required_key(sha_algo, padding): """Test verified boot with the given hash algorithm. @@ -257,12 +243,12 @@ def test_vboot(u_boot_console, sha_algo, padding, required): # Build the FIT with prod key (keys required) and sign it. This puts the # signature into sandbox-u-boot.dtb, marked 'required' - make_fit('sign-configs-%s%s-prod.its' % (sha_algo , padding)) + make_fit('sign-configs-%s%s-prod.its' % (sha_algo, padding)) sign_fit(sha_algo) # Build the FIT with dev key (keys NOT required). This adds the # signature into sandbox-u-boot.dtb, NOT marked 'required'. - make_fit('sign-configs-%s%s.its' % (sha_algo , padding)) + make_fit('sign-configs-%s%s.its' % (sha_algo, padding)) sign_fit(sha_algo) # So now sandbox-u-boot.dtb two signatures, for the prod and dev keys. @@ -274,7 +260,6 @@ def test_vboot(u_boot_console, sha_algo, padding, required): cons = u_boot_console tmpdir = cons.config.result_dir + '/' - tmp = tmpdir + 'vboot.tmp' datadir = cons.config.source_dir + '/test/py/tests/vboot/' fit = '%stest.fit' % tmpdir mkimage = cons.config.build_dir + '/tools/mkimage' -- cgit v1.2.3 From 72188f546291cfadea99e9383c133d6aaa37d87d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 18 Mar 2020 11:44:06 -0600 Subject: image: Use constants for 'required' and 'key-name-hint' These are used in multiple places so update them to use a shared #define. Signed-off-by: Simon Glass Reviewed-by: Philippe Reynes --- common/image-cipher.c | 2 +- common/image-fit.c | 6 +++--- common/image-sig.c | 8 +++++--- include/image.h | 4 +++- lib/rsa/rsa-sign.c | 6 +++--- tools/image-host.c | 8 ++++---- 6 files changed, 19 insertions(+), 15 deletions(-) diff --git a/common/image-cipher.c b/common/image-cipher.c index cee3b03ee50..f50c3d31bd5 100644 --- a/common/image-cipher.c +++ b/common/image-cipher.c @@ -88,7 +88,7 @@ static int fit_image_setup_decrypt(struct image_cipher_info *info, return -1; } - info->keyname = fdt_getprop(fit, cipher_noffset, "key-name-hint", NULL); + info->keyname = fdt_getprop(fit, cipher_noffset, FIT_KEY_HINT, NULL); if (!info->keyname) { printf("Can't get key name\n"); return -1; diff --git a/common/image-fit.c b/common/image-fit.c index 47fc84aa4e3..0fef0a918da 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -168,7 +168,7 @@ static void fit_image_print_data(const void *fit, int noffset, const char *p, int value_len; char *algo; const char *padding; - int required; + bool required; int ret, i; debug("%s %s node: '%s'\n", p, type, @@ -179,8 +179,8 @@ static void fit_image_print_data(const void *fit, int noffset, const char *p, return; } printf("%s", algo); - keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL); - required = fdt_getprop(fit, noffset, "required", NULL) != NULL; + keyname = fdt_getprop(fit, noffset, FIT_KEY_HINT, NULL); + required = fdt_getprop(fit, noffset, FIT_KEY_REQUIRED, NULL) != NULL; if (keyname) printf(":%s", keyname); if (required) diff --git a/common/image-sig.c b/common/image-sig.c index 03143a40401..6563effcf34 100644 --- a/common/image-sig.c +++ b/common/image-sig.c @@ -229,7 +229,7 @@ static int fit_image_setup_verify(struct image_sign_info *info, padding_name = RSA_DEFAULT_PADDING_NAME; memset(info, '\0', sizeof(*info)); - info->keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL); + info->keyname = fdt_getprop(fit, noffset, FIT_KEY_HINT, NULL); info->fit = (void *)fit; info->node_offset = noffset; info->name = algo_name; @@ -340,7 +340,8 @@ int fit_image_verify_required_sigs(const void *fit, int image_noffset, const char *required; int ret; - required = fdt_getprop(sig_blob, noffset, "required", NULL); + required = fdt_getprop(sig_blob, noffset, FIT_KEY_REQUIRED, + NULL); if (!required || strcmp(required, "image")) continue; ret = fit_image_verify_sig(fit, image_noffset, data, size, @@ -557,7 +558,8 @@ int fit_config_verify_required_sigs(const void *fit, int conf_noffset, const char *required; int ret; - required = fdt_getprop(sig_blob, noffset, "required", NULL); + required = fdt_getprop(sig_blob, noffset, FIT_KEY_REQUIRED, + NULL); if (!required || strcmp(required, "conf")) continue; ret = fit_config_verify_sig(fit, conf_noffset, sig_blob, diff --git a/include/image.h b/include/image.h index 512243f159a..3ffc0fdd682 100644 --- a/include/image.h +++ b/include/image.h @@ -939,12 +939,14 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size, #define FIT_IMAGES_PATH "/images" #define FIT_CONFS_PATH "/configurations" -/* hash/signature node */ +/* hash/signature/key node */ #define FIT_HASH_NODENAME "hash" #define FIT_ALGO_PROP "algo" #define FIT_VALUE_PROP "value" #define FIT_IGNORE_PROP "uboot-ignore" #define FIT_SIG_NODENAME "signature" +#define FIT_KEY_REQUIRED "required" +#define FIT_KEY_HINT "key-name-hint" /* cipher node */ #define FIT_CIPHER_NODENAME "cipher" diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c index 6400ef63d6a..580c7447093 100644 --- a/lib/rsa/rsa-sign.c +++ b/lib/rsa/rsa-sign.c @@ -792,8 +792,8 @@ int rsa_add_verify_data(struct image_sign_info *info, void *keydest) } if (!ret) { - ret = fdt_setprop_string(keydest, node, "key-name-hint", - info->keyname); + ret = fdt_setprop_string(keydest, node, FIT_KEY_HINT, + info->keyname); } if (!ret) ret = fdt_setprop_u32(keydest, node, "rsa,num-bits", bits); @@ -815,7 +815,7 @@ int rsa_add_verify_data(struct image_sign_info *info, void *keydest) info->name); } if (!ret && info->require_keys) { - ret = fdt_setprop_string(keydest, node, "required", + ret = fdt_setprop_string(keydest, node, FIT_KEY_REQUIRED, info->require_keys); } done: diff --git a/tools/image-host.c b/tools/image-host.c index dfea48e894f..4e57ddea969 100644 --- a/tools/image-host.c +++ b/tools/image-host.c @@ -170,7 +170,7 @@ static int fit_image_setup_sig(struct image_sign_info *info, memset(info, '\0', sizeof(*info)); info->keydir = keydir; - info->keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL); + info->keyname = fdt_getprop(fit, noffset, FIT_KEY_HINT, NULL); info->fit = fit; info->node_offset = noffset; info->name = strdup(algo_name); @@ -249,7 +249,7 @@ static int fit_image_process_sig(const char *keydir, void *keydest, free(value); /* Get keyname again, as FDT has changed and invalidated our pointer */ - info.keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL); + info.keyname = fdt_getprop(fit, noffset, FIT_KEY_HINT, NULL); /* * Write the public key into the supplied FDT file; this might fail @@ -337,7 +337,7 @@ static int fit_image_setup_cipher(struct image_cipher_info *info, info->keydir = keydir; /* Read the key name */ - info->keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL); + info->keyname = fdt_getprop(fit, noffset, FIT_KEY_HINT, NULL); if (!info->keyname) { printf("Can't get key name for cipher '%s' in image '%s'\n", node_name, image_name); @@ -886,7 +886,7 @@ static int fit_config_process_sig(const char *keydir, void *keydest, free(region_prop); /* Get keyname again, as FDT has changed and invalidated our pointer */ - info.keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL); + info.keyname = fdt_getprop(fit, noffset, FIT_KEY_HINT, NULL); /* Write the public key into the supplied FDT file */ if (keydest) { -- cgit v1.2.3 From da76ed2795f2679ff0fa3c43f2b906157ec7c0b0 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 18 Mar 2020 11:44:07 -0600 Subject: test: vboot: Move key creation into a function This code is repeated so move it into a function with a parameter. Signed-off-by: Simon Glass --- test/py/tests/test_vboot.py | 39 ++++++++++++++++++--------------------- 1 file changed, 18 insertions(+), 21 deletions(-) diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py index 0b8bd9ac0b0..91305a4f0fc 100644 --- a/test/py/tests/test_vboot.py +++ b/test/py/tests/test_vboot.py @@ -138,6 +138,22 @@ def test_vboot(u_boot_console, sha_algo, padding, required): handle.write(struct.pack(">I", size)) return struct.unpack(">I", total_size)[0] + def create_rsa_pair(name): + """Generate a new RSA key paid and certificate + + Args: + name: Name of of the key (e.g. 'dev') + """ + public_exponent = 65537 + util.run_and_log(cons, 'openssl genpkey -algorithm RSA -out %s%s.key ' + '-pkeyopt rsa_keygen_bits:2048 ' + '-pkeyopt rsa_keygen_pubexp:%d' % + (tmpdir, name, public_exponent)) + + # Create a certificate containing the public key + util.run_and_log(cons, 'openssl req -batch -new -x509 -key %s%s.key ' + '-out %s%s.crt' % (tmpdir, name, tmpdir, name)) + def test_with_algo(sha_algo, padding): """Test verified boot with the given hash algorithm. @@ -268,27 +284,8 @@ def test_vboot(u_boot_console, sha_algo, padding, required): dtb = '%ssandbox-u-boot.dtb' % tmpdir sig_node = '/configurations/conf-1/signature' - # Create an RSA key pair - public_exponent = 65537 - util.run_and_log(cons, 'openssl genpkey -algorithm RSA -out %sdev.key ' - '-pkeyopt rsa_keygen_bits:2048 ' - '-pkeyopt rsa_keygen_pubexp:%d' % - (tmpdir, public_exponent)) - - # Create a certificate containing the public key - util.run_and_log(cons, 'openssl req -batch -new -x509 -key %sdev.key -out ' - '%sdev.crt' % (tmpdir, tmpdir)) - - # Create an RSA key pair (prod) - public_exponent = 65537 - util.run_and_log(cons, 'openssl genpkey -algorithm RSA -out %sprod.key ' - '-pkeyopt rsa_keygen_bits:2048 ' - '-pkeyopt rsa_keygen_pubexp:%d' % - (tmpdir, public_exponent)) - - # Create a certificate containing the public key (prod) - util.run_and_log(cons, 'openssl req -batch -new -x509 -key %sprod.key -out ' - '%sprod.crt' % (tmpdir, tmpdir)) + create_rsa_pair('dev') + create_rsa_pair('prod') # Create a number kernel image with zeroes with open('%stest-kernel.bin' % tmpdir, 'w') as fd: -- cgit v1.2.3 From 0e29648f8e7e0aa60c0f7efe9d2efed98f8c0c6e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 18 Mar 2020 11:44:08 -0600 Subject: test: vboot: Reduce fake kernel size to 500 bytes We don't need 5KB to test things out. A smaller size makes it easier to look at the FIT with fdtdump. Signed-off-by: Simon Glass --- test/py/tests/test_vboot.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py index 91305a4f0fc..e67f2b3d0f6 100644 --- a/test/py/tests/test_vboot.py +++ b/test/py/tests/test_vboot.py @@ -289,7 +289,7 @@ def test_vboot(u_boot_console, sha_algo, padding, required): # Create a number kernel image with zeroes with open('%stest-kernel.bin' % tmpdir, 'w') as fd: - fd.write(5000 * chr(0)) + fd.write(500 * chr(0)) try: # We need to use our own device tree file. Remember to restore it -- cgit v1.2.3 From ba03a6c94493686ec8cc8c4b95dfb3c7a723b99c Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 20 Mar 2020 09:37:59 +0000 Subject: spi: atmel-quadspi: fix possible MMIO window size overrun The sama5d2 QSPI controller memory space is limited to 128MB: 0x9000_00000-0x9800_00000/0XD000_0000--0XD800_0000. There are nor flashes that are bigger in size than the memory size supported by the controller: Micron MT25QL02G (256 MB). Check if the address exceeds the MMIO window size. An improvement would be to add support for regular SPI mode and fall back to it when the flash memories overrun the controller's memory space. Fixes: 24c8ff4684c5 ("spi: Add Atmel QuadSPI driver") Signed-off-by: Tudor Ambarus Reviewed-by: Jagan Teki --- drivers/spi/atmel-quadspi.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index a09bf884e83..4099ee87993 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -146,6 +146,7 @@ struct atmel_qspi_caps { struct atmel_qspi { void __iomem *regs; void __iomem *mem; + resource_size_t mmap_size; const struct atmel_qspi_caps *caps; ulong bus_clk_rate; u32 mr; @@ -326,6 +327,14 @@ static int atmel_qspi_exec_op(struct spi_slave *slave, u32 sr, imr, offset; int err; + /* + * Check if the address exceeds the MMIO window size. An improvement + * would be to add support for regular SPI mode and fall back to it + * when the flash memories overrun the controller's memory space. + */ + if (op->addr.val + op->data.nbytes > aq->mmap_size) + return -ENOTSUPP; + err = atmel_qspi_set_cfg(aq, op, &offset); if (err) return err; @@ -490,6 +499,8 @@ static int atmel_qspi_probe(struct udevice *dev) if (IS_ERR(aq->mem)) return PTR_ERR(aq->mem); + aq->mmap_size = resource_size(&res); + ret = atmel_qspi_enable_clk(dev); if (ret) return ret; -- cgit v1.2.3 From 52e2565bfb5d332e53021c6ec437cdb95eaf9dde Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 20 Mar 2020 09:37:59 +0000 Subject: spi: atmel-quadspi: Add verbose debug facilities to monitor register accesses This feature should not be enabled in release but can be useful for developers who need to monitor register accesses at some specific places. Helped me identify a bug in u-boot, by comparing the register accesses from the u-boot driver with the ones from its linux variant. Signed-off-by: Tudor Ambarus [jagan: use 16 bit array with tmp variable] Signed-off-by: Jagan Teki Reviewed-by: Jagan Teki --- drivers/spi/atmel-quadspi.c | 114 +++++++++++++++++++++++++++++++++++++------- 1 file changed, 96 insertions(+), 18 deletions(-) diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 4099ee87993..a6c3939db54 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -148,6 +148,7 @@ struct atmel_qspi { void __iomem *mem; resource_size_t mmap_size; const struct atmel_qspi_caps *caps; + struct udevice *dev; ulong bus_clk_rate; u32 mr; }; @@ -169,6 +170,81 @@ static const struct atmel_qspi_mode atmel_qspi_modes[] = { { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD }, }; +#ifdef VERBOSE_DEBUG +static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz) +{ + switch (offset) { + case QSPI_CR: + return "CR"; + case QSPI_MR: + return "MR"; + case QSPI_RD: + return "MR"; + case QSPI_TD: + return "TD"; + case QSPI_SR: + return "SR"; + case QSPI_IER: + return "IER"; + case QSPI_IDR: + return "IDR"; + case QSPI_IMR: + return "IMR"; + case QSPI_SCR: + return "SCR"; + case QSPI_IAR: + return "IAR"; + case QSPI_ICR: + return "ICR/WICR"; + case QSPI_IFR: + return "IFR"; + case QSPI_RICR: + return "RICR"; + case QSPI_SMR: + return "SMR"; + case QSPI_SKR: + return "SKR"; + case QSPI_WPMR: + return "WPMR"; + case QSPI_WPSR: + return "WPSR"; + case QSPI_VERSION: + return "VERSION"; + default: + snprintf(tmp, sz, "0x%02x", offset); + break; + } + + return tmp; +} +#endif /* VERBOSE_DEBUG */ + +static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset) +{ + u32 value = readl(aq->regs + offset); + +#ifdef VERBOSE_DEBUG + char tmp[16]; + + dev_vdbg(aq->dev, "read 0x%08x from %s\n", value, + atmel_qspi_reg_name(offset, tmp, sizeof(tmp))); +#endif /* VERBOSE_DEBUG */ + + return value; +} + +static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset) +{ +#ifdef VERBOSE_DEBUG + char tmp[16]; + + dev_vdbg(aq->dev, "write 0x%08x into %s\n", value, + atmel_qspi_reg_name(offset, tmp, sizeof(tmp))); +#endif /* VERBOSE_DEBUG */ + + writel(value, aq->regs + offset); +} + static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op, const struct atmel_qspi_mode *mode) { @@ -289,32 +365,32 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq, * Serial Memory Mode (SMM). */ if (aq->mr != QSPI_MR_SMM) { - writel(QSPI_MR_SMM, aq->regs + QSPI_MR); + atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR); aq->mr = QSPI_MR_SMM; } /* Clear pending interrupts */ - (void)readl(aq->regs + QSPI_SR); + (void)atmel_qspi_read(aq, QSPI_SR); if (aq->caps->has_ricr) { if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN) ifr |= QSPI_IFR_APBTFRTYP_READ; /* Set QSPI Instruction Frame registers */ - writel(iar, aq->regs + QSPI_IAR); + atmel_qspi_write(iar, aq, QSPI_IAR); if (op->data.dir == SPI_MEM_DATA_IN) - writel(icr, aq->regs + QSPI_RICR); + atmel_qspi_write(icr, aq, QSPI_RICR); else - writel(icr, aq->regs + QSPI_WICR); - writel(ifr, aq->regs + QSPI_IFR); + atmel_qspi_write(icr, aq, QSPI_WICR); + atmel_qspi_write(ifr, aq, QSPI_IFR); } else { if (op->data.dir == SPI_MEM_DATA_OUT) ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR; /* Set QSPI Instruction Frame registers */ - writel(iar, aq->regs + QSPI_IAR); - writel(icr, aq->regs + QSPI_ICR); - writel(ifr, aq->regs + QSPI_IFR); + atmel_qspi_write(iar, aq, QSPI_IAR); + atmel_qspi_write(icr, aq, QSPI_ICR); + atmel_qspi_write(ifr, aq, QSPI_IFR); } return 0; @@ -342,7 +418,7 @@ static int atmel_qspi_exec_op(struct spi_slave *slave, /* Skip to the final steps if there is no data */ if (op->data.nbytes) { /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */ - (void)readl(aq->regs + QSPI_IFR); + (void)atmel_qspi_read(aq, QSPI_IFR); /* Send/Receive data */ if (op->data.dir == SPI_MEM_DATA_IN) @@ -353,7 +429,7 @@ static int atmel_qspi_exec_op(struct spi_slave *slave, op->data.nbytes); /* Release the chip-select */ - writel(QSPI_CR_LASTXFER, aq->regs + QSPI_CR); + atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR); } /* Poll INSTruction End and Chip Select Rise flags. */ @@ -375,12 +451,12 @@ static int atmel_qspi_set_speed(struct udevice *bus, uint hz) new_value = QSPI_SCR_SCBR(scbr); mask = QSPI_SCR_SCBR_MASK; - scr = readl(aq->regs + QSPI_SCR); + scr = atmel_qspi_read(aq, QSPI_SCR); if ((scr & mask) == new_value) return 0; scr = (scr & ~mask) | new_value; - writel(scr, aq->regs + QSPI_SCR); + atmel_qspi_write(scr, aq, QSPI_SCR); return 0; } @@ -397,12 +473,12 @@ static int atmel_qspi_set_mode(struct udevice *bus, uint mode) mask = QSPI_SCR_CPOL | QSPI_SCR_CPHA; - scr = readl(aq->regs + QSPI_SCR); + scr = atmel_qspi_read(aq, QSPI_SCR); if ((scr & mask) == new_value) return 0; scr = (scr & ~mask) | new_value; - writel(scr, aq->regs + QSPI_SCR); + atmel_qspi_write(scr, aq, QSPI_SCR); return 0; } @@ -455,14 +531,14 @@ free_pclk: static void atmel_qspi_init(struct atmel_qspi *aq) { /* Reset the QSPI controller */ - writel(QSPI_CR_SWRST, aq->regs + QSPI_CR); + atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR); /* Set the QSPI controller by default in Serial Memory Mode */ - writel(QSPI_MR_SMM, aq->regs + QSPI_MR); + atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR); aq->mr = QSPI_MR_SMM; /* Enable the QSPI controller */ - writel(QSPI_CR_QSPIEN, aq->regs + QSPI_CR); + atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR); } static int atmel_qspi_probe(struct udevice *dev) @@ -505,6 +581,8 @@ static int atmel_qspi_probe(struct udevice *dev) if (ret) return ret; + aq->dev = dev; + atmel_qspi_init(aq); return 0; -- cgit v1.2.3 From b1bcd61665646d3f44e6d0e94a3ef946417027ca Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 2 Apr 2020 17:11:21 +0530 Subject: clk: rk3399: Set empty for vopl assigned-clocks During vidconsole probe, the device probe will try to check whether the assigned clocks on that video console node is initialized or not? and return an error if not. But, unlike Linux U-Boot won't require to handle these vopl assigned-clocks since core clocks are enough to handle the video out to process. So, mark them as empty in set_rate to satisfy clk_set_defaults so-that probe happened properly. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang Tested-by: Peter Robinson --- drivers/clk/rockchip/clk_rk3399.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 865b80cc0fb..1f623765956 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -994,6 +994,13 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case DCLK_VOP1: ret = rk3399_vop_set_clk(priv->cru, clk->id, rate); break; + case ACLK_VOP1: + case HCLK_VOP1: + /** + * assigned-clocks handling won't require for vopl, so + * return 0 to satisfy clk_set_defaults during device probe. + */ + return 0; case SCLK_DDRCLK: ret = rk3399_ddr_set_clk(priv->cru, rate); break; -- cgit v1.2.3 From e67243f1a3afc1289f647c86642f067c1ab05498 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 2 Apr 2020 17:11:22 +0530 Subject: video: rockchip: Fix vop modes for rk3399 VOP display endpoint pipeline configuration differs between rk3288 vs rk3399. These VOP pipeline configuration depends on how the different display interfaces connected in sequence to IN and OUT ports like for, RK3288: vopb_out: port { #address-cells = <1>; #size-cells = <0>; vopb_out_edp: endpoint@0 { reg = <0>; remote-endpoint = <&edp_in_vopb>; }; vopb_out_hdmi: endpoint@1 { reg = <1>; remote-endpoint = <&hdmi_in_vopb>; }; vopb_out_lvds: endpoint@2 { reg = <2>; remote-endpoint = <&lvds_in_vopb>; }; vopb_out_mipi: endpoint@3 { reg = <3>; remote-endpoint = <&mipi_in_vopb>; }; }; RK3399: vopb_out: port { #address-cells = <1>; #size-cells = <0>; vopb_out_edp: endpoint@0 { reg = <0>; remote-endpoint = <&edp_in_vopb>; }; vopb_out_mipi: endpoint@1 { reg = <1>; remote-endpoint = <&mipi_in_vopb>; }; vopb_out_hdmi: endpoint@2 { reg = <2>; remote-endpoint = <&hdmi_in_vopb>; }; vopb_out_mipi1: endpoint@3 { reg = <3>; remote-endpoint = <&mipi1_in_vopb>; }; vopb_out_dp: endpoint@4 { reg = <4>; remote-endpoint = <&dp_in_vopb>; }; }; here, HDMI interface has endpoint 1 in rk3288 and 2 in rk3399. The rockchip vop driver often depends on this determined endpoint number and stored in vop_mode. So based on this vop_mode the bpp and pin polarity would configure on detected display interface. Since, the existing driver using rk3288 vop mode settings enabling the same will result wrong display interface configuration for rk3399. Add the patch for fixing these vop modes for rk3399. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang Tested-by: Peter Robinson --- arch/arm/include/asm/arch-rockchip/vop_rk3288.h | 11 +++++++++++ drivers/video/rockchip/rk3399_vop.c | 2 -- drivers/video/rockchip/rk_vop.c | 4 ++++ 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h index 83982495096..872a158b714 100644 --- a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h @@ -85,6 +85,16 @@ enum { LB_RGB_1280X8 = 0x5 }; +#if defined(CONFIG_ROCKCHIP_RK3399) +enum vop_modes { + VOP_MODE_EDP = 0, + VOP_MODE_MIPI, + VOP_MODE_HDMI, + VOP_MODE_MIPI1, + VOP_MODE_DP, + VOP_MODE_NONE, +}; +#else enum vop_modes { VOP_MODE_EDP = 0, VOP_MODE_HDMI, @@ -94,6 +104,7 @@ enum vop_modes { VOP_MODE_AUTO_DETECT, VOP_MODE_UNKNOWN, }; +#endif /* VOP_VERSION_INFO */ #define M_FPGA_VERSION (0xffff << 16) diff --git a/drivers/video/rockchip/rk3399_vop.c b/drivers/video/rockchip/rk3399_vop.c index 81c122d7a9e..1d5b3931a65 100644 --- a/drivers/video/rockchip/rk3399_vop.c +++ b/drivers/video/rockchip/rk3399_vop.c @@ -45,8 +45,6 @@ static void rk3399_set_pin_polarity(struct udevice *dev, V_RK3399_DSP_MIPI_POL(polarity)); break; - case VOP_MODE_LVDS: - /* The RK3399 has neither parallel RGB nor LVDS output. */ default: debug("%s: unsupported output mode %x\n", __func__, mode); } diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index e91d4dfa7fb..e1bd656beed 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -118,10 +118,12 @@ static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode) V_EDP_OUT_EN(1)); break; +#if defined(CONFIG_ROCKCHIP_RK3288) case VOP_MODE_LVDS: clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, V_RGB_OUT_EN(1)); break; +#endif case VOP_MODE_MIPI: clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, @@ -313,7 +315,9 @@ static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node) /* Set bitwidth for vop display according to vop mode */ switch (vop_id) { case VOP_MODE_EDP: +#if defined(CONFIG_ROCKCHIP_RK3288) case VOP_MODE_LVDS: +#endif l2bpp = VIDEO_BPP16; break; case VOP_MODE_HDMI: -- cgit v1.2.3 From 61853a7ac7e167d90899ec4e99d2e07db7bc72c1 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 2 Apr 2020 17:11:23 +0530 Subject: rockchip: Enable pre console for rk3399 Enable pre console buffer for rk3399 platform. This would help to capture the console messages prior to the console being initialised. Enabling this would help to capture all the console messages on video output source like HDMI. So we can find the full console messages of U-Boot proper on HDMI display when enabled it for RK3399 platform boards. Buffer address used for pre console is 0x0f200000 which is ram base plus 240MiB. right now the Allwinner SoC is using similar computation. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang Tested-by: Peter Robinson --- arch/arm/mach-rockchip/Kconfig | 1 + common/Kconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index ed7514ab759..0cb1f23d0f3 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -229,6 +229,7 @@ config ROCKCHIP_RK3399 select DM_PMIC select DM_REGULATOR_FIXED select BOARD_LATE_INIT + imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_SDRAM_COMMON imply SPL_ROCKCHIP_COMMON_BOARD diff --git a/common/Kconfig b/common/Kconfig index 46e4193fc83..bd35de30560 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -568,6 +568,7 @@ config PRE_CON_BUF_ADDR default 0x2f000000 if ARCH_SUNXI && MACH_SUN9I default 0x4f000000 if ARCH_SUNXI && !MACH_SUN9I default 0x0f000000 if ROCKCHIP_RK3288 + default 0x0f200000 if ROCKCHIP_RK3399 help This sets the start address of the pre-console buffer. This must be in available memory and is accessed before relocation and -- cgit v1.2.3 From 9778edae5576e0a43a13387f9081ce11ef633025 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 2 Apr 2020 17:11:24 +0530 Subject: rockchip: Enable HDMI output on rk3399 board w/ HDMI Enable config options and console setting to respective rk3399 board for HDMI output. Boards supported and tested on this patch are: - NanoPc T4 - NanoPi M4 - NanoPi Neo4 - ROC-RK3399-PC - Rock960 Cc: Manivannan Sadhasivam Signed-off-by: Jagan Teki Tested-by: Peter Robinson Reviewed-by: Kever Yang --- configs/nanopc-t4-rk3399_defconfig | 7 +++++++ configs/nanopi-m4-rk3399_defconfig | 7 +++++++ configs/nanopi-neo4-rk3399_defconfig | 7 +++++++ configs/roc-pc-rk3399_defconfig | 6 ++++++ configs/rock960-rk3399_defconfig | 7 +++++++ include/configs/evb_rk3399.h | 5 +++++ include/configs/rock960_rk3399.h | 5 +++++ 7 files changed, 44 insertions(+) diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index 9ea9b11574f..607a00dbf76 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -52,5 +52,12 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_KEYBOARD=y CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_BPP16=y +CONFIG_VIDEO_BPP32=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index ad0e808bf61..3fcb7ac2d79 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -52,5 +52,12 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_KEYBOARD=y CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_BPP16=y +CONFIG_VIDEO_BPP32=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index d038a8cab94..b9ea535e435 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -52,5 +52,12 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_KEYBOARD=y CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_BPP16=y +CONFIG_VIDEO_BPP32=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index d540a17aebe..be76524cef7 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -59,3 +59,9 @@ CONFIG_USB_ETHER_SMSC95XX=y CONFIG_USB_KEYBOARD=y CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_BPP16=y +CONFIG_VIDEO_BPP32=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index ba4226e1735..c4e954731a0 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -58,5 +58,12 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_KEYBOARD=y CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_BPP16=y +CONFIG_VIDEO_BPP32=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h index c0b03588938..2d3db22877d 100644 --- a/include/configs/evb_rk3399.h +++ b/include/configs/evb_rk3399.h @@ -6,6 +6,11 @@ #ifndef __EVB_RK3399_H #define __EVB_RK3399_H +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + #include #if defined(CONFIG_ENV_IS_IN_MMC) diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h index 746d24cbff5..304ad2b7aae 100644 --- a/include/configs/rock960_rk3399.h +++ b/include/configs/rock960_rk3399.h @@ -6,6 +6,11 @@ #ifndef __ROCK960_RK3399_H #define __ROCK960_RK3399_H +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + #include #define CONFIG_SYS_MMC_ENV_DEV 1 -- cgit v1.2.3 From 05c65a82c3c1a1f5aced30babde51f934e066717 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 2 Apr 2020 17:11:25 +0530 Subject: video: rockchip: Support 4K resolution for rk3399, HDMI The default resolution for rockchip display is 1920x1080 which failed to work on 4K HDMI out displays on rk3399. So, mark the default resolution as 3480x2160 for rk3399 HDMI out. This would work all the hdmi display resolutions till 4K. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang Tested-by: Peter Robinson --- drivers/video/rockchip/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig index 10182d0b66c..cfd774ead60 100644 --- a/drivers/video/rockchip/Kconfig +++ b/drivers/video/rockchip/Kconfig @@ -22,6 +22,7 @@ menuconfig VIDEO_ROCKCHIP config VIDEO_ROCKCHIP_MAX_XRES int "Maximum horizontal resolution (for memory allocation purposes)" depends on VIDEO_ROCKCHIP + default 3480 if ROCKCHIP_RK3399 && DISPLAY_ROCKCHIP_HDMI default 1920 help The maximum horizontal resolution to support for the framebuffer. @@ -31,6 +32,7 @@ config VIDEO_ROCKCHIP_MAX_XRES config VIDEO_ROCKCHIP_MAX_YRES int "Maximum vertical resolution (for memory allocation purposes)" depends on VIDEO_ROCKCHIP + default 2160 if ROCKCHIP_RK3399 && DISPLAY_ROCKCHIP_HDMI default 1080 help The maximum vertical resolution to support for the framebuffer. -- cgit v1.2.3 From c9d1ff70e236a0d78ac07bdbadb5d6d7e8896361 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Fri, 27 Mar 2020 12:15:45 +0200 Subject: apalis-tk1: add update_uboot wrapper Add universal update_uboot wrapper that helps to update U-Boot image on internal storage. Create an proper tegra image: $ cbootimage -s tegra124 apalis-tk1.img.cfg apalis-tk1.img Flash in U-boot shell: > tftpboot ${loadaddr} ${board_name}/${board_name}.img > run update_uboot Signed-off-by: Igor Opaniuk Reviewed-by: Oleksandr Suvorov --- include/configs/apalis-tk1.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index 4127f2d6c62..8ca571b9b7a 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -46,6 +46,14 @@ "zImage fat 0 1 mmcpart 0; " \ "tegra124-apalis-eval.dtb fat 0 1 mmcpart 0" +#define UBOOT_UPDATE \ + "uboot_hwpart=1\0" \ + "uboot_blk=0\0" \ + "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \ + "setexpr blkcnt ${blkcnt} / 0x200\0" \ + "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \ + "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \ + #define EMMC_BOOTCMD \ "set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} " \ "ro rootfstype=ext4 rootwait\0" \ @@ -104,6 +112,7 @@ "fdt_module=" FDT_MODULE "\0" \ NFS_BOOTCMD \ SD_BOOTCMD \ + UBOOT_UPDATE \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ "00:14:2d:00:00:00; fi; pci enum && tftpboot ${loadaddr} " \ "flash_eth.img && source ${loadaddr}\0" \ -- cgit v1.2.3 From 195b48367fcb01ee0578f56615c2087ff756bbf2 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Fri, 27 Mar 2020 12:15:46 +0200 Subject: apalis_t30: add update_uboot wrapper Add universal update_uboot wrapper that helps to update U-Boot image on internal storage. Create an proper tegra image: $ cbootimage -s tegra30 apalis_t30.img.cfg apalis_t30.img Flash in U-boot shell: > tftpboot ${loadaddr} ${board_name}/${board_name}.img > run update_uboot Signed-off-by: Igor Opaniuk Reviewed-by: Oleksandr Suvorov --- include/configs/apalis_t30.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index 821162a2be8..701b34aa846 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -40,6 +40,17 @@ #undef CONFIG_SYS_MAXARGS #define CONFIG_SYS_MAXARGS 32 +#define UBOOT_UPDATE \ + "uboot_hwpart=1\0" \ + "uboot_blk=0\0" \ + "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \ + "setexpr blkcnt ${blkcnt} / 0x200\0" \ + "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \ + "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \ + +#define BOARD_EXTRA_ENV_SETTINGS \ + UBOOT_UPDATE + #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -- cgit v1.2.3 From a63dd9840096df8f8bb6d36981505ba7c42350d3 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Fri, 27 Mar 2020 12:15:47 +0200 Subject: colibri_t20: add update_uboot wrapper Add universal update_uboot wrapper that helps to update U-Boot image on internal storage(NAND). Create an proper tegra image: $ cbootimage -s tegra20 colibri_t20-512-v12-nand.img.cfg colibri_t20.img Flash in U-boot shell: > tftpboot ${loadaddr} ${board_name}/${board_name}.img > run update_uboot Signed-off-by: Igor Opaniuk Reviewed-by: Oleksandr Suvorov --- include/configs/colibri_t20.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index 122294de6fc..94e17bbb7cc 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -27,10 +27,14 @@ #define CONFIG_TEGRA_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 -/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */ +#define UBOOT_UPDATE \ + "update_uboot=nand erase.part u-boot && " \ + "nand write ${loadaddr} u-boot ${filesize}\0" \ +/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */ #define BOARD_EXTRA_ENV_SETTINGS \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + UBOOT_UPDATE /* Increase console I/O buffer size */ #undef CONFIG_SYS_CBSIZE -- cgit v1.2.3 From b308ffb0bf2171fe32aa6028340f9f5dad46ff8f Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Fri, 27 Mar 2020 12:15:48 +0200 Subject: colibri_t30: add update_uboot wrapper Add universal update_uboot wrapper that helps to update U-Boot image on internal storage. Create an proper tegra image: $ cbootimage -s tegra30 colibri_t30.img.cfg colibri_t30.img Flash in U-boot shell: > tftpboot ${loadaddr} ${board_name}/${board_name}.img > run update_uboot Signed-off-by: Igor Opaniuk Reviewed-by: Oleksandr Suvorov --- include/configs/colibri_t30.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index 5aecf14393a..4e5e89b547d 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -39,6 +39,17 @@ #undef CONFIG_SYS_MAXARGS #define CONFIG_SYS_MAXARGS 32 +#define UBOOT_UPDATE \ + "uboot_hwpart=1\0" \ + "uboot_blk=0\0" \ + "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \ + "setexpr blkcnt ${blkcnt} / 0x200\0" \ + "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \ + "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \ + +#define BOARD_EXTRA_ENV_SETTINGS \ + UBOOT_UPDATE + #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -- cgit v1.2.3 From 9eb15cbe5c94fca24519b5d89d934eeb34a68e5d Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 26 Mar 2020 15:20:45 -0700 Subject: ARM: tegra: p2371-2180: add I2C nodes to DT This adds to the DT the I2C controllers that connect to the board ID EEPROM, etc. With this change, you can now probe all I2C devices on a TX1 board. Signed-off-by: Tom Warren Acked-by: Stephen Warren --- arch/arm/dts/tegra210-p2371-2180.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/dts/tegra210-p2371-2180.dts b/arch/arm/dts/tegra210-p2371-2180.dts index c2f497c524a..649c163152e 100644 --- a/arch/arm/dts/tegra210-p2371-2180.dts +++ b/arch/arm/dts/tegra210-p2371-2180.dts @@ -12,6 +12,8 @@ aliases { i2c0 = "/i2c@7000d000"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; mmc0 = "/sdhci@700b0600"; mmc1 = "/sdhci@700b0000"; usb0 = "/usb@7d000000"; @@ -85,6 +87,16 @@ non-removable; }; + i2c@7000c400 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + i2c@7000d000 { status = "okay"; clock-frequency = <400000>; -- cgit v1.2.3 From d491dc09e4cfb7e513d3d6f448d811f1297753d9 Mon Sep 17 00:00:00 2001 From: JC Kuo Date: Thu, 26 Mar 2020 16:10:09 -0700 Subject: t210: do not enable PLLE and UPHY PLL HW PWRSEQ This commit removes the programming sequence that enables PLLE and UPHY PLL hardware power sequencers. Per TRM, boot software should enable PLLE and UPHY PLLs in software controlled power-on state and should power down PLL before jumping into kernel or the next stage boot software. Adds call to board_cleanup_before_linux to facilitate this. Signed-off-by: JC Kuo Signed-off-by: Tom Warren Acked-by: Stephen Warren --- arch/arm/cpu/armv8/cpu.c | 5 ++ arch/arm/include/asm/arch-tegra/xusb-padctl.h | 1 + arch/arm/mach-tegra/board2.c | 6 +++ arch/arm/mach-tegra/tegra210/clock.c | 19 -------- arch/arm/mach-tegra/tegra210/xusb-padctl.c | 68 +++++++++++++++++---------- arch/arm/mach-tegra/xusb-padctl-dummy.c | 4 ++ 6 files changed, 59 insertions(+), 44 deletions(-) diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c index 2467e0b87be..35752037bcf 100644 --- a/arch/arm/cpu/armv8/cpu.c +++ b/arch/arm/cpu/armv8/cpu.c @@ -32,6 +32,8 @@ void sdelay(unsigned long loops) "b.ne 1b" : "=r" (loops) : "0"(loops) : "cc"); } +void __weak board_cleanup_before_linux(void){} + int cleanup_before_linux(void) { /* @@ -40,6 +42,9 @@ int cleanup_before_linux(void) * * disable interrupt and turn off caches etc ... */ + + board_cleanup_before_linux(); + disable_interrupts(); /* diff --git a/arch/arm/include/asm/arch-tegra/xusb-padctl.h b/arch/arm/include/asm/arch-tegra/xusb-padctl.h index deccdf455d9..7e14d8109d1 100644 --- a/arch/arm/include/asm/arch-tegra/xusb-padctl.h +++ b/arch/arm/include/asm/arch-tegra/xusb-padctl.h @@ -16,6 +16,7 @@ struct tegra_xusb_phy; struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type); void tegra_xusb_padctl_init(void); +void tegra_xusb_padctl_exit(void); int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy); int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy); int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy); diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index d3497a2673e..787ff974203 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -181,6 +181,12 @@ int board_init(void) return nvidia_board_init(); } +void board_cleanup_before_linux(void) +{ + /* power down UPHY PLL */ + tegra_xusb_padctl_exit(); +} + #ifdef CONFIG_BOARD_EARLY_INIT_F static void __gpio_early_init(void) { diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index b240860f08c..f1b25e262a1 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -1235,25 +1235,6 @@ int tegra_plle_enable(void) value &= ~PLLE_SS_CNTL_INTERP_RESET; writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); - /* 7. Enable HW power sequencer for PLLE */ - - value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); - value &= ~PLLE_MISC_IDDQ_SWCTL; - writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); - - value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); - value &= ~PLLE_AUX_SS_SWCTL; - value &= ~PLLE_AUX_ENABLE_SWCTL; - value |= PLLE_AUX_SS_SEQ_INCLUDE; - value |= PLLE_AUX_USE_LOCKDET; - writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); - - /* 8. Wait 1 us */ - - udelay(1); - value |= PLLE_AUX_SEQ_ENABLE; - writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); - return 0; } diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c index ab6684f027c..64dc297ae27 100644 --- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c @@ -170,6 +170,17 @@ static int phy_unprepare(struct tegra_xusb_phy *phy) return tegra_xusb_padctl_disable(phy->padctl); } +#define XUSB_PADCTL_USB3_PAD_MUX 0x28 +#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE (1 << 0) +#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0 (1 << 1) +#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 (1 << 2) +#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2 (1 << 3) +#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 (1 << 4) +#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4 (1 << 5) +#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5 (1 << 6) +#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6 (1 << 7) +#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 (1 << 8) + #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20) #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20) @@ -366,31 +377,6 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy) value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN; padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); - value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); - value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL; - value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL; - value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET; - value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ; - writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); - - value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); - value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD; - padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); - - value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); - value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD; - padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); - - value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); - value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD; - padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); - - udelay(1); - - value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); - value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE; - writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); - debug("< %s()\n", __func__); return 0; } @@ -454,3 +440,35 @@ void tegra_xusb_padctl_init(void) ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata); debug("%s: done, ret=%d\n", __func__, ret); } + +void tegra_xusb_padctl_exit(void) +{ + u32 value; + + debug("> %s\n", __func__); + + value = padctl_readl(&padctl, XUSB_PADCTL_USB3_PAD_MUX); + value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE; + value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0; + value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1; + value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2; + value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3; + value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4; + value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5; + value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6; + value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0; + padctl_writel(&padctl, value, XUSB_PADCTL_USB3_PAD_MUX); + + value = padctl_readl(&padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); + value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ; + value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK; + value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(3); + value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE; + padctl_writel(&padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); + + reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1); + while (padctl.enable) + tegra_xusb_padctl_disable(&padctl); + + debug("< %s()\n", __func__); +} diff --git a/arch/arm/mach-tegra/xusb-padctl-dummy.c b/arch/arm/mach-tegra/xusb-padctl-dummy.c index 3ec27a2e3aa..f2d90302f6d 100644 --- a/arch/arm/mach-tegra/xusb-padctl-dummy.c +++ b/arch/arm/mach-tegra/xusb-padctl-dummy.c @@ -36,3 +36,7 @@ int __weak tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy) void __weak tegra_xusb_padctl_init(void) { } + +void __weak tegra_xusb_padctl_exit(void) +{ +} -- cgit v1.2.3 From 48ba1969c1deeb7599179d328be814362e4f63cc Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Thu, 26 Mar 2020 16:10:11 -0700 Subject: t210: pinmux: Remove pinmux/GPIO init from T210 boards T210 CBoot is now doing the full pinmux and GPIO init, based on the DTB tables. Remove pinmux/GPIO init tables & code from all T210-based builds below: p2371-2180 aka TX1 p2371-0000 e2220-1170 p2571 Signed-off-by: Tom Warren Acked-by: Stephen Warren --- arch/arm/mach-tegra/tegra210/Makefile | 3 +- arch/arm/mach-tegra/tegra210/pinmux.c | 194 -------------- board/nvidia/e2220-1170/e2220-1170.c | 21 +- board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 276 -------------------- board/nvidia/p2371-0000/p2371-0000.c | 21 +- board/nvidia/p2371-0000/pinmux-config-p2371-0000.h | 267 -------------------- board/nvidia/p2371-2180/p2371-2180.c | 21 +- board/nvidia/p2371-2180/pinmux-config-p2371-2180.h | 278 --------------------- board/nvidia/p2571/p2571.c | 21 +- board/nvidia/p2571/pinmux-config-p2571.h | 242 ------------------ 10 files changed, 5 insertions(+), 1339 deletions(-) delete mode 100644 arch/arm/mach-tegra/tegra210/pinmux.c delete mode 100644 board/nvidia/e2220-1170/pinmux-config-e2220-1170.h delete mode 100644 board/nvidia/p2371-0000/pinmux-config-p2371-0000.h delete mode 100644 board/nvidia/p2371-2180/pinmux-config-p2371-2180.h delete mode 100644 board/nvidia/p2571/pinmux-config-p2571.h diff --git a/arch/arm/mach-tegra/tegra210/Makefile b/arch/arm/mach-tegra/tegra210/Makefile index b6012fc7baa..cfcba5b68fe 100644 --- a/arch/arm/mach-tegra/tegra210/Makefile +++ b/arch/arm/mach-tegra/tegra210/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2013-2015 +# (C) Copyright 2013-2020 # NVIDIA Corporation # # SPDX-License-Identifier: GPL-2.0+ @@ -7,6 +7,5 @@ obj-y += clock.o obj-y += funcmux.o -obj-y += pinmux.o obj-y += xusb-padctl.o obj-y += ../xusb-padctl-common.o diff --git a/arch/arm/mach-tegra/tegra210/pinmux.c b/arch/arm/mach-tegra/tegra210/pinmux.c deleted file mode 100644 index 615809990ba..00000000000 --- a/arch/arm/mach-tegra/tegra210/pinmux.c +++ /dev/null @@ -1,194 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - */ - -#include -#include -#include - -#define PIN(pin, f0, f1, f2, f3) \ - { \ - .funcs = { \ - PMUX_FUNC_##f0, \ - PMUX_FUNC_##f1, \ - PMUX_FUNC_##f2, \ - PMUX_FUNC_##f3, \ - }, \ - } - -#define PIN_RESERVED {} - -static const struct pmux_pingrp_desc tegra210_pingroups[] = { - /* pin, f0, f1, f2, f3 */ - /* Offset 0x3000 */ - PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3), - PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3), - PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3), - PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3), - PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3), - PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3), - PIN_RESERVED, - /* Offset 0x301c */ - PIN(SDMMC3_CLK_PP0, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(SDMMC3_CMD_PP1, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(SDMMC3_DAT0_PP5, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(SDMMC3_DAT1_PP4, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(SDMMC3_DAT2_PP3, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(SDMMC3_DAT3_PP2, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN_RESERVED, - /* Offset 0x3038 */ - PIN(PEX_L0_RST_N_PA0, PE0, RSVD1, RSVD2, RSVD3), - PIN(PEX_L0_CLKREQ_N_PA1, PE0, RSVD1, RSVD2, RSVD3), - PIN(PEX_WAKE_N_PA2, PE, RSVD1, RSVD2, RSVD3), - PIN(PEX_L1_RST_N_PA3, PE1, RSVD1, RSVD2, RSVD3), - PIN(PEX_L1_CLKREQ_N_PA4, PE1, RSVD1, RSVD2, RSVD3), - PIN(SATA_LED_ACTIVE_PA5, SATA, RSVD1, RSVD2, RSVD3), - PIN(SPI1_MOSI_PC0, SPI1, RSVD1, RSVD2, RSVD3), - PIN(SPI1_MISO_PC1, SPI1, RSVD1, RSVD2, RSVD3), - PIN(SPI1_SCK_PC2, SPI1, RSVD1, RSVD2, RSVD3), - PIN(SPI1_CS0_PC3, SPI1, RSVD1, RSVD2, RSVD3), - PIN(SPI1_CS1_PC4, SPI1, RSVD1, RSVD2, RSVD3), - PIN(SPI2_MOSI_PB4, SPI2, DTV, RSVD2, RSVD3), - PIN(SPI2_MISO_PB5, SPI2, DTV, RSVD2, RSVD3), - PIN(SPI2_SCK_PB6, SPI2, DTV, RSVD2, RSVD3), - PIN(SPI2_CS0_PB7, SPI2, DTV, RSVD2, RSVD3), - PIN(SPI2_CS1_PDD0, SPI2, RSVD1, RSVD2, RSVD3), - PIN(SPI4_MOSI_PC7, SPI4, RSVD1, RSVD2, RSVD3), - PIN(SPI4_MISO_PD0, SPI4, RSVD1, RSVD2, RSVD3), - PIN(SPI4_SCK_PC5, SPI4, RSVD1, RSVD2, RSVD3), - PIN(SPI4_CS0_PC6, SPI4, RSVD1, RSVD2, RSVD3), - PIN(QSPI_SCK_PEE0, QSPI, RSVD1, RSVD2, RSVD3), - PIN(QSPI_CS_N_PEE1, QSPI, RSVD1, RSVD2, RSVD3), - PIN(QSPI_IO0_PEE2, QSPI, RSVD1, RSVD2, RSVD3), - PIN(QSPI_IO1_PEE3, QSPI, RSVD1, RSVD2, RSVD3), - PIN(QSPI_IO2_PEE4, QSPI, RSVD1, RSVD2, RSVD3), - PIN(QSPI_IO3_PEE5, QSPI, RSVD1, RSVD2, RSVD3), - PIN_RESERVED, - /* Offset 0x30a4 */ - PIN(DMIC1_CLK_PE0, DMIC1, I2S3, RSVD2, RSVD3), - PIN(DMIC1_DAT_PE1, DMIC1, I2S3, RSVD2, RSVD3), - PIN(DMIC2_CLK_PE2, DMIC2, I2S3, RSVD2, RSVD3), - PIN(DMIC2_DAT_PE3, DMIC2, I2S3, RSVD2, RSVD3), - PIN(DMIC3_CLK_PE4, DMIC3, I2S5A, RSVD2, RSVD3), - PIN(DMIC3_DAT_PE5, DMIC3, I2S5A, RSVD2, RSVD3), - PIN(GEN1_I2C_SCL_PJ1, I2C1, RSVD1, RSVD2, RSVD3), - PIN(GEN1_I2C_SDA_PJ0, I2C1, RSVD1, RSVD2, RSVD3), - PIN(GEN2_I2C_SCL_PJ2, I2C2, RSVD1, RSVD2, RSVD3), - PIN(GEN2_I2C_SDA_PJ3, I2C2, RSVD1, RSVD2, RSVD3), - PIN(GEN3_I2C_SCL_PF0, I2C3, RSVD1, RSVD2, RSVD3), - PIN(GEN3_I2C_SDA_PF1, I2C3, RSVD1, RSVD2, RSVD3), - PIN(CAM_I2C_SCL_PS2, I2C3, I2CVI, RSVD2, RSVD3), - PIN(CAM_I2C_SDA_PS3, I2C3, I2CVI, RSVD2, RSVD3), - PIN(PWR_I2C_SCL_PY3, I2CPMU, RSVD1, RSVD2, RSVD3), - PIN(PWR_I2C_SDA_PY4, I2CPMU, RSVD1, RSVD2, RSVD3), - PIN(UART1_TX_PU0, UARTA, RSVD1, RSVD2, RSVD3), - PIN(UART1_RX_PU1, UARTA, RSVD1, RSVD2, RSVD3), - PIN(UART1_RTS_PU2, UARTA, RSVD1, RSVD2, RSVD3), - PIN(UART1_CTS_PU3, UARTA, RSVD1, RSVD2, RSVD3), - PIN(UART2_TX_PG0, UARTB, I2S4A, SPDIF, UART), - PIN(UART2_RX_PG1, UARTB, I2S4A, SPDIF, UART), - PIN(UART2_RTS_PG2, UARTB, I2S4A, RSVD2, UART), - PIN(UART2_CTS_PG3, UARTB, I2S4A, RSVD2, UART), - PIN(UART3_TX_PD1, UARTC, SPI4, RSVD2, RSVD3), - PIN(UART3_RX_PD2, UARTC, SPI4, RSVD2, RSVD3), - PIN(UART3_RTS_PD3, UARTC, SPI4, RSVD2, RSVD3), - PIN(UART3_CTS_PD4, UARTC, SPI4, RSVD2, RSVD3), - PIN(UART4_TX_PI4, UARTD, UART, RSVD2, RSVD3), - PIN(UART4_RX_PI5, UARTD, UART, RSVD2, RSVD3), - PIN(UART4_RTS_PI6, UARTD, UART, RSVD2, RSVD3), - PIN(UART4_CTS_PI7, UARTD, UART, RSVD2, RSVD3), - PIN(DAP1_FS_PB0, I2S1, RSVD1, RSVD2, RSVD3), - PIN(DAP1_DIN_PB1, I2S1, RSVD1, RSVD2, RSVD3), - PIN(DAP1_DOUT_PB2, I2S1, RSVD1, RSVD2, RSVD3), - PIN(DAP1_SCLK_PB3, I2S1, RSVD1, RSVD2, RSVD3), - PIN(DAP2_FS_PAA0, I2S2, RSVD1, RSVD2, RSVD3), - PIN(DAP2_DIN_PAA2, I2S2, RSVD1, RSVD2, RSVD3), - PIN(DAP2_DOUT_PAA3, I2S2, RSVD1, RSVD2, RSVD3), - PIN(DAP2_SCLK_PAA1, I2S2, RSVD1, RSVD2, RSVD3), - PIN(DAP4_FS_PJ4, I2S4B, RSVD1, RSVD2, RSVD3), - PIN(DAP4_DIN_PJ5, I2S4B, RSVD1, RSVD2, RSVD3), - PIN(DAP4_DOUT_PJ6, I2S4B, RSVD1, RSVD2, RSVD3), - PIN(DAP4_SCLK_PJ7, I2S4B, RSVD1, RSVD2, RSVD3), - PIN(CAM1_MCLK_PS0, EXTPERIPH3, RSVD1, RSVD2, RSVD3), - PIN(CAM2_MCLK_PS1, EXTPERIPH3, RSVD1, RSVD2, RSVD3), - PIN(JTAG_RTCK, JTAG, RSVD1, RSVD2, RSVD3), - PIN(CLK_32K_IN, CLK, RSVD1, RSVD2, RSVD3), - PIN(CLK_32K_OUT_PY5, SOC, BLINK, RSVD2, RSVD3), - PIN(BATT_BCL, BCL, RSVD1, RSVD2, RSVD3), - PIN(CLK_REQ, SYS, RSVD1, RSVD2, RSVD3), - PIN(CPU_PWR_REQ, CPU, RSVD1, RSVD2, RSVD3), - PIN(PWR_INT_N, PMI, RSVD1, RSVD2, RSVD3), - PIN(SHUTDOWN, SHUTDOWN, RSVD1, RSVD2, RSVD3), - PIN(CORE_PWR_REQ, CORE, RSVD1, RSVD2, RSVD3), - PIN(AUD_MCLK_PBB0, AUD, RSVD1, RSVD2, RSVD3), - PIN(DVFS_PWM_PBB1, RSVD0, CLDVFS, SPI3, RSVD3), - PIN(DVFS_CLK_PBB2, RSVD0, CLDVFS, SPI3, RSVD3), - PIN(GPIO_X1_AUD_PBB3, RSVD0, RSVD1, SPI3, RSVD3), - PIN(GPIO_X3_AUD_PBB4, RSVD0, RSVD1, SPI3, RSVD3), - PIN(PCC7, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(HDMI_CEC_PCC0, CEC, RSVD1, RSVD2, RSVD3), - PIN(HDMI_INT_DP_HPD_PCC1, DP, RSVD1, RSVD2, RSVD3), - PIN(SPDIF_OUT_PCC2, SPDIF, RSVD1, RSVD2, RSVD3), - PIN(SPDIF_IN_PCC3, SPDIF, RSVD1, RSVD2, RSVD3), - PIN(USB_VBUS_EN0_PCC4, USB, RSVD1, RSVD2, RSVD3), - PIN(USB_VBUS_EN1_PCC5, USB, RSVD1, RSVD2, RSVD3), - PIN(DP_HPD0_PCC6, DP, RSVD1, RSVD2, RSVD3), - PIN(WIFI_EN_PH0, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(WIFI_RST_PH1, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(WIFI_WAKE_AP_PH2, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(AP_WAKE_BT_PH3, RSVD0, UARTB, SPDIF, RSVD3), - PIN(BT_RST_PH4, RSVD0, UARTB, SPDIF, RSVD3), - PIN(BT_WAKE_AP_PH5, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(AP_WAKE_NFC_PH7, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(NFC_EN_PI0, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(NFC_INT_PI1, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(GPS_EN_PI2, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(GPS_RST_PI3, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(CAM_RST_PS4, VGP1, RSVD1, RSVD2, RSVD3), - PIN(CAM_AF_EN_PS5, VIMCLK, VGP2, RSVD2, RSVD3), - PIN(CAM_FLASH_EN_PS6, VIMCLK, VGP3, RSVD2, RSVD3), - PIN(CAM1_PWDN_PS7, VGP4, RSVD1, RSVD2, RSVD3), - PIN(CAM2_PWDN_PT0, VGP5, RSVD1, RSVD2, RSVD3), - PIN(CAM1_STROBE_PT1, VGP6, RSVD1, RSVD2, RSVD3), - PIN(LCD_TE_PY2, DISPLAYA, RSVD1, RSVD2, RSVD3), - PIN(LCD_BL_PWM_PV0, DISPLAYA, PWM0, SOR0, RSVD3), - PIN(LCD_BL_EN_PV1, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(LCD_RST_PV2, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(LCD_GPIO1_PV3, DISPLAYB, RSVD1, RSVD2, RSVD3), - PIN(LCD_GPIO2_PV4, DISPLAYB, PWM1, RSVD2, SOR1), - PIN(AP_READY_PV5, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(TOUCH_RST_PV6, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(TOUCH_CLK_PV7, TOUCH, RSVD1, RSVD2, RSVD3), - PIN(MODEM_WAKE_AP_PX0, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(TOUCH_INT_PX1, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(MOTION_INT_PX2, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(ALS_PROX_INT_PX3, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(TEMP_ALERT_PX4, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(BUTTON_POWER_ON_PX5, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(BUTTON_VOL_UP_PX6, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(BUTTON_VOL_DOWN_PX7, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(BUTTON_SLIDE_SW_PY0, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(BUTTON_HOME_PY1, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(PA6, SATA, RSVD1, RSVD2, RSVD3), - PIN(PE6, RSVD0, I2S5A, PWM2, RSVD3), - PIN(PE7, RSVD0, I2S5A, PWM3, RSVD3), - PIN(PH6, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(PK0, IQC0, I2S5B, RSVD2, RSVD3), - PIN(PK1, IQC0, I2S5B, RSVD2, RSVD3), - PIN(PK2, IQC0, I2S5B, RSVD2, RSVD3), - PIN(PK3, IQC0, I2S5B, RSVD2, RSVD3), - PIN(PK4, IQC1, RSVD1, RSVD2, RSVD3), - PIN(PK5, IQC1, RSVD1, RSVD2, RSVD3), - PIN(PK6, IQC1, RSVD1, RSVD2, RSVD3), - PIN(PK7, IQC1, RSVD1, RSVD2, RSVD3), - PIN(PL0, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(PL1, SOC, RSVD1, RSVD2, RSVD3), - PIN(PZ0, VIMCLK2, RSVD1, RSVD2, RSVD3), - PIN(PZ1, VIMCLK2, SDMMC1, RSVD2, RSVD3), - PIN(PZ2, SDMMC3, CCLA, RSVD2, RSVD3), - PIN(PZ3, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(PZ4, SDMMC1, RSVD1, RSVD2, RSVD3), - PIN(PZ5, SOC, RSVD1, RSVD2, RSVD3), -}; -const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra210_pingroups; diff --git a/board/nvidia/e2220-1170/e2220-1170.c b/board/nvidia/e2220-1170/e2220-1170.c index 8baaf2c911f..5aac0404bf8 100644 --- a/board/nvidia/e2220-1170/e2220-1170.c +++ b/board/nvidia/e2220-1170/e2220-1170.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2019 * NVIDIA Corporation */ @@ -9,7 +9,6 @@ #include #include #include "../p2571/max77620_init.h" -#include "pinmux-config-e2220-1170.h" void pin_mux_mmc(void) { @@ -30,21 +29,3 @@ void pin_mux_mmc(void) if (ret) printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); } - -/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) -{ - pinmux_clear_tristate_input_clamping(); - - gpio_config_table(e2220_1170_gpio_inits, - ARRAY_SIZE(e2220_1170_gpio_inits)); - - pinmux_config_pingrp_table(e2220_1170_pingrps, - ARRAY_SIZE(e2220_1170_pingrps)); - - pinmux_config_drvgrp_table(e2220_1170_drvgrps, - ARRAY_SIZE(e2220_1170_drvgrps)); -} diff --git a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h deleted file mode 100644 index 14bbfbfc103..00000000000 --- a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h +++ /dev/null @@ -1,276 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - */ - -/* - * THIS FILE IS AUTO-GENERATED - DO NOT EDIT! - * - * To generate this file, use the tegra-pinmux-scripts tool available from - * https://github.com/NVIDIA/tegra-pinmux-scripts - * Run "board-to-uboot.py e2220-1170". - */ - -#ifndef _PINMUX_CONFIG_E2220_1170_H_ -#define _PINMUX_CONFIG_E2220_1170_H_ - -#define GPIO_INIT(_port, _gpio, _init) \ - { \ - .gpio = TEGRA_GPIO(_port, _gpio), \ - .init = TEGRA_GPIO_INIT_##_init, \ - } - -static const struct tegra_gpio_config e2220_1170_gpio_inits[] = { - /* port, pin, init_val */ - GPIO_INIT(A, 5, IN), - GPIO_INIT(A, 6, IN), - GPIO_INIT(B, 4, IN), - GPIO_INIT(E, 6, IN), - GPIO_INIT(G, 2, OUT0), - GPIO_INIT(G, 3, OUT0), - GPIO_INIT(H, 0, OUT0), - GPIO_INIT(H, 1, OUT0), - GPIO_INIT(H, 2, IN), - GPIO_INIT(H, 3, OUT0), - GPIO_INIT(H, 4, OUT0), - GPIO_INIT(H, 5, IN), - GPIO_INIT(H, 6, OUT0), - GPIO_INIT(H, 7, OUT0), - GPIO_INIT(I, 0, OUT0), - GPIO_INIT(I, 1, IN), - GPIO_INIT(I, 2, OUT0), - GPIO_INIT(I, 3, OUT0), - GPIO_INIT(K, 0, IN), - GPIO_INIT(K, 1, OUT0), - GPIO_INIT(K, 2, OUT0), - GPIO_INIT(K, 3, OUT0), - GPIO_INIT(K, 4, IN), - GPIO_INIT(K, 5, OUT0), - GPIO_INIT(K, 6, IN), - GPIO_INIT(K, 7, OUT0), - GPIO_INIT(L, 0, OUT0), - GPIO_INIT(S, 4, OUT0), - GPIO_INIT(S, 5, OUT0), - GPIO_INIT(S, 6, OUT0), - GPIO_INIT(S, 7, OUT0), - GPIO_INIT(T, 0, OUT0), - GPIO_INIT(T, 1, OUT0), - GPIO_INIT(V, 1, OUT0), - GPIO_INIT(V, 2, OUT0), - GPIO_INIT(V, 3, IN), - GPIO_INIT(V, 5, OUT0), - GPIO_INIT(V, 6, OUT0), - GPIO_INIT(X, 0, IN), - GPIO_INIT(X, 1, IN), - GPIO_INIT(X, 2, IN), - GPIO_INIT(X, 3, IN), - GPIO_INIT(X, 4, IN), - GPIO_INIT(X, 5, IN), - GPIO_INIT(X, 6, IN), - GPIO_INIT(X, 7, IN), - GPIO_INIT(Y, 0, IN), - GPIO_INIT(Y, 1, IN), - GPIO_INIT(Z, 0, IN), - GPIO_INIT(Z, 4, OUT0), - GPIO_INIT(BB, 2, OUT0), - GPIO_INIT(BB, 3, OUT0), - GPIO_INIT(BB, 4, IN), - GPIO_INIT(CC, 1, IN), - GPIO_INIT(CC, 5, OUT0), - GPIO_INIT(CC, 6, IN), - GPIO_INIT(CC, 7, OUT0), -}; - -#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .od = PMUX_PIN_OD_##_od, \ - .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ - .lock = PMUX_PIN_LOCK_DEFAULT, \ - } - -static const struct pmux_pingrp_config e2220_1170_pingrps[] = { - /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ - PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), - PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, UP, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(PEX_WAKE_N_PA2, PE, UP, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), - PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, UP, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PA6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI2_MOSI_PB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI1_MOSI_PC0, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI1_MISO_PC1, SPI1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI1_SCK_PC2, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI1_CS0_PC3, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI1_CS1_PC4, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI4_SCK_PC5, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI4_CS0_PC6, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI4_MOSI_PC7, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI4_MISO_PD0, SPI4, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART3_RX_PD2, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART3_CTS_PD4, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC1_CLK_PE0, DMIC1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(DMIC1_DAT_PE1, DMIC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC2_CLK_PE2, DMIC2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(DMIC2_DAT_PE3, DMIC2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC3_CLK_PE4, DMIC3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(DMIC3_DAT_PE5, DMIC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(UART2_TX_PG0, UART, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART2_RX_PG1, UART, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART2_RTS_PG2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART2_CTS_PG3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(WIFI_RST_PH1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PH6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GPS_RST_PI3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PK2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PK3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PK4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PK6, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PL0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PL1, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_GPIO1_PV3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(TOUCH_CLK_PV7, TOUCH, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_SLIDE_SW_PY0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GPIO_X3_AUD_PBB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(SPDIF_OUT_PCC2, SPDIF, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPDIF_IN_PCC3, SPDIF, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(USB_VBUS_EN1_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), - PINCFG(DP_HPD0_PCC6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), - PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_SCK_PEE0, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(QSPI_CS_N_PEE1, QSPI, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO0_PEE2, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO1_PEE3, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO2_PEE4, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO3_PEE5, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -}; - -#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ - { \ - .drvgrp = PMUX_DRVGRP_##_drvgrp, \ - .slwf = _slwf, \ - .slwr = _slwr, \ - .drvup = _drvup, \ - .drvdn = _drvdn, \ - .lpmd = PMUX_LPMD_##_lpmd, \ - .schmt = PMUX_SCHMT_##_schmt, \ - .hsm = PMUX_HSM_##_hsm, \ - } - -static const struct pmux_drvgrp_config e2220_1170_drvgrps[] = { -}; - -#endif /* PINMUX_CONFIG_E2220_1170_H */ diff --git a/board/nvidia/p2371-0000/p2371-0000.c b/board/nvidia/p2371-0000/p2371-0000.c index e0c907bd17c..5aac0404bf8 100644 --- a/board/nvidia/p2371-0000/p2371-0000.c +++ b/board/nvidia/p2371-0000/p2371-0000.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2019 * NVIDIA Corporation */ @@ -9,7 +9,6 @@ #include #include #include "../p2571/max77620_init.h" -#include "pinmux-config-p2371-0000.h" void pin_mux_mmc(void) { @@ -30,21 +29,3 @@ void pin_mux_mmc(void) if (ret) printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); } - -/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) -{ - pinmux_clear_tristate_input_clamping(); - - gpio_config_table(p2371_0000_gpio_inits, - ARRAY_SIZE(p2371_0000_gpio_inits)); - - pinmux_config_pingrp_table(p2371_0000_pingrps, - ARRAY_SIZE(p2371_0000_pingrps)); - - pinmux_config_drvgrp_table(p2371_0000_drvgrps, - ARRAY_SIZE(p2371_0000_drvgrps)); -} diff --git a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h deleted file mode 100644 index aa5d7f95d0f..00000000000 --- a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h +++ /dev/null @@ -1,267 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - */ - -/* - * THIS FILE IS AUTO-GENERATED - DO NOT EDIT! - * - * To generate this file, use the tegra-pinmux-scripts tool available from - * https://github.com/NVIDIA/tegra-pinmux-scripts - * Run "board-to-uboot.py p2371-0000". - */ - -#ifndef _PINMUX_CONFIG_P2371_0000_H_ -#define _PINMUX_CONFIG_P2371_0000_H_ - -#define GPIO_INIT(_port, _gpio, _init) \ - { \ - .gpio = TEGRA_GPIO(_port, _gpio), \ - .init = TEGRA_GPIO_INIT_##_init, \ - } - -static const struct tegra_gpio_config p2371_0000_gpio_inits[] = { - /* port, pin, init_val */ - GPIO_INIT(A, 5, IN), - GPIO_INIT(E, 4, OUT0), - GPIO_INIT(E, 6, IN), - GPIO_INIT(G, 0, IN), - GPIO_INIT(G, 3, OUT0), - GPIO_INIT(H, 0, OUT0), - GPIO_INIT(H, 2, IN), - GPIO_INIT(H, 3, OUT0), - GPIO_INIT(H, 4, OUT0), - GPIO_INIT(H, 5, IN), - GPIO_INIT(H, 6, OUT0), - GPIO_INIT(H, 7, OUT0), - GPIO_INIT(I, 0, OUT0), - GPIO_INIT(I, 1, IN), - GPIO_INIT(I, 2, OUT0), - GPIO_INIT(I, 3, OUT0), - GPIO_INIT(K, 4, IN), - GPIO_INIT(K, 5, OUT0), - GPIO_INIT(K, 6, IN), - GPIO_INIT(K, 7, OUT0), - GPIO_INIT(L, 0, OUT0), - GPIO_INIT(S, 4, OUT0), - GPIO_INIT(S, 5, OUT0), - GPIO_INIT(S, 6, OUT0), - GPIO_INIT(S, 7, OUT0), - GPIO_INIT(T, 0, OUT0), - GPIO_INIT(T, 1, OUT0), - GPIO_INIT(V, 1, OUT0), - GPIO_INIT(V, 2, OUT0), - GPIO_INIT(V, 5, OUT0), - GPIO_INIT(V, 6, OUT0), - GPIO_INIT(V, 7, OUT1), - GPIO_INIT(X, 0, IN), - GPIO_INIT(X, 1, IN), - GPIO_INIT(X, 2, IN), - GPIO_INIT(X, 3, IN), - GPIO_INIT(X, 4, IN), - GPIO_INIT(X, 5, IN), - GPIO_INIT(X, 6, IN), - GPIO_INIT(X, 7, IN), - GPIO_INIT(Y, 1, IN), - GPIO_INIT(Z, 0, IN), - GPIO_INIT(Z, 4, OUT0), - GPIO_INIT(BB, 2, OUT0), - GPIO_INIT(BB, 3, OUT0), - GPIO_INIT(CC, 1, IN), - GPIO_INIT(CC, 6, IN), - GPIO_INIT(CC, 7, OUT0), -}; - -#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .od = PMUX_PIN_OD_##_od, \ - .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ - .lock = PMUX_PIN_LOCK_DEFAULT, \ - } - -static const struct pmux_pingrp_config p2371_0000_pingrps[] = { - /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ - PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), - PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), - PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PA6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI2_MOSI_PB4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI1_MOSI_PC0, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI1_MISO_PC1, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI1_SCK_PC2, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI1_CS0_PC3, SPI1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI1_CS1_PC4, SPI1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI4_SCK_PC5, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI4_CS0_PC6, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI4_MOSI_PC7, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI4_MISO_PD0, SPI4, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART3_RX_PD2, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC1_CLK_PE0, DMIC1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(DMIC1_DAT_PE1, DMIC1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC2_CLK_PE2, DMIC2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(DMIC2_DAT_PE3, DMIC2, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC3_CLK_PE4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(UART2_TX_PG0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART2_RX_PG1, UARTB, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART2_RTS_PG2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART2_CTS_PG3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PH6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GPS_RST_PI3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK0, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK1, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK2, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK3, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PK6, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PL0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PL1, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(TOUCH_CLK_PV7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PZ3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(USB_VBUS_EN1_PCC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), - PINCFG(DP_HPD0_PCC6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), - PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -}; - -#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ - { \ - .drvgrp = PMUX_DRVGRP_##_drvgrp, \ - .slwf = _slwf, \ - .slwr = _slwr, \ - .drvup = _drvup, \ - .drvdn = _drvdn, \ - .lpmd = PMUX_LPMD_##_lpmd, \ - .schmt = PMUX_SCHMT_##_schmt, \ - .hsm = PMUX_HSM_##_hsm, \ - } - -static const struct pmux_drvgrp_config p2371_0000_drvgrps[] = { -}; - -#endif /* PINMUX_CONFIG_P2371_0000_H */ diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index fa5288bf185..1756bbca985 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2019 * NVIDIA Corporation */ @@ -13,7 +13,6 @@ #include #include #include "../p2571/max77620_init.h" -#include "pinmux-config-p2371-2180.h" void pin_mux_mmc(void) { @@ -57,24 +56,6 @@ void pin_mux_mmc(void) } } -/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) -{ - pinmux_clear_tristate_input_clamping(); - - gpio_config_table(p2371_2180_gpio_inits, - ARRAY_SIZE(p2371_2180_gpio_inits)); - - pinmux_config_pingrp_table(p2371_2180_pingrps, - ARRAY_SIZE(p2371_2180_pingrps)); - - pinmux_config_drvgrp_table(p2371_2180_drvgrps, - ARRAY_SIZE(p2371_2180_drvgrps)); -} - #ifdef CONFIG_PCI_TEGRA int tegra_pcie_board_init(void) { diff --git a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h deleted file mode 100644 index d9abfa7115a..00000000000 --- a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h +++ /dev/null @@ -1,278 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - */ - -/* - * THIS FILE IS AUTO-GENERATED - DO NOT EDIT! - * - * To generate this file, use the tegra-pinmux-scripts tool available from - * https://github.com/NVIDIA/tegra-pinmux-scripts - * Run "board-to-uboot.py p2371-2180". - */ - -#ifndef _PINMUX_CONFIG_P2371_2180_H_ -#define _PINMUX_CONFIG_P2371_2180_H_ - -#define GPIO_INIT(_port, _gpio, _init) \ - { \ - .gpio = TEGRA_GPIO(_port, _gpio), \ - .init = TEGRA_GPIO_INIT_##_init, \ - } - -static const struct tegra_gpio_config p2371_2180_gpio_inits[] = { - /* port, pin, init_val */ - GPIO_INIT(A, 5, IN), - GPIO_INIT(B, 0, IN), - GPIO_INIT(B, 1, IN), - GPIO_INIT(B, 2, IN), - GPIO_INIT(B, 3, IN), - GPIO_INIT(C, 0, IN), - GPIO_INIT(C, 1, IN), - GPIO_INIT(C, 2, IN), - GPIO_INIT(C, 3, IN), - GPIO_INIT(C, 4, IN), - GPIO_INIT(E, 4, IN), - GPIO_INIT(E, 5, IN), - GPIO_INIT(E, 6, IN), - GPIO_INIT(H, 0, OUT0), - GPIO_INIT(H, 1, OUT0), - GPIO_INIT(H, 2, IN), - GPIO_INIT(H, 3, OUT0), - GPIO_INIT(H, 4, OUT0), - GPIO_INIT(H, 5, IN), - GPIO_INIT(H, 6, IN), - GPIO_INIT(H, 7, IN), - GPIO_INIT(I, 0, OUT0), - GPIO_INIT(I, 1, IN), - GPIO_INIT(I, 2, OUT0), - GPIO_INIT(K, 4, IN), - GPIO_INIT(K, 5, OUT0), - GPIO_INIT(K, 6, IN), - GPIO_INIT(K, 7, IN), - GPIO_INIT(L, 1, IN), - GPIO_INIT(S, 4, OUT0), - GPIO_INIT(S, 5, OUT0), - GPIO_INIT(S, 6, OUT0), - GPIO_INIT(S, 7, OUT0), - GPIO_INIT(T, 0, OUT0), - GPIO_INIT(T, 1, OUT0), - GPIO_INIT(U, 2, IN), - GPIO_INIT(U, 3, IN), - GPIO_INIT(V, 1, OUT0), - GPIO_INIT(V, 2, OUT0), - GPIO_INIT(V, 3, IN), - GPIO_INIT(V, 5, OUT0), - GPIO_INIT(V, 6, OUT0), - GPIO_INIT(X, 0, IN), - GPIO_INIT(X, 1, IN), - GPIO_INIT(X, 2, IN), - GPIO_INIT(X, 3, IN), - GPIO_INIT(X, 4, IN), - GPIO_INIT(X, 5, IN), - GPIO_INIT(X, 6, IN), - GPIO_INIT(X, 7, IN), - GPIO_INIT(Y, 0, IN), - GPIO_INIT(Y, 1, IN), - GPIO_INIT(Z, 0, IN), - GPIO_INIT(Z, 2, IN), - GPIO_INIT(Z, 3, OUT0), - GPIO_INIT(BB, 0, IN), - GPIO_INIT(BB, 2, OUT0), - GPIO_INIT(BB, 3, IN), - GPIO_INIT(CC, 1, IN), -}; - -#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .od = PMUX_PIN_OD_##_od, \ - .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ - .lock = PMUX_PIN_LOCK_DEFAULT, \ - } - -static const struct pmux_pingrp_config p2371_2180_pingrps[] = { - /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ - PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), - PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), - PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PA6, SATA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(DAP1_FS_PB0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP1_DIN_PB1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP1_DOUT_PB2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP1_SCLK_PB3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI2_MOSI_PB4, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI2_MISO_PB5, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI2_SCK_PB6, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI2_CS0_PB7, SPI2, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI1_MOSI_PC0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI1_MISO_PC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI1_SCK_PC2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI1_CS0_PC3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI1_CS1_PC4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI4_SCK_PC5, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI4_CS0_PC6, SPI4, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI4_MOSI_PC7, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI4_MISO_PD0, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART3_RX_PD2, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC3_CLK_PE4, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC3_DAT_PE5, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PE6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(UART2_TX_PG0, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART2_RX_PG1, UARTB, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART2_RTS_PG2, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART2_CTS_PG3, UARTB, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(WIFI_RST_PH1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(AP_WAKE_NFC_PH7, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(NFC_INT_PI1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK0, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK1, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK2, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK3, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PK6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PL1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART1_RTS_PU2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART1_CTS_PU3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_GPIO1_PV3, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(TOUCH_CLK_PV7, TOUCH, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(ALS_PROX_INT_PX3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_SLIDE_SW_PY0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PZ4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(AUD_MCLK_PBB0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(USB_VBUS_EN1_PCC5, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(DP_HPD0_PCC6, DP, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), - PINCFG(SPI2_CS1_PDD0, SPI2, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CLK_REQ, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -}; - -#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ - { \ - .drvgrp = PMUX_DRVGRP_##_drvgrp, \ - .slwf = _slwf, \ - .slwr = _slwr, \ - .drvup = _drvup, \ - .drvdn = _drvdn, \ - .lpmd = PMUX_LPMD_##_lpmd, \ - .schmt = PMUX_SCHMT_##_schmt, \ - .hsm = PMUX_HSM_##_hsm, \ - } - -static const struct pmux_drvgrp_config p2371_2180_drvgrps[] = { -}; - -#endif /* PINMUX_CONFIG_P2371_2180_H */ diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c index dba3579ad2d..a9e4d21e7b0 100644 --- a/board/nvidia/p2571/p2571.c +++ b/board/nvidia/p2571/p2571.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2019 * NVIDIA Corporation */ @@ -10,7 +10,6 @@ #include #include #include "max77620_init.h" -#include "pinmux-config-p2571.h" void pin_mux_mmc(void) { @@ -32,24 +31,6 @@ void pin_mux_mmc(void) printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); } -/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) -{ - pinmux_clear_tristate_input_clamping(); - - gpio_config_table(p2571_gpio_inits, - ARRAY_SIZE(p2571_gpio_inits)); - - pinmux_config_pingrp_table(p2571_pingrps, - ARRAY_SIZE(p2571_pingrps)); - - pinmux_config_drvgrp_table(p2571_drvgrps, - ARRAY_SIZE(p2571_drvgrps)); -} - /* * Routine: start_cpu_fan * Description: Enable/start PWM CPU fan on P2571 diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h deleted file mode 100644 index 04bb6ce2077..00000000000 --- a/board/nvidia/p2571/pinmux-config-p2571.h +++ /dev/null @@ -1,242 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - */ - -/* - * THIS FILE IS AUTO-GENERATED - DO NOT EDIT! - * - * To generate this file, use the tegra-pinmux-scripts tool available from - * https://github.com/NVIDIA/tegra-pinmux-scripts - * Run "board-to-uboot.py p2571". - */ - -#ifndef _PINMUX_CONFIG_P2571_H_ -#define _PINMUX_CONFIG_P2571_H_ - -#define GPIO_INIT(_port, _gpio, _init) \ - { \ - .gpio = TEGRA_GPIO(_port, _gpio), \ - .init = TEGRA_GPIO_INIT_##_init, \ - } - -static const struct tegra_gpio_config p2571_gpio_inits[] = { - /* port, pin, init_val */ - GPIO_INIT(A, 0, IN), - GPIO_INIT(A, 5, IN), - GPIO_INIT(D, 4, IN), - GPIO_INIT(E, 4, OUT0), - GPIO_INIT(G, 0, IN), - GPIO_INIT(H, 0, OUT0), - GPIO_INIT(H, 2, IN), - GPIO_INIT(H, 3, OUT0), - GPIO_INIT(H, 4, OUT0), - GPIO_INIT(H, 5, IN), - GPIO_INIT(I, 0, OUT0), - GPIO_INIT(I, 1, IN), - GPIO_INIT(V, 1, OUT0), - GPIO_INIT(V, 6, OUT1), - GPIO_INIT(X, 4, IN), - GPIO_INIT(X, 6, IN), - GPIO_INIT(X, 7, IN), - GPIO_INIT(Y, 1, IN), - GPIO_INIT(Z, 0, IN), - GPIO_INIT(Z, 4, OUT0), - GPIO_INIT(BB, 2, OUT0), - GPIO_INIT(CC, 1, IN), - GPIO_INIT(CC, 3, IN), -}; - -#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .od = PMUX_PIN_OD_##_od, \ - .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ - .lock = PMUX_PIN_LOCK_DEFAULT, \ - } - -static const struct pmux_pingrp_config p2571_pingrps[] = { - /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ - PINCFG(PEX_L0_RST_N_PA0, DEFAULT, UP, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(PEX_L0_CLKREQ_N_PA1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), - PINCFG(PEX_WAKE_N_PA2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), - PINCFG(PEX_L1_RST_N_PA3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), - PINCFG(PEX_L1_CLKREQ_N_PA4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), - PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PA6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(DAP1_FS_PB0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(DAP1_DIN_PB1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(DAP1_DOUT_PB2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(DAP1_SCLK_PB3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI2_MOSI_PB4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI1_MOSI_PC0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI1_MISO_PC1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI1_SCK_PC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI1_CS0_PC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI1_CS1_PC4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI4_SCK_PC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI4_CS0_PC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI4_MOSI_PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI4_MISO_PD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART3_TX_PD1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART3_RX_PD2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART3_RTS_PD3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART3_CTS_PD4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC3_CLK_PE4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PE6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(UART2_TX_PG0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART2_RX_PG1, UARTB, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART2_RTS_PG2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART2_CTS_PG3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PH6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(AP_WAKE_NFC_PH7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(GPS_EN_PI2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(DAP4_FS_PJ4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(DAP4_DIN_PJ5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(DAP4_DOUT_PJ6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(DAP4_SCLK_PJ7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PK0, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PK1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PK2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PK3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PK4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PK5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PK6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PK7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PL1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(CAM1_MCLK_PS0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM2_MCLK_PS1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(CAM_RST_PS4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_AF_EN_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_FLASH_EN_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM1_PWDN_PS7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM2_PWDN_PT0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM1_STROBE_PT1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_RST_PV2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(AP_READY_PV5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(TOUCH_CLK_PV7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(MODEM_WAKE_AP_PX0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(TOUCH_INT_PX1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(MOTION_INT_PX2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(ALS_PROX_INT_PX3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_POWER_ON_PX5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(LCD_TE_PY2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PZ3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GPIO_X1_AUD_PBB3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPDIF_IN_PCC3, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(USB_VBUS_EN1_PCC5, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(DP_HPD0_PCC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), - PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -}; - -#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ - { \ - .drvgrp = PMUX_DRVGRP_##_drvgrp, \ - .slwf = _slwf, \ - .slwr = _slwr, \ - .drvup = _drvup, \ - .drvdn = _drvdn, \ - .lpmd = PMUX_LPMD_##_lpmd, \ - .schmt = PMUX_SCHMT_##_schmt, \ - .hsm = PMUX_HSM_##_hsm, \ - } - -static const struct pmux_drvgrp_config p2571_drvgrps[] = { -}; - -#endif /* PINMUX_CONFIG_P2571_H */ -- cgit v1.2.3 From d43c1dc2e8e8b0c5c3203d4dfbd71607d65dbf1e Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Fri, 27 Mar 2020 10:24:31 -0700 Subject: i2c: t210: Add VI_I2C clock source support Fix VI_I2C clock source type. Will be needed by VI_I2C driver. Also added use of INTERNAL_ID macro in two places, needed to keep the id returned to 8 bits. Signed-off-by: Tom Warren --- arch/arm/mach-tegra/tegra210/clock.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index f1b25e262a1..00c65c281fc 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2020 * NVIDIA Corporation */ @@ -333,7 +333,7 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { TYPE(PERIPHC_DMIC3, CLOCK_TYPE_NONE), TYPE(PERIPHC_APE, CLOCK_TYPE_NONE), TYPE(PERIPHC_QSPI, CLOCK_TYPE_PC01C00_C42C41TC40), - TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_NONE), + TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_PC2CC3M_T16), TYPE(PERIPHC_USB2_HSIC_TRK, CLOCK_TYPE_NONE), TYPE(PERIPHC_PEX_SATA_USB_RX_BYP, CLOCK_TYPE_NONE), @@ -739,7 +739,7 @@ int get_periph_clock_info(enum periph_id periph_id, int *mux_bits, if (!clock_periph_id_isvalid(periph_id)) return -1; - internal_id = periph_id_to_internal_id[periph_id]; + internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]); if (!periphc_internal_id_isvalid(internal_id)) return -1; @@ -765,7 +765,7 @@ enum clock_id get_periph_clock_id(enum periph_id periph_id, int source) if (!clock_periph_id_isvalid(periph_id)) return CLOCK_ID_NONE; - internal_id = periph_id_to_internal_id[periph_id]; + internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]); if (!periphc_internal_id_isvalid(internal_id)) return CLOCK_ID_NONE; -- cgit v1.2.3 From c0d436fe892f1cc31bde3426834fe8512bc8a029 Mon Sep 17 00:00:00 2001 From: Vishruth Date: Thu, 26 Mar 2020 15:20:43 -0700 Subject: ARM: tegra: p2771-0000: enable PIE relocation U-Boot is configured to build as position independent executable. Enable relocation of RELA section required to work with different load addresses. Signed-off-by: Vishruth Signed-off-by: Tom Warren Reviewed-by: Stephen Warren Tested-by: Peter Robinson --- configs/p2771-0000-000_defconfig | 1 + configs/p2771-0000-500_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig index 06f12e2b952..e347a7728b0 100644 --- a/configs/p2771-0000-000_defconfig +++ b/configs/p2771-0000-000_defconfig @@ -36,3 +36,4 @@ CONFIG_TEGRA186_POWER_DOMAIN=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_POSITION_INDEPENDENT=y diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig index 1a14a9244ae..0803b26cd81 100644 --- a/configs/p2771-0000-500_defconfig +++ b/configs/p2771-0000-500_defconfig @@ -36,3 +36,4 @@ CONFIG_TEGRA186_POWER_DOMAIN=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_POSITION_INDEPENDENT=y -- cgit v1.2.3 From 224595abaae918a64fba2625553e51a482ead084 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Thu, 26 Mar 2020 15:59:14 -0700 Subject: tegra: Enable CONFIG_BOOTP_PREFER_SERVERIP for all Jetson boards This allows the user to set $serverip in the environment before executing a DHCP request. If they do, U-Boot will use that IP rather than using the IP in the DHCP response. Signed-off-by: Tom Warren Acked-by: Stephen Warren --- configs/e2220-1170_defconfig | 1 + configs/p2371-0000_defconfig | 1 + configs/p2371-2180_defconfig | 1 + configs/p2571_defconfig | 1 + configs/p2771-0000-000_defconfig | 1 + configs/p2771-0000-500_defconfig | 1 + 6 files changed, 6 insertions(+) diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig index 16390400278..951ed1df55c 100644 --- a/configs/e2220-1170_defconfig +++ b/configs/e2220-1170_defconfig @@ -43,3 +43,4 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig index 2070199016c..70817194c35 100644 --- a/configs/p2371-0000_defconfig +++ b/configs/p2371-0000_defconfig @@ -44,3 +44,4 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index 8c808ae7e82..c70217c82d5 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -52,3 +52,4 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index 721c5c5f360..43c24b83304 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -44,3 +44,4 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig index e347a7728b0..8bf84193e60 100644 --- a/configs/p2771-0000-000_defconfig +++ b/configs/p2771-0000-000_defconfig @@ -37,3 +37,4 @@ CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_POSITION_INDEPENDENT=y +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig index 0803b26cd81..1f40333b0e3 100644 --- a/configs/p2771-0000-500_defconfig +++ b/configs/p2771-0000-500_defconfig @@ -37,3 +37,4 @@ CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_POSITION_INDEPENDENT=y +CONFIG_BOOTP_PREFER_SERVERIP=y -- cgit v1.2.3 From 5e965e814067e7539943bbaeb47d7bf9738a701b Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Wed, 29 May 2019 09:30:01 -0700 Subject: mmc: t210: Add autocal and tap/trim updates for SDMMC1/3 As per the T210 TRM, when running at 3.3v, the SDMMC1 tap/trim and autocal values need to be set to condition the signals correctly before talking to the SD-card. This is the same as what's being done in CBoot, but it gets reset when the SDMMC1 HW is soft-reset during SD driver init, so needs to be repeated here. Also set autocal and tap/trim for SDMMC3, although no T210 boards use it for SD-card at this time. Signed-off-by: Tom Warren Reviewed-by: Jaehoon Chung --- arch/arm/include/asm/arch-tegra/tegra_mmc.h | 20 +++++-- drivers/mmc/tegra_mmc.c | 84 ++++++++++++++++++++++++++--- 2 files changed, 92 insertions(+), 12 deletions(-) diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index a2b6f63ff0e..a8bfa466c02 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -2,7 +2,7 @@ /* * (C) Copyright 2009 SAMSUNG Electronics * Minkyu Kang - * Portions Copyright (C) 2011-2012 NVIDIA Corporation + * Portions Copyright (C) 2011-2012,2019 NVIDIA Corporation */ #ifndef __TEGRA_MMC_H_ @@ -52,7 +52,7 @@ struct tegra_mmc { unsigned char admaerr; /* offset 54h */ unsigned char res4[3]; /* RESERVED, offset 55h-57h */ unsigned long admaaddr; /* offset 58h-5Fh */ - unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */ + unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */ unsigned short slotintstatus; /* offset FCh */ unsigned short hcver; /* HOST Version */ unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */ @@ -127,11 +127,23 @@ struct tegra_mmc { #define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1) -/* SDMMC1/3 settings from section 24.6 of T30 TRM */ +/* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */ #define MEMCOMP_PADCTRL_VREF 7 -#define AUTO_CAL_ENABLED (1 << 29) +#define AUTO_CAL_ENABLE (1 << 29) +#if defined(CONFIG_TEGRA210) +#define AUTO_CAL_ACTIVE (1 << 31) +#define AUTO_CAL_START (1 << 31) +#define AUTO_CAL_PD_OFFSET (0x7D << 8) +#define AUTO_CAL_PU_OFFSET (0 << 0) +#define IO_TRIM_BYPASS_MASK (1 << 2) +#define TRIM_VAL_SHIFT 24 +#define TRIM_VAL_MASK (0x1F << TRIM_VAL_SHIFT) +#define TAP_VAL_SHIFT 16 +#define TAP_VAL_MASK (0xFF << TAP_VAL_SHIFT) +#else #define AUTO_CAL_PD_OFFSET (0x70 << 8) #define AUTO_CAL_PU_OFFSET (0x62 << 0) +#endif #endif /* __ASSEMBLY__ */ #endif /* __TEGRA_MMC_H_ */ diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index f022e935525..73ac58c6c8d 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -3,7 +3,7 @@ * (C) Copyright 2009 SAMSUNG Electronics * Minkyu Kang * Jaehoon Chung - * Portions Copyright 2011-2016 NVIDIA Corporation + * Portions Copyright 2011-2019 NVIDIA Corporation */ #include @@ -15,6 +15,9 @@ #include #include #include +#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210) +#include +#endif struct tegra_mmc_plat { struct mmc_config cfg; @@ -30,6 +33,7 @@ struct tegra_mmc_priv { struct gpio_desc wp_gpio; /* Write Protect GPIO */ unsigned int version; /* SDHCI spec. version */ unsigned int clock; /* Current clock (MHz) */ + int mmc_id; /* peripheral id */ }; static void tegra_mmc_set_power(struct tegra_mmc_priv *priv, @@ -446,16 +450,19 @@ static int tegra_mmc_set_ios(struct udevice *dev) static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv) { -#if defined(CONFIG_TEGRA30) +#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210) u32 val; + u16 clk_con; + int timeout; + int id = priv->mmc_id; - debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg); + debug("%s: sdmmc address = %p, id = %d\n", __func__, + priv->reg, id); /* Set the pad drive strength for SDMMC1 or 3 only */ - if (priv->reg != (void *)0x78000000 && - priv->reg != (void *)0x78000400) { + if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", - __func__); + __func__); return; } @@ -464,11 +471,65 @@ static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv) val |= MEMCOMP_PADCTRL_VREF; writel(val, &priv->reg->sdmemcmppadctl); + /* Disable SD Clock Enable before running auto-cal as per TRM */ + clk_con = readw(&priv->reg->clkcon); + debug("%s: CLOCK_CONTROL = 0x%04X\n", __func__, clk_con); + clk_con &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; + writew(clk_con, &priv->reg->clkcon); + val = readl(&priv->reg->autocalcfg); val &= 0xFFFF0000; - val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; + val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET; writel(val, &priv->reg->autocalcfg); -#endif + val |= AUTO_CAL_START | AUTO_CAL_ENABLE; + writel(val, &priv->reg->autocalcfg); + debug("%s: AUTO_CAL_CFG = 0x%08X\n", __func__, val); + udelay(1); + timeout = 100; /* 10 mSec max (100*100uS) */ + do { + val = readl(&priv->reg->autocalsts); + udelay(100); + } while ((val & AUTO_CAL_ACTIVE) && --timeout); + val = readl(&priv->reg->autocalsts); + debug("%s: Final AUTO_CAL_STATUS = 0x%08X, timeout = %d\n", + __func__, val, timeout); + + /* Re-enable SD Clock Enable when auto-cal is done */ + clk_con |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; + writew(clk_con, &priv->reg->clkcon); + clk_con = readw(&priv->reg->clkcon); + debug("%s: final CLOCK_CONTROL = 0x%04X\n", __func__, clk_con); + + if (timeout == 0) { + printf("%s: Warning: Autocal timed out!\n", __func__); + /* TBD: Set CFG2TMC_SDMMC1_PAD_CAL_DRV* regs here */ + } + +#if defined(CONFIG_TEGRA210) + u32 tap_value, trim_value; + + /* Set tap/trim values for SDMMC1/3 @ <48MHz here */ + val = readl(&priv->reg->venspictl); /* aka VENDOR_SYS_SW_CNTL */ + val &= IO_TRIM_BYPASS_MASK; + if (id == PERIPH_ID_SDMMC1) { + tap_value = 4; /* default */ + if (val) + tap_value = 3; + trim_value = 2; + } else { /* SDMMC3 */ + tap_value = 3; + trim_value = 3; + } + + val = readl(&priv->reg->venclkctl); + val &= ~TRIM_VAL_MASK; + val |= (trim_value << TRIM_VAL_SHIFT); + val &= ~TAP_VAL_MASK; + val |= (tap_value << TAP_VAL_SHIFT); + writel(val, &priv->reg->venclkctl); + debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val); +#endif /* T210 */ +#endif /* T30/T210 */ } static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc) @@ -514,6 +575,13 @@ static int tegra_mmc_init(struct udevice *dev) unsigned int mask; debug(" tegra_mmc_init called\n"); +#if defined(CONFIG_TEGRA210) + priv->mmc_id = clock_decode_periph_id(dev); + if (priv->mmc_id == PERIPH_ID_NONE) { + printf("%s: Missing/invalid peripheral ID\n", __func__); + return -EINVAL; + } +#endif tegra_mmc_reset(priv, mmc); #if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK) -- cgit v1.2.3 From a482f32992230d8bdae2caa72056ab7d9208d5f0 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Mon, 3 Jun 2019 16:06:34 -0700 Subject: mmc: t210: Fix 'bad' SD-card clock when doing 400KHz card detect According to the HW team, for some reason the normal clock select code picks what appears to be a perfectly valid 375KHz SD card clock, based on the CAR clock source and SDMMC1 controller register settings (CAR = 408MHz PLLP0 divided by 68 for 6MHz, then a SD Clock Control register divisor of 16 = 375KHz). But the resulting SD card clock, as measured by the HW team, is 700KHz, which is out-of-spec. So the WAR is to use the values given in the TRM PLLP table to generate a 400KHz SD-clock (CAR clock of 24.7MHz, SD Clock Control divisor of 62) only for SDMMC1 on T210 when the requested clock is <= 400KHz. Note that as far as I can tell, the other requests for clocks in the Tegra MMC driver result in valid SD clocks. Signed-off-by: Tom Warren Reviewed-by: Jaehoon Chung --- arch/arm/include/asm/arch-tegra/tegra_mmc.h | 2 +- drivers/mmc/tegra_mmc.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index a8bfa466c02..70dcf4aa663 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -130,9 +130,9 @@ struct tegra_mmc { /* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */ #define MEMCOMP_PADCTRL_VREF 7 #define AUTO_CAL_ENABLE (1 << 29) -#if defined(CONFIG_TEGRA210) #define AUTO_CAL_ACTIVE (1 << 31) #define AUTO_CAL_START (1 << 31) +#if defined(CONFIG_TEGRA210) #define AUTO_CAL_PD_OFFSET (0x7D << 8) #define AUTO_CAL_PU_OFFSET (0 << 0) #define IO_TRIM_BYPASS_MASK (1 << 2) diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index 73ac58c6c8d..2b041562a63 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -376,6 +376,25 @@ static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock) rate = clk_set_rate(&priv->clk, clock); div = (rate + clock - 1) / clock; + +#if defined(CONFIG_TEGRA210) + if (priv->mmc_id == PERIPH_ID_SDMMC1 && clock <= 400000) { + /* clock_adjust_periph_pll_div() chooses a 'bad' clock + * on SDMMC1 T210, so skip it here and force a clock + * that's been spec'd in the table in the TRM for + * card-detect (400KHz). + */ + uint effective_rate = clock_adjust_periph_pll_div(priv->mmc_id, + CLOCK_ID_PERIPH, 24727273, NULL); + div = 62; + + debug("%s: WAR: Using SDMMC1 clock of %u, div %d to achieve %dHz card clock ...\n", + __func__, effective_rate, div, clock); + } else { + clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH, + clock, &div); + } +#endif debug("div = %d\n", div); writew(0, &priv->reg->clkcon); -- cgit v1.2.3 From 3c8cf240322e76eebbb31593c96f0754092df91f Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Tue, 12 Nov 2019 13:17:37 -0700 Subject: qspi: t210: Fix claim_bus's use of the wrong bus/device claim_bus() is passed a udevice *dev, which is the bus device's parent. In this driver, claim_bus assumed it was the bus, which caused the 'priv' info pointer to be wrong, and periph_id was incorrect. This in turn caused the periph clock call to assign the wrong clock (PLLM instead of PLLP0), which caused a kernel warning. I only saw the 'bad' periph_id when enabling DEBUG due to an assert. Not sure how QSPI was working w/this errant clock, but it was moot as QSPI wasn't active unless you probed it, and that wasn't happening until I posted a patch to enable env save to QSPI for Nano (coming soon). Signed-off-by: Tom Warren --- drivers/spi/tegra210_qspi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c index d82ecaa61fa..2a77126d04f 100644 --- a/drivers/spi/tegra210_qspi.c +++ b/drivers/spi/tegra210_qspi.c @@ -2,7 +2,8 @@ /* * NVIDIA Tegra210 QSPI controller driver * - * (C) Copyright 2015 NVIDIA Corporation + * (C) Copyright 2015-2019 NVIDIA Corporation + * */ #include @@ -137,8 +138,9 @@ static int tegra210_qspi_probe(struct udevice *bus) return 0; } -static int tegra210_qspi_claim_bus(struct udevice *bus) +static int tegra210_qspi_claim_bus(struct udevice *dev) { + struct udevice *bus = dev->parent; struct tegra210_qspi_priv *priv = dev_get_priv(bus); struct qspi_regs *regs = priv->regs; -- cgit v1.2.3 From 2fcc3ba1b766df5f8cfbf35cb2cc88edff94d0f3 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Mon, 25 Nov 2019 14:43:50 -0700 Subject: qspi: t210: Fix QSPI clock and tap delays When claim_bus was setting the clock, it reset the QSPI controller, which wipes out any tap delays set by previous bootloaders (nvtboot, CBoot for example on Nano). Instead of doing that in claim_bus, which gets called a lot, moved clock setting to probe(), and set tap delays there, too. Also updated clock to 80MHz to match CBoot. Now QSPI env save works reliably again. Signed-off-by: Tom Warren --- drivers/spi/tegra210_qspi.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c index 2a77126d04f..d914337d662 100644 --- a/drivers/spi/tegra210_qspi.c +++ b/drivers/spi/tegra210_qspi.c @@ -42,10 +42,10 @@ DECLARE_GLOBAL_DATA_PTR; #define QSPI_CMD1_BITLEN_SHIFT 0 /* COMMAND2 */ -#define QSPI_CMD2_TX_CLK_TAP_DELAY BIT(6) -#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11,6) -#define QSPI_CMD2_RX_CLK_TAP_DELAY BIT(0) -#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5,0) +#define QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT 10 +#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(14,10) +#define QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT 0 +#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(7,0) /* TRANSFER STATUS */ #define QSPI_XFER_STS_RDY BIT(30) @@ -111,9 +111,9 @@ static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus) /* Use 500KHz as a suitable default */ plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", - 500000); + 500000); plat->deactivate_delay_us = fdtdec_get_int(blob, node, - "spi-deactivate-delay", 0); + "spi-deactivate-delay", 0); debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", __func__, plat->base, plat->periph_id, plat->frequency, plat->deactivate_delay_us); @@ -127,14 +127,23 @@ static int tegra210_qspi_probe(struct udevice *bus) struct tegra210_qspi_priv *priv = dev_get_priv(bus); priv->regs = (struct qspi_regs *)plat->base; + struct qspi_regs *regs = priv->regs; priv->last_transaction_us = timer_get_us(); priv->freq = plat->frequency; priv->periph_id = plat->periph_id; + debug("%s: Freq = %u, id = %d\n", __func__, priv->freq, + priv->periph_id); /* Change SPI clock to correct frequency, PLLP_OUT0 source */ clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); + /* Set tap delays here, clock change above resets QSPI controller */ + u32 reg = (0x09 << QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT) | + (0x0C << QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT); + writel(reg, ®s->command2); + debug("%s: COMMAND2 = %08x\n", __func__, readl(®s->command2)); + return 0; } @@ -144,9 +153,6 @@ static int tegra210_qspi_claim_bus(struct udevice *dev) struct tegra210_qspi_priv *priv = dev_get_priv(bus); struct qspi_regs *regs = priv->regs; - /* Change SPI clock to correct frequency, PLLP_OUT0 source */ - clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); - debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status)); /* Set master mode and sw controlled CS */ -- cgit v1.2.3 From b1747fdb82e9a2befb65b762ba7579b3870d47cb Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Fri, 20 Mar 2020 14:33:00 -0700 Subject: qspi: t210: Use dev_read calls to get FDT data like base, freq This Tegra QSPI driver hadn't been brought up to date with how DM drivers are fetching data from the FDT now, and was pulling in bogus data for base, max freq, etc. Fixed ofdata_to_platdata to work the same way it does in the tegra114 SPI driver, using dev_read_ functions. Signed-off-by: Tom Warren --- drivers/spi/tegra210_qspi.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c index d914337d662..6e540e97df4 100644 --- a/drivers/spi/tegra210_qspi.c +++ b/drivers/spi/tegra210_qspi.c @@ -2,7 +2,7 @@ /* * NVIDIA Tegra210 QSPI controller driver * - * (C) Copyright 2015-2019 NVIDIA Corporation + * (C) Copyright 2015-2020 NVIDIA Corporation * */ @@ -97,10 +97,8 @@ struct tegra210_qspi_priv { static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus) { struct tegra_spi_platdata *plat = bus->platdata; - const void *blob = gd->fdt_blob; - int node = dev_of_offset(bus); - plat->base = devfdt_get_addr(bus); + plat->base = dev_read_addr(bus); plat->periph_id = clock_decode_periph_id(bus); if (plat->periph_id == PERIPH_ID_NONE) { @@ -110,10 +108,11 @@ static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus) } /* Use 500KHz as a suitable default */ - plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", - 500000); - plat->deactivate_delay_us = fdtdec_get_int(blob, node, - "spi-deactivate-delay", 0); + plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", + 500000); + plat->deactivate_delay_us = dev_read_u32_default(bus, + "spi-deactivate-delay", + 0); debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", __func__, plat->base, plat->periph_id, plat->frequency, plat->deactivate_delay_us); -- cgit v1.2.3 From 5dc1dc804d0ffcdb9ddfdf37f8446a9b41f38f78 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Mon, 16 Mar 2020 17:01:43 -0700 Subject: t210: Adjust ramdisk_addr_r/fdt_addr_r to allow for large kernels The L4T kernel is 32MB+, and can overwrite the ramdisk/fdt loaded from extlinux.conf. Adjust the load addresses to fix this for now. Using the calculated_env addresses table from T186 U-Boot is a better fix, but it isn't working correctly on T210 U-Boot right now, so this will do until I can fix it. Signed-off-by: Tom Warren --- include/configs/tegra210-common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index 1c533118ad0..1b8e94b60cc 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -46,8 +46,8 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "fdt_addr_r=0x82000000\0" \ - "ramdisk_addr_r=0x82100000\0" + "fdt_addr_r=0x83000000\0" \ + "ramdisk_addr_r=0x83200000\0" /* For USB EHCI controller */ #define CONFIG_EHCI_IS_TDI -- cgit v1.2.3 From 808e19362f054c8e7cac68e6cd306f7b85d166d3 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Fri, 20 Mar 2020 14:20:09 -0700 Subject: mtd: spi: Add Macronix MX25U3235F device Add Macronix MX25U3235F flash device description. This is a 4MiB part. Signed-off-by: Tom Warren --- drivers/mtd/spi/spi-nor-ids.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 973b6f86c94..abdf560e020 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -147,6 +147,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx25l6405d", 0xc22017, 0, 64 * 1024, 128, SECT_4K) }, { INFO("mx25u2033e", 0xc22532, 0, 64 * 1024, 4, SECT_4K) }, { INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) }, + { INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) }, { INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) }, { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) }, { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) }, -- cgit v1.2.3 From 7c02bc9649f6d3afd272ac4a94b280495473834c Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Fri, 28 Feb 2020 16:17:07 -0700 Subject: ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support The Jetson Nano Developer Kit is a Tegra X1-based development board. It is similar to Jetson TX1 but it is not pin compatible. It features 4GB of LPDDR4, a SPI NOR flash for early boot firmware and an SD card slot used for storage. HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0 and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI Ethernet controller provides onboard network connectivity. NVMe support has also been added. Env save is at the end of QSPI (4MB-8K). A 40-pin header on the board can be used to extend the capabilities and exposed interfaces of the Jetson Nano. Signed-off-by: Thierry Reding Signed-off-by: Tom Warren Tested-by: Peter Robinson --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/tegra210-p3450-0000.dts | 147 +++++++++++++++++++++++++++++ arch/arm/mach-tegra/board2.c | 25 +++++ arch/arm/mach-tegra/tegra210/Kconfig | 7 ++ board/nvidia/p3450-0000/Kconfig | 12 +++ board/nvidia/p3450-0000/MAINTAINERS | 6 ++ board/nvidia/p3450-0000/Makefile | 8 ++ board/nvidia/p3450-0000/p3450-0000.c | 178 +++++++++++++++++++++++++++++++++++ configs/p3450-0000_defconfig | 64 +++++++++++++ include/configs/p3450-0000.h | 46 +++++++++ 10 files changed, 495 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/tegra210-p3450-0000.dts create mode 100644 board/nvidia/p3450-0000/Kconfig create mode 100644 board/nvidia/p3450-0000/MAINTAINERS create mode 100644 board/nvidia/p3450-0000/Makefile create mode 100644 board/nvidia/p3450-0000/p3450-0000.c create mode 100644 configs/p3450-0000_defconfig create mode 100644 include/configs/p3450-0000.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9c593b2c986..820ee9733a0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -180,7 +180,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra210-e2220-1170.dtb \ tegra210-p2371-0000.dtb \ tegra210-p2371-2180.dtb \ - tegra210-p2571.dtb + tegra210-p2571.dtb \ + tegra210-p3450-0000.dtb dtb-$(CONFIG_ARCH_MVEBU) += \ armada-3720-db.dtb \ diff --git a/arch/arm/dts/tegra210-p3450-0000.dts b/arch/arm/dts/tegra210-p3450-0000.dts new file mode 100644 index 00000000000..9ef744ac8b0 --- /dev/null +++ b/arch/arm/dts/tegra210-p3450-0000.dts @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019-2020 NVIDIA Corporation + */ +/dts-v1/; + +#include "tegra210.dtsi" + +/ { + model = "NVIDIA Jetson Nano Developer Kit"; + compatible = "nvidia,p3450-0000", "nvidia,tegra210"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0"; + i2c0 = "/i2c@7000d000"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; + i2c4 = "/i2c@7000c700"; + mmc0 = "/sdhci@700b0600"; + mmc1 = "/sdhci@700b0000"; + spi0 = "/spi@70410000"; + usb0 = "/usb@7d000000"; + }; + + memory { + reg = <0x0 0x80000000 0x0 0xc0000000>; + }; + + pcie@1003000 { + status = "okay"; + + pci@1,0 { + status = "okay"; + }; + + pci@2,0 { + status = "okay"; + + ethernet@0,0 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + }; + + serial@70006000 { + status = "okay"; + }; + + padctl@7009f000 { + pinctrl-0 = <&padctl_default>; + pinctrl-names = "default"; + + padctl_default: pinmux { + xusb { + nvidia,lanes = "otg-1", "otg-2"; + nvidia,function = "xusb"; + nvidia,iddq = <0>; + }; + + usb3 { + nvidia,lanes = "pcie-5", "pcie-6"; + nvidia,function = "usb3"; + nvidia,iddq = <0>; + }; + + pcie-x1 { + nvidia,lanes = "pcie-0"; + nvidia,function = "pcie-x1"; + nvidia,iddq = <0>; + }; + + pcie-x4 { + nvidia,lanes = "pcie-1", "pcie-2", + "pcie-3", "pcie-4"; + nvidia,function = "pcie-x4"; + nvidia,iddq = <0>; + }; + + sata { + nvidia,lanes = "sata-0"; + nvidia,function = "sata"; + nvidia,iddq = <0>; + }; + }; + }; + + sdhci@700b0000 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + sdhci@700b0600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@7000c700 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + }; + + spi@70410000 { + status = "okay"; + spi-max-frequency = <80000000>; + }; + + usb@7d000000 { + status = "okay"; + dr_mode = "peripheral"; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 787ff974203..224efc97c53 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -217,6 +217,31 @@ int board_early_init_f(void) arch_timer_init(); #endif +#if defined(CONFIG_DISABLE_SDMMC1_EARLY) + /* + * Turn off (reset/disable) SDMMC1 on Nano here, before GPIO INIT. + * We do this because earlier bootloaders have enabled power to + * SDMMC1 on Nano, and toggling power-gpio (PZ3) in pinmux_init() + * results in power being back-driven into the SD-card and SDMMC1 + * HW, which is 'bad' as per the HW team. + * + * From the HW team: "LDO2 from the PMIC has already been set to 3.3v in + * nvtboot/CBoot on Nano (for SD-card boot). So when U-Boot's GPIO_INIT + * table sets PZ3 to OUT0 as per the pinmux spreadsheet, it turns off + * the loadswitch. When PZ3 is 0 and not driving, essentially the SDCard + * voltage turns off. Since the SDCard voltage is no longer there, the + * SDMMC CLK/DAT lines are backdriving into what essentially is a + * powered-off SDCard, that's why the voltage drops from 3.3V to ~1.6V" + * + * Note that this can probably be removed when we change over to storing + * all BL components on QSPI on Nano, and U-Boot then becomes the first + * one to turn on SDMMC1 power. Another fix would be to have CBoot + * disable power/gate SDMMC1 off before handing off to U-Boot/kernel. + */ + reset_set_enable(PERIPH_ID_SDMMC1, 1); + clock_set_enable(PERIPH_ID_SDMMC1, 0); +#endif /* CONFIG_DISABLE_SDMMC1_EARLY */ + pinmux_init(); board_init_uart_f(); diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig index 3637473051b..97ed8e05f43 100644 --- a/arch/arm/mach-tegra/tegra210/Kconfig +++ b/arch/arm/mach-tegra/tegra210/Kconfig @@ -35,6 +35,12 @@ config TARGET_P2571 help P2571 is a P2530 married to a P1963 I/O board +config TARGET_P3450_0000 + bool "NVIDIA Jetson Nano Developer Kit" + select BOARD_LATE_INIT + help + P3450-0000 is a P3448 CPU board married to a P3449 I/O board. + endchoice config SYS_SOC @@ -44,5 +50,6 @@ source "board/nvidia/e2220-1170/Kconfig" source "board/nvidia/p2371-0000/Kconfig" source "board/nvidia/p2371-2180/Kconfig" source "board/nvidia/p2571/Kconfig" +source "board/nvidia/p3450-0000/Kconfig" endif diff --git a/board/nvidia/p3450-0000/Kconfig b/board/nvidia/p3450-0000/Kconfig new file mode 100644 index 00000000000..7a08cd88675 --- /dev/null +++ b/board/nvidia/p3450-0000/Kconfig @@ -0,0 +1,12 @@ +if TARGET_P3450_0000 + +config SYS_BOARD + default "p3450-0000" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "p3450-0000" + +endif diff --git a/board/nvidia/p3450-0000/MAINTAINERS b/board/nvidia/p3450-0000/MAINTAINERS new file mode 100644 index 00000000000..40700066bf3 --- /dev/null +++ b/board/nvidia/p3450-0000/MAINTAINERS @@ -0,0 +1,6 @@ +P3450-0000 BOARD +M: Tom Warren +S: Maintained +F: board/nvidia/p3450-0000/ +F: include/configs/p3450-0000.h +F: configs/p3450-0000_defconfig diff --git a/board/nvidia/p3450-0000/Makefile b/board/nvidia/p3450-0000/Makefile new file mode 100644 index 00000000000..993c506d820 --- /dev/null +++ b/board/nvidia/p3450-0000/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2018 +# NVIDIA Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += p3450-0000.o diff --git a/board/nvidia/p3450-0000/p3450-0000.c b/board/nvidia/p3450-0000/p3450-0000.c new file mode 100644 index 00000000000..f4212ab8222 --- /dev/null +++ b/board/nvidia/p3450-0000/p3450-0000.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018-2019 + * NVIDIA Corporation + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "../p2571/max77620_init.h" + +void pin_mux_mmc(void) +{ + struct udevice *dev; + uchar val; + int ret; + + /* Turn on MAX77620 LDO2 to 3.3V for SD card power */ + debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__); + ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); + if (ret) { + printf("%s: Cannot find MAX77620 I2C chip\n", __func__); + return; + } + /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + val = 0xF2; + ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); + + /* Disable LDO4 discharge */ + ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1); + if (ret) { + printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret); + } else { + val &= ~BIT(1); /* ADE */ + ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret); + } + + /* Set MBLPD */ + ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1); + if (ret) { + printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret); + } else { + val |= BIT(6); /* MBLPD */ + ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret); + } +} + +#ifdef CONFIG_PCI_TEGRA +int tegra_pcie_board_init(void) +{ + struct udevice *dev; + uchar val; + int ret; + + /* Turn on MAX77620 LDO1 to 1.05V for PEX power */ + debug("%s: Set LDO1 for PEX power to 1.05V\n", __func__); + ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); + if (ret) { + printf("%s: Cannot find MAX77620 I2C chip\n", __func__); + return -1; + } + /* 0xCA for 1.05v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + val = 0xCA; + ret = dm_i2c_write(dev, MAX77620_CNFG1_L1_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x25 failed: %d\n", ret); + + return 0; +} +#endif /* PCI */ + +static void ft_mac_address_setup(void *fdt) +{ + const void *cboot_fdt = (const void *)cboot_boot_x0; + uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN]; + const char *path; + int offset, err; + + err = cboot_get_ethaddr(cboot_fdt, local_mac); + if (err < 0) + memset(local_mac, 0, ETH_ALEN); + + path = fdt_get_alias(fdt, "ethernet"); + if (!path) + return; + + debug("ethernet alias found: %s\n", path); + + offset = fdt_path_offset(fdt, path); + if (offset < 0) { + printf("ethernet alias points to absent node %s\n", path); + return; + } + + if (is_valid_ethaddr(local_mac)) { + err = fdt_setprop(fdt, offset, "local-mac-address", local_mac, + ETH_ALEN); + if (!err) + debug("Local MAC address set: %pM\n", local_mac); + } + + if (eth_env_get_enetaddr("ethaddr", mac)) { + if (memcmp(local_mac, mac, ETH_ALEN) != 0) { + err = fdt_setprop(fdt, offset, "mac-address", mac, + ETH_ALEN); + if (!err) + debug("MAC address set: %pM\n", mac); + } + } +} + +static int ft_copy_carveout(void *dst, const void *src, const char *node) +{ + struct fdt_memory fb; + int err; + + err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb); + if (err < 0) { + if (err != -FDT_ERR_NOTFOUND) + printf("failed to get carveout for %s: %d\n", node, + err); + + return err; + } + + err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer", + &fb); + if (err < 0) { + printf("failed to set carveout for %s: %d\n", node, err); + return err; + } + + return 0; +} + +static void ft_carveout_setup(void *fdt) +{ + const void *cboot_fdt = (const void *)cboot_boot_x0; + static const char * const nodes[] = { + "/host1x@50000000/dc@54200000", + "/host1x@50000000/dc@54240000", + }; + unsigned int i; + int err; + + for (i = 0; i < ARRAY_SIZE(nodes); i++) { + printf("copying carveout for %s...\n", nodes[i]); + + err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]); + if (err < 0) { + if (err != -FDT_ERR_NOTFOUND) + printf("failed to copy carveout for %s: %d\n", + nodes[i], err); + + continue; + } + } +} + +int ft_board_setup(void *fdt, bd_t *bd) +{ + ft_mac_address_setup(fdt); + ft_carveout_setup(fdt); + + return 0; +} diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig new file mode 100644 index 00000000000..f78e1d38674 --- /dev/null +++ b/configs/p3450-0000_defconfig @@ -0,0 +1,64 @@ +CONFIG_ARM=y +CONFIG_TEGRA=y +CONFIG_SYS_TEXT_BASE=0x80080000 +CONFIG_TEGRA210=y +CONFIG_TARGET_P3450_0000=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_CONSOLE_MUX=y +CONFIG_SYS_STDIO_DEREGISTER=y +CONFIG_SYS_PROMPT="Tegra210 (P3450-0000) # " +# CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_LIVE=y +CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-0000" +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SYS_I2C_TEGRA=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_USE_4K_SECTORS=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_RTL8169=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_TEGRA114_SPI=y +CONFIG_TEGRA210_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" +CONFIG_USB_GADGET_VENDOR_NUM=0x0955 +CONFIG_USB_GADGET_PRODUCT_NUM=0x701a +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_ENV_OFFSET=0xFFFFE000 +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_DISABLE_SDMMC1_EARLY=y diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h new file mode 100644 index 00000000000..7f05bebbcd7 --- /dev/null +++ b/include/configs/p3450-0000.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018-2019 NVIDIA Corporation. + */ + +#ifndef _P3450_0000_H +#define _P3450_0000_H + +#include + +#include "tegra210-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P3450-0000" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA + +/* Only MMC/PXE/DHCP for now, add USB back in later when supported */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +/* Environment at end of QSPI, in the VER partition */ +#define CONFIG_ENV_SPI_MAX_HZ 48000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_0 +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +#define CONFIG_PREBOOT + +#define BOARD_EXTRA_ENV_SETTINGS \ + "preboot=if test -e mmc 1:1 /u-boot-preboot.scr; then " \ + "load mmc 1:1 ${scriptaddr} /u-boot-preboot.scr; " \ + "source ${scriptaddr}; " \ + "fi\0" + +/* General networking support */ +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +/* Crystal is 38.4MHz. clk_m runs at half that rate */ +#define COUNTER_FREQUENCY 19200000 + +#endif /* _P3450_0000_H */ -- cgit v1.2.3 From 9d15d1d1c24f6d3a2bcc7f35c706d8c76c2960b0 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 1 Apr 2020 07:42:04 -0700 Subject: Revert "common: spl_fit: Default to IH_OS_U_BOOT if FIT_IMAGE_TINY enabled" Commit cf8dcc5d02c3 ("common: spl_fit: Default to IH_OS_U_BOOT if FIT_IMAGE_TINY enabled") is not correct, it will append fdt to each loadable image. Actually when using TINY FIT, the first loadable image is thought as u-boot and already have fdt appended. Signed-off-by: Ye Li Tested-by: Fabio Estevam --- common/spl/spl_fit.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index aef1dbdd49a..69dabd27f6d 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -646,10 +646,6 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, if (!spl_fit_image_get_os(fit, node, &os_type)) debug("Loadable is %s\n", genimg_get_os_name(os_type)); -#if CONFIG_IS_ENABLED(FIT_IMAGE_TINY) - else - os_type = IH_OS_U_BOOT; -#endif if (os_type == IH_OS_U_BOOT) { spl_fit_append_fdt(&image_info, info, sector, -- cgit v1.2.3 From 740370282e0caa9fab1c5865fe9b9a58ac008c5f Mon Sep 17 00:00:00 2001 From: Jan-Christoph Tebbe Date: Mon, 16 Mar 2020 17:51:51 +0100 Subject: mach-snapdragon: Fix overwriting last digit of serial number When generating the MAC address based on the boards serial number the last digit was overwritten with the null termination. That way boards with serial numbers close to each other would use the same MAC address. Signed-off-by: Jan-Christoph Tebbe --- arch/arm/mach-snapdragon/misc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-snapdragon/misc.c b/arch/arm/mach-snapdragon/misc.c index f6c87866c0e..aaa561c2c68 100644 --- a/arch/arm/mach-snapdragon/misc.c +++ b/arch/arm/mach-snapdragon/misc.c @@ -41,7 +41,7 @@ void msm_generate_mac_addr(u8 *mac) int i; char sn[9]; - snprintf(sn, 8, "%08x", msm_board_serial()); + snprintf(sn, 9, "%08x", msm_board_serial()); /* fill in the mac with serialno, use locally adminstrated pool */ mac[0] = 0x02; -- cgit v1.2.3 From e14ba8a57703457e31248eccd4959cead92e2063 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 30 Mar 2020 13:58:59 +0200 Subject: arch: Add explicit linker script for u-boot-elf Commit f4dc714aaa2d ("arm64: Turn u-boot.bin back into an ELF file after relocate-rela") introduce REMAKE_ELF option to recreate u-boot.elf from u-boot -> u-boot.bin + DT -> u-boot.elf. The best is to ilustrate it from make V=1 output cat u-boot-nodtb.bin dts/dt.dtb > u-boot-dtb.bin cp u-boot-dtb.bin u-boot.bin aarch64-linux-gnu-objcopy -I binary -B aarch64 -O elf64-littleaarch64 u-boot.bin u-boot-elf.o aarch64-linux-gnu-ld.bfd u-boot-elf.o -o u-boot.elf --defsym="_start"=0x8000000 -Ttext=0x8000000 Last command has no explicit linker script passed that's why toolchain internal linker script is used. In Binutils 2.32 case it contains SIZEOF_HEADERS symbol which has changed behavior by commit https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=64029e93683a266c38d19789e780f3748bd6a188 which result in situation that program headers has changed from (xilinx_zynqmp_mini_defconfig) Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flags Align LOAD 0x0000000000010000 0x00000000fffc0000 0x00000000fffc0000 0x0000000000018918 0x0000000000018918 RW 0x10000 to Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flags Align LOAD 0x0000000000000000 0x00000000fffb0000 0x00000000fffb0000 0x0000000000028918 0x0000000000028918 RW 0x10000 Xilinx tools like XSDB or Bootgen are using program headers for loading ELF to the right location and by above binutils change ELF is loaded to incorrect location. The patch is explicitly use u-boot-elf.lds (just cat now) for u-boot.elf recreation which is called when REMAKE_ELF is setup. By purpose u-boot-elf.lds doesn't contain OUTPUT_FORMAT/OUTPUT_ARCH to be able to use by all archs. Signed-off-by: Michal Simek Reviewed-by: Tom Rini Reviewed-by: Daniel Schwierzeck Tested-By: Álvaro Fernández Rojas --- Kconfig | 5 +++++ Makefile | 11 +++++------ arch/mips/config.mk | 1 - arch/u-boot-elf.lds | 9 +++++++++ 4 files changed, 19 insertions(+), 7 deletions(-) create mode 100644 arch/u-boot-elf.lds diff --git a/Kconfig b/Kconfig index b4864cdf8d3..f698e0a94fe 100644 --- a/Kconfig +++ b/Kconfig @@ -299,6 +299,11 @@ config ERR_PTR_OFFSET pointer values - up to 'MAX_ERRNO' bytes below this value must be unused/invalid addresses. +config PLATFORM_ELFENTRY + string + default "__start" if MIPS + default "_start" + endmenu # General setup menu "Boot images" diff --git a/Makefile b/Makefile index 7fae3c2f643..0db44d42494 100644 --- a/Makefile +++ b/Makefile @@ -1647,18 +1647,17 @@ OBJCOPYFLAGS_u-boot-img-spl-at-end.bin := -I binary -O binary \ u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE $(call if_changed,pad_cat) -# Create a new ELF from a raw binary file. -ifndef PLATFORM_ELFENTRY - PLATFORM_ELFENTRY = "_start" -endif quiet_cmd_u-boot-elf ?= LD $@ cmd_u-boot-elf ?= $(LD) u-boot-elf.o -o $@ \ - --defsym=$(PLATFORM_ELFENTRY)=$(CONFIG_SYS_TEXT_BASE) \ + -T u-boot-elf.lds --defsym=$(CONFIG_PLATFORM_ELFENTRY)=$(CONFIG_SYS_TEXT_BASE) \ -Ttext=$(CONFIG_SYS_TEXT_BASE) -u-boot.elf: u-boot.bin +u-boot.elf: u-boot.bin u-boot-elf.lds $(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o $(call if_changed,u-boot-elf) +u-boot-elf.lds: arch/u-boot-elf.lds prepare FORCE + $(call if_changed_dep,cpp_lds) + # MediaTek's ARM-based u-boot needs a header to contains its load address # which is parsed by the BootROM. # If the SPL build is enabled, the header will be added to the spl binary, diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 9d3a84539a7..527fd6a2fd9 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -36,7 +36,6 @@ CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 endif PLATFORM_CPPFLAGS += -D__MIPS__ -PLATFORM_ELFENTRY = "__start" PLATFORM_ELFFLAGS += -B mips $(OBJCOPYFLAGS) # diff --git a/arch/u-boot-elf.lds b/arch/u-boot-elf.lds new file mode 100644 index 00000000000..1666027e363 --- /dev/null +++ b/arch/u-boot-elf.lds @@ -0,0 +1,9 @@ +ENTRY(CONFIG_PLATFORM_ELFENTRY) +SECTIONS +{ + . = CONFIG_PLATFORM_ELFENTRY; + + .data : { + *(.data*) + } +} -- cgit v1.2.3 From b13da11255a01475d41bdc5d367d55ed3656bae8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 4 Apr 2020 15:01:22 +0200 Subject: net: sh_eth: Init the hardware before PHY access To access the PHY, the MAC registers must be initialized. Call the init function in probe() to make it so, otherwise the PHY ID readout returns all zeroes. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Nobuhiro Iwamatsu --- drivers/net/sh_eth.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 183e8e3083a..f8e5d05722a 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -859,6 +859,10 @@ static int sh_ether_probe(struct udevice *udev) goto err_mdio_register; #endif + ret = sh_eth_init_common(eth, pdata->enetaddr); + if (ret) + goto err_phy_config; + ret = sh_eth_phy_config(udev); if (ret) { printf(SHETHER_NAME ": phy config timeout\n"); -- cgit v1.2.3 From ddcccb2b2c1251ee9cd658c340d722a716d75a96 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 27 Feb 2020 16:00:51 +0200 Subject: x86: acpi: Refactor XSDT handling in acpi_add_table() There is no need to have an assignment to NULL for XSDT pointer. Therefore, no need to assign it when rsdt_address is not set. Because of above changes we may decrease indentation level as well. While here, drop unnecessary parentheses. Signed-off-by: Andy Shevchenko Reviewed-by: Bin Meng --- arch/x86/lib/acpi_table.c | 37 +++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 0d69cf271f4..66e32f21bdb 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -109,14 +109,11 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table) { int i, entries_num; struct acpi_rsdt *rsdt; - struct acpi_xsdt *xsdt = NULL; + struct acpi_xsdt *xsdt; /* The RSDT is mandatory while the XSDT is not */ rsdt = (struct acpi_rsdt *)rsdp->rsdt_address; - if (rsdp->xsdt_address) - xsdt = (struct acpi_xsdt *)((u32)rsdp->xsdt_address); - /* This should always be MAX_ACPI_TABLES */ entries_num = ARRAY_SIZE(rsdt->entry); @@ -135,30 +132,34 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table) /* Fix RSDT length or the kernel will assume invalid entries */ rsdt->header.length = sizeof(struct acpi_table_header) + - (sizeof(u32) * (i + 1)); + sizeof(u32) * (i + 1); /* Re-calculate checksum */ rsdt->header.checksum = 0; rsdt->header.checksum = table_compute_checksum((u8 *)rsdt, rsdt->header.length); + /* The RSDT is mandatory while the XSDT is not */ + if (!rsdp->xsdt_address) + return; + /* * And now the same thing for the XSDT. We use the same index as for * now we want the XSDT and RSDT to always be in sync in U-Boot */ - if (xsdt) { - /* Add table to the XSDT */ - xsdt->entry[i] = (u64)(u32)table; - - /* Fix XSDT length */ - xsdt->header.length = sizeof(struct acpi_table_header) + - (sizeof(u64) * (i + 1)); - - /* Re-calculate checksum */ - xsdt->header.checksum = 0; - xsdt->header.checksum = table_compute_checksum((u8 *)xsdt, - xsdt->header.length); - } + xsdt = (struct acpi_xsdt *)((u32)rsdp->xsdt_address); + + /* Add table to the XSDT */ + xsdt->entry[i] = (u64)(u32)table; + + /* Fix XSDT length */ + xsdt->header.length = sizeof(struct acpi_table_header) + + sizeof(u64) * (i + 1); + + /* Re-calculate checksum */ + xsdt->header.checksum = 0; + xsdt->header.checksum = table_compute_checksum((u8 *)xsdt, + xsdt->header.length); } static void acpi_create_facs(struct acpi_facs *facs) -- cgit v1.2.3 From 63a6098961a2e68ca03093bc45353f2bcc743981 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Thu, 5 Mar 2020 22:56:26 +0200 Subject: doc: board: verdin-imx8mm: use mainline TF-A 1. Update build steps where mainline Trusted Firmware A is used. 2. Fix BL31_BASE to the proper one according to the SoC reference manual. Signed-off-by: Igor Opaniuk Reviewed-by: Bin Meng --- doc/board/toradex/verdin-imx8mm.rst | 26 ++++++-------------------- 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/doc/board/toradex/verdin-imx8mm.rst b/doc/board/toradex/verdin-imx8mm.rst index b2ae4fabea9..b9f7dc39c96 100644 --- a/doc/board/toradex/verdin-imx8mm.rst +++ b/doc/board/toradex/verdin-imx8mm.rst @@ -18,31 +18,22 @@ Get and Build the ARM Trusted Firmware (Trusted Firmware A) .. code-block:: bash $ echo "Downloading and building TF-A..." - $ git clone -b imx_4.14.98_2.3.0 \ - https://source.codeaurora.org/external/imx/imx-atf - $ cd imx-atf - -Please edit ``plat/imx/imx8mm/include/platform_def.h`` so it contains proper -values for UART configuration and BL31 base address (correct values listed -below): - -.. code-block:: bash - - #define BL31_BASE 0x910000 - #define IMX_BOOT_UART_BASE 0x30860000 - #define DEBUG_CONSOLE 1 + $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git + $ cd trusted-firmware-a Then build ATF (TF-A): .. code-block:: bash - $ make PLAT=imx8mm bl31 + $ make PLAT=imx8mm IMX_BOOT_UART_BASE=0x30860000 bl31 + $ cp build/imx8mm/release/bl31.bin ../ Get the DDR Firmware -------------------- .. code-block:: bash + $ cd .. $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.4.1.bin $ chmod +x firmware-imx-8.4.1.bin $ ./firmware-imx-8.4.1.bin @@ -53,6 +44,7 @@ Build U-Boot .. code-block:: bash $ export CROSS_COMPILE=aarch64-linux-gnu- + $ export ATF_LOAD_ADDR=0x920000 $ make verdin-imx8mm_defconfig $ make flash.bin @@ -89,12 +81,6 @@ Output: U-Boot SPL 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100) Normal Boot Trying to boot from MMC1 - NOTICE: Configuring TZASC380 - NOTICE: RDC off - NOTICE: BL31: v2.0(release):rel_imx_4.14.98_2.3.0-0-g09c5cc994-dirty - NOTICE: BL31: Built : 01:11:41, Jan 25 2020 - NOTICE: sip svc init - U-Boot 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100) -- cgit v1.2.3 From d0f7ab531057d666ebebeb8bb1860f52010e7a84 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 20 Mar 2020 19:59:21 +0200 Subject: x86: acpi: Add I²C timings to Intel Merrifield platform There is established way to provide I²C timings, or actually counters, to the OS via ACPI. Fill them for Intel Merrifield platform. Signed-off-by: Andy Shevchenko Reviewed-by: Simon Glass --- .../include/asm/arch-tangier/acpi/southcluster.asl | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl index c622783f44c..6ccdc25136e 100644 --- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl +++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl @@ -240,6 +240,21 @@ Device (PCI0) Return (STA_VISIBLE) } + Name (SSCN, Package () + { + 0x02F8, 0x037B, Zero, + }) + + Name (FMCN, Package () + { + 0x0087, 0x010A, Zero, + }) + + Name (HSCN, Package () + { + 0x0008, 0x0020, Zero, + }) + Name (RBUF, ResourceTemplate() { FixedDMA(0x0009, 0x0000, Width32bit, ) @@ -260,6 +275,21 @@ Device (PCI0) { Return (STA_VISIBLE) } + + Name (SSCN, Package () + { + 0x02F8, 0x037B, Zero, + }) + + Name (FMCN, Package () + { + 0x0087, 0x010A, Zero, + }) + + Name (HSCN, Package () + { + 0x0008, 0x0020, Zero, + }) } Device (GPIO) -- cgit v1.2.3 From 4d073fa83bed62c65aeedb71c4b5584371dc59b7 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 26 Mar 2020 12:33:36 +0200 Subject: x86: acpi: Describe USB 3 host controller found on Intel Tangier USB 3 host controller may be described in ACPI to allow users alter the properties or other features. Describe it for Intel Tangier SoC. Signed-off-by: Andy Shevchenko Reviewed-by: Bin Meng --- .../include/asm/arch-tangier/acpi/southcluster.asl | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl index 6ccdc25136e..f088fe3cf51 100644 --- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl +++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl @@ -321,6 +321,53 @@ Device (PCI0) } } + Device (DWC3) + { + Name (_ADR, 0x00110000) + Name (_DEP, Package () + { + ^IPC1.PMIC + }) + + Method (_STA, 0, NotSerialized) + { + Return (STA_VISIBLE) + } + + Device (RHUB) + { + Name (_ADR, Zero) + + /* GPLD: Generate Port Location Data (PLD) */ + Method (GPLD, 1, Serialized) { + Name (PCKG, Package () { + Buffer (0x14) {} + }) + + /* REV: Revision 0x02 for ACPI 5.0 */ + CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) + Store (0x0002, REV) + + /* VISI: Port visibility to user per port */ + CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) + Store (Arg0, VISI) + + /* VOFF: Vertical offset is not supplied */ + CreateField (DerefOf (Index (PCKG, Zero)), 0x80, 0x10, VOFF) + Store (0xFFFF, VOFF) + + /* HOFF: Horizontal offset is not supplied */ + CreateField (DerefOf (Index (PCKG, Zero)), 0x90, 0x10, HOFF) + Store (0xFFFF, HOFF) + + Return (PCKG) + } + + Device (HS01) { Name (_ADR, 1) } + Device (SS01) { Name (_ADR, 2) } + } + } + Device (PWM0) { Name (_ADR, 0x00170000) -- cgit v1.2.3 From 9e6ce62190b7cd874d2bf727c7681292551ba6b9 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 3 Apr 2020 18:35:32 -0700 Subject: serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko Signed-off-by: Bin Meng Tested-by: Andy Shevchenko Reviewed-by: Wolfgang Wallner Tested-by: Wolfgang Wallner --- drivers/serial/ns16550.c | 39 ++++++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index c1b303ffcba..a2f1b356295 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -479,39 +479,38 @@ static int ns16550_serial_getinfo(struct udevice *dev, return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) -static int ns1655_serial_set_base_addr(struct udevice *dev) +static int ns16550_serial_assign_base(struct ns16550_platdata *plat, ulong base) { - fdt_addr_t addr; - struct ns16550_platdata *plat; - - plat = dev_get_platdata(dev); - - addr = dev_read_addr_pci(dev); - if (addr == FDT_ADDR_T_NONE) + if (base == FDT_ADDR_T_NONE) return -EINVAL; #ifdef CONFIG_SYS_NS16550_PORT_MAPPED - plat->base = addr; + plat->base = base; #else - plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE); + plat->base = (unsigned long)map_physmem(base, 0, MAP_NOCACHE); #endif return 0; } -#endif int ns16550_serial_probe(struct udevice *dev) { + struct ns16550_platdata *plat = dev->platdata; struct NS16550 *const com_port = dev_get_priv(dev); struct reset_ctl_bulk reset_bulk; + fdt_addr_t addr; int ret; -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) - ret = ns1655_serial_set_base_addr(dev); - if (ret) - return ret; -#endif + /* + * If we are on PCI bus, either directly attached to a PCI root port, + * or via a PCI bridge, assign platdata->base before probing hardware. + */ + if (device_is_on_pci_bus(dev)) { + addr = devfdt_get_addr_pci(dev); + ret = ns16550_serial_assign_base(plat, addr); + if (ret) + return ret; + } ret = reset_get_bulk(dev, &reset_bulk); if (!ret) @@ -535,9 +534,15 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) { struct ns16550_platdata *plat = dev->platdata; const u32 port_type = dev_get_driver_data(dev); + fdt_addr_t addr; struct clk clk; int err; + addr = dev_read_addr(dev); + err = ns16550_serial_assign_base(plat, addr); + if (err && !device_is_on_pci_bus(dev)) + return err; + plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0); plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1); -- cgit v1.2.3 From c51430133718d5ac9c0983c0f9dd4714f02c6184 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 11 Feb 2020 12:43:14 +0100 Subject: arm64: zynqmp: Print multiboot register value in EL3 Multi boot register can be used for using different boot images and design better boot strategy. Let EL3 SPL or U-Boot to read it and print it. Signed-off-by: Michal Simek --- arch/arm/mach-zynqmp/include/mach/hardware.h | 4 +++- board/xilinx/zynqmp/zynqmp.c | 14 ++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h index fd361c5ce8a..a0acfa2ff1e 100644 --- a/arch/arm/mach-zynqmp/include/mach/hardware.h +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -128,7 +128,9 @@ struct apu_regs { #define ZYNQMP_SILICON_VER_SHIFT 12 struct csu_regs { - u32 reserved0[17]; + u32 reserved0[4]; + u32 multi_boot; + u32 reserved1[12]; u32 version; }; diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 8bdc67748ec..ba1a126fbf8 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -328,6 +328,17 @@ int board_early_init_f(void) return ret; } +static int multi_boot(void) +{ + u32 multiboot; + + multiboot = readl(&csu_base->multi_boot); + + printf("Multiboot:\t%x\n", multiboot); + + return 0; +} + int board_init(void) { struct udevice *dev; @@ -356,6 +367,9 @@ int board_init(void) } #endif + if (current_el() == 3) + multi_boot(); + return 0; } -- cgit v1.2.3 From 74ce8f47d14397b3319dd3d2b4cc3768d96ad6b3 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Thu, 13 Feb 2020 22:26:56 -0700 Subject: configs: versal: Add CONFIG_DISTRO_DEFAULTS to versal defconfig Add DISTRO_DEFAULTS config to versal virt defconfig file which is suitable for booting general purpose Linux distributions. Remove other configs which are selected by default by DISTRO_DEFAULTS configuration. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek --- configs/xilinx_versal_virt_defconfig | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index ea6244ba1df..df29995edcd 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -4,15 +4,13 @@ CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x100000 CONFIG_DM_GPIO=y CONFIG_COUNTER_FREQUENCY=62500000 -CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOOTDELAY=5 -CONFIG_SUPPORT_RAW_INITRD=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Versal> " CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MEMTEST=y @@ -25,22 +23,11 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_PXE=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ISO_PARTITION=y -CONFIG_EFI_PARTITION=y -# CONFIG_PARTITION_UUIDS is not set CONFIG_OF_BOARD=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y @@ -88,7 +75,6 @@ CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03FD -- cgit v1.2.3 From 19de158db159394207cdf15047cee474400f313f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 17 Feb 2020 12:14:32 +0100 Subject: arm64: zynqmp: Enable cache command for mini mtest configuration Enable cache commands by default for mtest configuration. It is good to be able to enable/disable caches when you test memory. Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_mini_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig index d953c91a66e..2d9a3b3a5f3 100644 --- a/configs/xilinx_zynqmp_mini_defconfig +++ b/configs/xilinx_zynqmp_mini_defconfig @@ -40,6 +40,7 @@ CONFIG_SYS_ALT_MEMTEST=y # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y # CONFIG_CMD_MISC is not set # CONFIG_PARTITIONS is not set CONFIG_OF_EMBED=y -- cgit v1.2.3 From 0b792fd4f1ec191167af91e74001c776bc9c4434 Mon Sep 17 00:00:00 2001 From: Quanyang Wang Date: Mon, 23 Sep 2019 17:47:08 +0800 Subject: ARM: dts: zc702: Fix I2C bus warnings The dtc has new checks for I2C and SPI buses. Fix the warnings in node names and unit-addresses. Warning from Linux kernel: arch/arm/boot/dts/zynq-zc702.dts:187.13-190.6: Warning (i2c_bus_reg): /amba/i2c@e0004000/i2c-mux@74/i2c@7/hwmon@52: I2C bus unit address format error, expected "34" arch/arm/boot/dts/zynq-zc702.dts:191.13-194.6: Warning (i2c_bus_reg): /amba/i2c@e0004000/i2c-mux@74/i2c@7/hwmon@53: I2C bus unit address format error, expected "35" arch/arm/boot/dts/zynq-zc702.dts:195.13-198.6: Warning (i2c_bus_reg): /amba/i2c@e0004000/i2c-mux@74/i2c@7/hwmon@54: I2C bus unit address format error, expected "36" Signed-off-by: Quanyang Wang Signed-off-by: Michal Simek --- arch/arm/dts/zynq-zc702.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index d10695740fa..b043d341d68 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -181,17 +181,17 @@ #address-cells = <1>; #size-cells = <0>; reg = <7>; - hwmon@52 { + hwmon@34 { compatible = "ti,ucd9248"; - reg = <52>; + reg = <0x34>; }; - hwmon@53 { + hwmon@35 { compatible = "ti,ucd9248"; - reg = <53>; + reg = <0x35>; }; - hwmon@54 { + hwmon@36 { compatible = "ti,ucd9248"; - reg = <54>; + reg = <0x36>; }; }; }; -- cgit v1.2.3 From 6bbe3e6c1614b42281ee0a56a0882afe3af3e4f1 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Fri, 21 Dec 2018 18:12:13 +0000 Subject: ARM: dts: zynq: replace gpio-key,wakeup with wakeup-source property Most of the legacy "gpio-key,wakeup" boolean property is already replaced with "wakeup-source". However few occurrences of old property has popped up again, probably from the remnants in downstream trees. Replace the legacy properties with the unified "wakeup-source" property introduced in the Linux kernel commit 700a38b27eef ("Input: gpio_keys - switch to using generic device properties") Cc: Michal Simek Signed-off-by: Sudeep Holla Signed-off-by: Michal Simek --- arch/arm/dts/zynq-zturn.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynq-zturn.dts b/arch/arm/dts/zynq-zturn.dts index cc41efcb463..600e8ee0255 100644 --- a/arch/arm/dts/zynq-zturn.dts +++ b/arch/arm/dts/zynq-zturn.dts @@ -54,7 +54,7 @@ label = "K1"; gpios = <&gpio0 0x32 0x1>; linux,code = <0x66>; - gpio-key,wakeup; + wakeup-source; autorepeat; }; }; -- cgit v1.2.3 From f695e1c8896f5437d0506ded377398be353b21a7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 18 Feb 2020 12:06:14 +0100 Subject: arm64: zynqmp: Replace gpio-key,wakeup with wakeup source The same change has been done for Zynq by commit 1241c72b6db1 ("ARM: dts: zynq: replace gpio-key,wakeup with wakeup-source property") in mainline Linux kernel. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu208-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu216-revA.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 9181060b893..85f9e1f6285 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -50,7 +50,7 @@ label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; - gpio-key,wakeup; + wakeup-source; autorepeat; }; }; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index c294e1b51a2..2db546fddd2 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -50,7 +50,7 @@ label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; - gpio-key,wakeup; + wakeup-source; autorepeat; }; }; -- cgit v1.2.3 From d31f1c9236973a463a73cd2748bcc62939fc9247 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 18 Feb 2020 08:38:06 +0100 Subject: arm64: zynqmp: Update Copyright years to 2020 Trivial change. Signed-off-by: Michal Simek --- arch/arm/dts/avnet-ultra96-rev1.dts | 2 +- arch/arm/dts/zynqmp-clk-ccf.dtsi | 2 +- arch/arm/dts/zynqmp-clk.dtsi | 2 +- arch/arm/dts/zynqmp-mini-qspi.dts | 2 +- arch/arm/dts/zynqmp-zc1232-revA.dts | 2 +- arch/arm/dts/zynqmp-zc1254-revA.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 2 +- arch/arm/dts/zynqmp-zcu100-revC.dts | 2 +- arch/arm/dts/zynqmp-zcu102-rev1.0.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revB.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revC.dts | 2 +- arch/arm/dts/zynqmp-zcu106-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu111-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu1275-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu1275-revB.dts | 2 +- arch/arm/dts/zynqmp-zcu1285-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu208-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu216-revA.dts | 2 +- arch/arm/dts/zynqmp.dtsi | 2 +- 25 files changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm/dts/avnet-ultra96-rev1.dts b/arch/arm/dts/avnet-ultra96-rev1.dts index 88aa06fa78a..ddb8febaece 100644 --- a/arch/arm/dts/avnet-ultra96-rev1.dts +++ b/arch/arm/dts/avnet-ultra96-rev1.dts @@ -2,7 +2,7 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 8eacd22d7cd..1098e890192 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -2,7 +2,7 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi index c9464ec8eb2..82eac56c9d9 100644 --- a/arch/arm/dts/zynqmp-clk.dtsi +++ b/arch/arm/dts/zynqmp-clk.dtsi @@ -2,7 +2,7 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts index e4ba5ae9b68..c523e812366 100644 --- a/arch/arm/dts/zynqmp-mini-qspi.dts +++ b/arch/arm/dts/zynqmp-mini-qspi.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP Mini Configuration * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2020, Xilinx, Inc. * * Siva Durga Prasad * Michal Simek diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts index 6117f83c474..87152afc32f 100644 --- a/arch/arm/dts/zynqmp-zc1232-revA.dts +++ b/arch/arm/dts/zynqmp-zc1232-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts index 6ac8346d23d..d6b2834f3aa 100644 --- a/arch/arm/dts/zynqmp-zc1254-revA.dts +++ b/arch/arm/dts/zynqmp-zc1254-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2020, Xilinx, Inc. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index bb6a94eefb8..d604cf13425 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 1cc8aaa8797..2ff7952e70e 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index 2ead8dd24d5..c7de59e1e98 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index 84c2904dc20..13508c45191 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index 12c0173c559..8d8ebeaac3b 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2020, Xilinx, Inc. * * Siva Durga Prasad * Michal Simek diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 21118c8cc34..1726edf78ed 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016 - 2020, Xilinx, Inc. * * Michal Simek * Nathalie Chan King Choy diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts index 6c702f2674e..f39013794fa 100644 --- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts +++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index b580f9263d0..222b67c7ce2 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index 38ec1881645..2422558b748 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 82557c88d21..6375b47ff85 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index e0e7dac010c..425d7605bf5 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index d31982fce78..dc533f5f6dd 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index bff224f78d1..1304c509ac2 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index c22de576a58..8755bc433b4 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU1275 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017 - 2020, Xilinx, Inc. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index 2ec29b0b5d1..16f609c7e5c 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018 - 2020, Xilinx, Inc. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts index 9c180131388..8a4d5b9fed1 100644 --- a/arch/arm/dts/zynqmp-zcu1285-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU1285 RevA * - * (C) Copyright 2018 - 2019, Xilinx, Inc. + * (C) Copyright 2018 - 2020, Xilinx, Inc. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 85f9e1f6285..7395f23b675 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU208 * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index 2db546fddd2..f08bbe36c2a 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU216 * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 9e7fae83f78..ec0dd73e150 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014 - 2020, Xilinx, Inc. * * Michal Simek * -- cgit v1.2.3 From d4fb2d1145ed1d975da3b18d8588ac3d398fa9e8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Sep 2019 12:53:09 +0200 Subject: ARM: zynq: Fix spi name node None name address should be aligned with address. DTC 1.5.1 is reporting issues related to that. arch/arm/boot/dts/zynq-zc770-xm010.dts:106.10-119.4: Warning (spi_bus_reg): /amba/spi@e0007000/flash@0: SPI bus unit address format error, expected "1" arch/arm/boot/dts/zynq-zc770-xm013.dts:101.19-109.4: Warning (spi_bus_reg): /amba/spi@e0006000/eeprom@0: SPI bus unit address format error, expected "2" Signed-off-by: Michal Simek --- arch/arm/dts/zynq-zc770-xm010.dts | 2 +- arch/arm/dts/zynq-zc770-xm013.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index e1f34653ec3..c547d7921d9 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -72,7 +72,7 @@ status = "okay"; num-cs = <4>; is-decoded-cs = <0>; - flash@0 { + flash@1 { compatible = "sst25wf080", "jedec,spi-nor"; reg = <1>; spi-max-frequency = <1000000>; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index 05a49982cc4..bdf0c2f956d 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -67,7 +67,7 @@ status = "okay"; num-cs = <4>; is-decoded-cs = <0>; - eeprom: eeprom@0 { + eeprom: eeprom@2 { at25,byte-len = <8192>; at25,addr-mode = <2>; at25,page-size = <32>; -- cgit v1.2.3 From 39419c21bf88fbf98a9a08e0ec93db34b9fc5494 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 18 Feb 2020 09:10:18 +0100 Subject: arm64: zynqmp: Remove unused zynqmp-clk.dtsi All boards have been converted to firmware based driver that's why we can remove this file now. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-clk.dtsi | 244 ------------------------------------------- 1 file changed, 244 deletions(-) delete mode 100644 arch/arm/dts/zynqmp-clk.dtsi diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi deleted file mode 100644 index 82eac56c9d9..00000000000 --- a/arch/arm/dts/zynqmp-clk.dtsi +++ /dev/null @@ -1,244 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Clock specification for Xilinx ZynqMP - * - * (C) Copyright 2015 - 2020, Xilinx, Inc. - * - * Michal Simek - */ - -/ { - clk100: clk100 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - u-boot,dm-pre-reloc; - }; - - clk125: clk125 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - clk200: clk200 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - u-boot,dm-pre-reloc; - }; - - clk250: clk250 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - }; - - clk300: clk300 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <300000000>; - u-boot,dm-pre-reloc; - }; - - clk600: clk600 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <600000000>; - }; - - dp_aclk: clock0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-accuracy = <100>; - }; - - dp_aud_clk: clock1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - clock-accuracy = <100>; - }; - - dpdma_clk: dpdma-clk { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <533000000>; - }; - - drm_clock: drm-clock { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <262750000>; - clock-accuracy = <0x64>; - }; -}; - -&can0 { - clocks = <&clk100 &clk100>; -}; - -&can1 { - clocks = <&clk100 &clk100>; -}; - -&fpd_dma_chan1 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan2 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan3 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan4 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan5 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan6 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan7 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan8 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan1 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan2 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan3 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan4 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan5 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan6 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan7 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan8 { - clocks = <&clk600>, <&clk100>; -}; - -&nand0 { - clocks = <&clk100 &clk100>; -}; - -&gem0 { - clocks = <&clk125>, <&clk125>, <&clk125>; -}; - -&gem1 { - clocks = <&clk125>, <&clk125>, <&clk125>; -}; - -&gem2 { - clocks = <&clk125>, <&clk125>, <&clk125>; -}; - -&gem3 { - clocks = <&clk125>, <&clk125>, <&clk125>; -}; - -&gpio { - clocks = <&clk100>; -}; - -&i2c0 { - clocks = <&clk100>; -}; - -&i2c1 { - clocks = <&clk100>; -}; - -&qspi { - clocks = <&clk300 &clk300>; -}; - -&sata { - clocks = <&clk250>; -}; - -&sdhci0 { - clocks = <&clk200 &clk200>; -}; - -&sdhci1 { - clocks = <&clk200 &clk200>; -}; - -&spi0 { - clocks = <&clk200 &clk200>; -}; - -&spi1 { - clocks = <&clk200 &clk200>; -}; - -&uart0 { - clocks = <&clk100 &clk100>; -}; - -&uart1 { - clocks = <&clk100 &clk100>; -}; - -&usb0 { - clocks = <&clk250>, <&clk250>; -}; - -&usb1 { - clocks = <&clk250>, <&clk250>; -}; - -&watchdog0 { - clocks = <&clk100>; -}; - -&lpd_watchdog { - clocks = <&clk250>; -}; - -&xilinx_drm { - clocks = <&drm_clock>; -}; - -&xlnx_dp { - clocks = <&dp_aclk>, <&dp_aud_clk>; -}; - -&xlnx_dpdma { - clocks = <&dpdma_clk>; -}; - -&xlnx_dp_snd_codec0 { - clocks = <&dp_aud_clk>; -}; -- cgit v1.2.3 From 21620990cf7ed6a5e0354db2942a31e69cdf6b6f Mon Sep 17 00:00:00 2001 From: Nava kishore Manne Date: Fri, 18 Oct 2019 18:07:32 +0200 Subject: arm64: zynqmp: Sync zynqmp fpga manager with mainline Sync zynqmp fpga manager with mainline. Signed-off-by: Nava kishore Manne Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-clk-ccf.dtsi | 4 ++++ arch/arm/dts/zynqmp.dtsi | 12 +++++++----- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 1098e890192..0b0fb6e9878 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -291,3 +291,7 @@ &xlnx_dp_snd_codec0 { clocks = <&zynqmp_clk DP_AUDIO_REF>; }; + +&zynqmp_pcap { + clocks = <&zynqmp_clk PCAP>; +}; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index ec0dd73e150..58ac62c4f85 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -149,6 +149,11 @@ #power-domain-cells = <0x1>; u-boot,dm-pre-reloc; + zynqmp_pcap: pcap { + compatible = "xlnx,zynqmp-pcap-fpga"; + clock-names = "ref_clk"; + }; + zynqmp_power: zynqmp-power { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-power"; @@ -180,9 +185,10 @@ fpga_full: fpga-full { compatible = "fpga-region"; - fpga-mgr = <&pcap>; + fpga-mgr = <&zynqmp_pcap>; #address-cells = <2>; #size-cells = <2>; + ranges; }; nvmem_firmware { @@ -195,10 +201,6 @@ }; }; - pcap: pcap { - compatible = "xlnx,zynqmp-pcap-fpga"; - }; - rst: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; -- cgit v1.2.3 From 12ffe75819bb18b433642b21bbb5d1be7c0a1142 Mon Sep 17 00:00:00 2001 From: Manish Narani Date: Thu, 13 Feb 2020 23:37:30 -0700 Subject: arm64: zynqmp: Add 'no-1-8-v' property for ZynqMP Boards Modify dts files to add 'no-1-8-v' property for all the ZynqMP boards. User can remove this property to enable the UHS mode. This is to keep the same speed (HS) modes across all the stages of the Linux Boot. Due to power cycling limitation of some of the ZynqMP boards, some SD cards don't get power cycled and are failing in Linux. Signed-off-by: Manish Narani --- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 5 ++++- arch/arm/dts/zynqmp-zcu102-rev1.0.dts | 4 ---- arch/arm/dts/zynqmp-zcu102-revA.dts | 6 +++++- arch/arm/dts/zynqmp-zcu106-revA.dts | 4 ++++ arch/arm/dts/zynqmp-zcu111-revA.dts | 4 ++++ arch/arm/dts/zynqmp-zcu1285-revA.dts | 4 ++++ arch/arm/dts/zynqmp-zcu208-revA.dts | 4 ++++ arch/arm/dts/zynqmp-zcu216-revA.dts | 4 ++++ 8 files changed, 29 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index d604cf13425..d8ea5578e77 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -154,7 +154,10 @@ /* SD1 with level shifter */ &sdhci1 { status = "okay"; - no-1-8-v; /* for 1.0 silicon */ + /* + * This property should be removed for supporting UHS mode + */ + no-1-8-v; xlnx,mio_bank = <1>; }; diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts index f39013794fa..d508f335994 100644 --- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts +++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts @@ -34,7 +34,3 @@ reg = <0xe0 0x3>; }; }; - -&sdhci1 { - /delete-property/ no-1-8-v; -}; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 222b67c7ce2..e63f4b9cd8b 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -655,7 +655,11 @@ /* SD1 with level shifter */ &sdhci1 { status = "okay"; - no-1-8-v; /* for 1.0 silicon */ + /* + * 1.0 revision has level shifter and this property should be + * removed for supporting UHS mode + */ + no-1-8-v; xlnx,mio_bank = <1>; }; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index dc533f5f6dd..a5c4309f2f3 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -653,6 +653,10 @@ /* SD1 with level shifter */ &sdhci1 { status = "okay"; + /* + * This property should be removed for supporting UHS mode + */ + no-1-8-v; xlnx,mio_bank = <1>; }; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 1304c509ac2..755c30e9ff6 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -567,6 +567,10 @@ &sdhci1 { status = "okay"; disable-wp; + /* + * This property should be removed for supporting UHS mode + */ + no-1-8-v; xlnx,mio_bank = <1>; }; diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts index 8a4d5b9fed1..d8b9cb1a9e1 100644 --- a/arch/arm/dts/zynqmp-zcu1285-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts @@ -241,5 +241,9 @@ &sdhci1 { status = "okay"; + /* + * This property should be removed for supporting UHS mode + */ + no-1-8-v; xlnx,mio_bank = <1>; }; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 7395f23b675..75ecd7a5c20 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -563,6 +563,10 @@ &sdhci1 { status = "okay"; disable-wp; + /* + * This property should be removed for supporting UHS mode + */ + no-1-8-v; xlnx,mio_bank = <1>; }; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index f08bbe36c2a..f3b5edfeb42 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -567,6 +567,10 @@ &sdhci1 { status = "okay"; disable-wp; + /* + * This property should be removed for supporting UHS mode + */ + no-1-8-v; xlnx,mio_bank = <1>; }; -- cgit v1.2.3 From 87b0176fbfb9c6f6fd0cfa575b4f94b9f08c87e6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 18 Feb 2020 09:20:21 +0100 Subject: arm64: zynqmp: Remove second copy of reset-controller Reset controller is handled via firmware that's why it should be the part of firmware node. Origin solution hasn't been removed when above change was applied by commit b07e97b4ba27 ("arm64: zynqmp: Use reset header in zynqmp.dtsi"). Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 58ac62c4f85..ed28f1f695b 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -201,11 +201,6 @@ }; }; - rst: reset-controller { - compatible = "xlnx,zynqmp-reset"; - #reset-cells = <1>; - }; - xlnx_dp_snd_card: dp_snd_card { compatible = "xlnx,dp-snd-card"; status = "disabled"; -- cgit v1.2.3 From d9872d8b47be5218b88e0e435c3ccd0311b44914 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Mon, 17 Feb 2020 23:32:57 -0700 Subject: arm64: dts: zynqmp: Add clk cells for sdhci Add clock-cells and clock-output-names for sdhci0 and sdhci1. These are needed for linux sdhci driver from 5.4 version onwards. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index ed28f1f695b..b117fc43c6d 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -791,6 +791,8 @@ power-domains = <&zynqmp_firmware PD_SD_0>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; + #clock-cells = <1>; + clock-output-names = "clk_out_sd0", "clk_in_sd0"; }; sdhci1: mmc@ff170000 { @@ -807,6 +809,8 @@ power-domains = <&zynqmp_firmware PD_SD_1>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; + #clock-cells = <1>; + clock-output-names = "clk_out_sd1", "clk_in_sd1"; }; pinctrl0: pinctrl@ff180000 { -- cgit v1.2.3 From 0546b1ab06b22fc3cc2c5b23be351ae671a58f82 Mon Sep 17 00:00:00 2001 From: Amit Kumar Mahapatra Date: Mon, 17 Feb 2020 07:50:05 -0700 Subject: arm64: zynqmp: Do not duplicate flash partition label property In kernel 5.4, support has been added for reading MTD devices via the nvmem API. For this the mtd devices are registered as read-only NVMEM providers under sysfs with the same name as the flash partition label property. So if flash partition label property of multiple flash devices are identical then the second mtd device fails to get registered as a NVMEM provider. This patch fixes the issue by having different label property for different flashes. Signed-off-by: Amit Kumar Mahapatra Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 2ff7952e70e..92d938d665d 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -197,7 +197,7 @@ reg = <0>; partition@0 { - label = "data"; + label = "spi0-data"; reg = <0x0 0x100000>; }; }; @@ -214,7 +214,7 @@ reg = <0>; partition@0 { - label = "data"; + label = "spi1-data"; reg = <0x0 0x84000>; }; }; -- cgit v1.2.3 From 04437dea7c908c99edb98de7f485f0175d9bc48d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 18 Feb 2020 09:24:08 +0100 Subject: arm64: zynqmp: Sync DP subsystem Sync DP subsystem with the latest state in Xilinx U-Boot repository. This binding hasn't been approved in mainline Linux but it is much better than ancient version which this patch removes. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-clk-ccf.dtsi | 6 +- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 19 ++--- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revA.dts | 20 ++--- arch/arm/dts/zynqmp.dtsi | 136 +++++++++++++------------------ 5 files changed, 73 insertions(+), 110 deletions(-) diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 0b0fb6e9878..b02ef22abd2 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -284,11 +284,15 @@ clocks = <&zynqmp_clk AMS_REF>; }; +&zynqmp_dpsub { + clocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; +}; + &xlnx_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; }; -&xlnx_dp_snd_codec0 { +&zynqmp_dp_snd_codec0 { clocks = <&zynqmp_clk DP_AUDIO_REF>; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index d8ea5578e77..fa3824d2a12 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -175,32 +175,23 @@ dr_mode = "host"; }; -&xilinx_drm { +&zynqmp_dpsub { status = "okay"; }; -&xlnx_dp { +&zynqmp_dp_snd_pcm0 { status = "okay"; }; -&xlnx_dp_sub { +&zynqmp_dp_snd_pcm1 { status = "okay"; - xlnx,vid-clk-pl; }; -&xlnx_dp_snd_pcm0 { +&zynqmp_dp_snd_card0 { status = "okay"; }; -&xlnx_dp_snd_pcm1 { - status = "okay"; -}; - -&xlnx_dp_snd_card { - status = "okay"; -}; - -&xlnx_dp_snd_codec0 { +&zynqmp_dp_snd_codec0 { status = "okay"; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index 13508c45191..6655b86a802 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -115,7 +115,7 @@ status = "okay"; }; -&xlnx_dp { +&zynqmp_dpsub { status = "okay"; }; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index e63f4b9cd8b..fd6dfdd3c22 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -705,33 +705,23 @@ status = "okay"; }; -&xilinx_drm { +&zynqmp_dpsub { status = "okay"; - clocks = <&si570_1>; }; -&xlnx_dp { +&zynqmp_dp_snd_codec0 { status = "okay"; }; -&xlnx_dp_sub { +&zynqmp_dp_snd_pcm0 { status = "okay"; - xlnx,vid-clk-pl; }; -&xlnx_dp_snd_pcm0 { +&zynqmp_dp_snd_pcm1 { status = "okay"; }; -&xlnx_dp_snd_pcm1 { - status = "okay"; -}; - -&xlnx_dp_snd_card { - status = "okay"; -}; - -&xlnx_dp_snd_codec0 { +&zynqmp_dp_snd_card0 { status = "okay"; }; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index b117fc43c6d..7d84a64b805 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -201,54 +201,6 @@ }; }; - xlnx_dp_snd_card: dp_snd_card { - compatible = "xlnx,dp-snd-card"; - status = "disabled"; - xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; - xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; - }; - - xlnx_dp_snd_codec0: dp_snd_codec0 { - compatible = "xlnx,dp-snd-codec"; - status = "disabled"; - clock-names = "aud_clk"; - }; - - xlnx_dp_snd_pcm0: dp_snd_pcm0 { - compatible = "xlnx,dp-snd-pcm"; - status = "disabled"; - dmas = <&xlnx_dpdma 4>; - dma-names = "tx"; - }; - - xlnx_dp_snd_pcm1: dp_snd_pcm1 { - compatible = "xlnx,dp-snd-pcm"; - status = "disabled"; - dmas = <&xlnx_dpdma 5>; - dma-names = "tx"; - }; - - xilinx_drm: xilinx_drm { - compatible = "xlnx,drm"; - status = "disabled"; - xlnx,encoder-slave = <&xlnx_dp>; - xlnx,connector-type = "DisplayPort"; - xlnx,dp-sub = <&xlnx_dp_sub>; - planes { - xlnx,pixel-format = "rgb565"; - plane0 { - dmas = <&xlnx_dpdma 3>; - dma-names = "dma0"; - }; - plane1 { - dmas = <&xlnx_dpdma 0>, - <&xlnx_dpdma 1>, - <&xlnx_dpdma 2>; - dma-names = "dma0", "dma1", "dma2"; - }; - }; - }; - amba_apu: amba-apu@0 { compatible = "simple-bus"; #address-cells = <2>; @@ -1016,37 +968,6 @@ }; }; - xlnx_dp: dp@fd4a0000 { - compatible = "xlnx,v-dp"; - status = "disabled"; - reg = <0x0 0xfd4a0000 0x0 0x1000>; - interrupts = <0 119 4>; - interrupt-parent = <&gic>; - clock-names = "aclk", "aud_clk"; - xlnx,dp-version = "v1.2"; - xlnx,max-lanes = <2>; - xlnx,max-link-rate = <540000>; - xlnx,max-bpc = <16>; - xlnx,enable-ycrcb; - xlnx,colormetry = "rgb"; - xlnx,bpc = <8>; - xlnx,audio-chan = <2>; - xlnx,dp-sub = <&xlnx_dp_sub>; - xlnx,max-pclock-frequency = <300000>; - }; - - xlnx_dp_sub: dp_sub@fd4aa000 { - compatible = "xlnx,dp-sub"; - status = "disabled"; - reg = <0x0 0xfd4aa000 0x0 0x1000>, - <0x0 0xfd4ab000 0x0 0x1000>, - <0x0 0xfd4ac000 0x0 0x1000>; - reg-names = "blend", "av_buf", "aud"; - xlnx,output-fmt = "rgb"; - xlnx,vid-fmt = "yuyv"; - xlnx,gfx-fmt = "rgb565"; - }; - xlnx_dpdma: dma@fd4c0000 { compatible = "xlnx,dpdma"; status = "disabled"; @@ -1076,5 +997,62 @@ compatible = "xlnx,audio1"; }; }; + + zynqmp_dpsub: zynqmp-display@fd4a0000 { + compatible = "xlnx,zynqmp-dpsub-1.7"; + status = "disabled"; + reg = <0x0 0xfd4a0000 0x0 0x1000>, + <0x0 0xfd4aa000 0x0 0x1000>, + <0x0 0xfd4ab000 0x0 0x1000>, + <0x0 0xfd4ac000 0x0 0x1000>; + reg-names = "dp", "blend", "av_buf", "aud"; + interrupts = <0 119 4>; + interrupt-parent = <&gic>; + + clock-names = "dp_apb_clk", "dp_aud_clk", + "dp_vtc_pixel_clk_in"; + + power-domains = <&zynqmp_firmware PD_DP>; + + vid-layer { + dma-names = "vid0", "vid1", "vid2"; + dmas = <&xlnx_dpdma 0>, + <&xlnx_dpdma 1>, + <&xlnx_dpdma 2>; + }; + + gfx-layer { + dma-names = "gfx0"; + dmas = <&xlnx_dpdma 3>; + }; + + /* dummy node to indicate there's no child i2c device */ + i2c-bus { + }; + + zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 { + compatible = "xlnx,dp-snd-codec"; + clock-names = "aud_clk"; + }; + + zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 { + compatible = "xlnx,dp-snd-pcm"; + dmas = <&xlnx_dpdma 4>; + dma-names = "tx"; + }; + + zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 { + compatible = "xlnx,dp-snd-pcm"; + dmas = <&xlnx_dpdma 5>; + dma-names = "tx"; + }; + + zynqmp_dp_snd_card0: zynqmp_dp_snd_card { + compatible = "xlnx,dp-snd-card"; + xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>, + <&zynqmp_dp_snd_pcm1>; + xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>; + }; + }; }; }; -- cgit v1.2.3 From 5df63a60aa3b509382d11c9115f22b54f86eef05 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 14 Feb 2020 14:19:56 +0100 Subject: arm64: zynqmp: Fix addresses in partition definitions Node name should be @
which is not how partitions are described. Issue was found by running dtbs_check as: flash@0: 'partition@qspi-device-tree', 'partition@qspi-fsbl-uboot', 'partition@qspi-linux', 'partition@qspi-rootfs' do not match any of the regexes: ... Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1232-revA.dts | 8 ++++---- arch/arm/dts/zynqmp-zc1254-revA.dts | 8 ++++---- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 8 ++++---- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 8 ++++---- arch/arm/dts/zynqmp-zcu102-revA.dts | 8 ++++---- arch/arm/dts/zynqmp-zcu104-revA.dts | 8 ++++---- arch/arm/dts/zynqmp-zcu104-revC.dts | 8 ++++---- arch/arm/dts/zynqmp-zcu106-revA.dts | 8 ++++---- arch/arm/dts/zynqmp-zcu111-revA.dts | 8 ++++---- arch/arm/dts/zynqmp-zcu1275-revA.dts | 8 ++++---- arch/arm/dts/zynqmp-zcu1275-revB.dts | 8 ++++---- 11 files changed, 44 insertions(+), 44 deletions(-) diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts index 87152afc32f..afb3e96520b 100644 --- a/arch/arm/dts/zynqmp-zc1232-revA.dts +++ b/arch/arm/dts/zynqmp-zc1232-revA.dts @@ -48,19 +48,19 @@ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@qspi-fsbl-uboot { /* for testing purpose */ + partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; - partition@qspi-linux { /* for testing purpose */ + partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; - partition@qspi-device-tree { /* for testing purpose */ + partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; - partition@qspi-rootfs { /* for testing purpose */ + partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts index d6b2834f3aa..9cc1c0c6c5a 100644 --- a/arch/arm/dts/zynqmp-zc1254-revA.dts +++ b/arch/arm/dts/zynqmp-zc1254-revA.dts @@ -48,19 +48,19 @@ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@qspi-fsbl-uboot { /* for testing purpose */ + partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; - partition@qspi-linux { /* for testing purpose */ + partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; - partition@qspi-device-tree { /* for testing purpose */ + partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; - partition@qspi-rootfs { /* for testing purpose */ + partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index fa3824d2a12..0805b93c4ac 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -108,19 +108,19 @@ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@qspi-fsbl-uboot { /* for testing purpose */ + partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; - partition@qspi-linux { /* for testing purpose */ + partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; - partition@qspi-device-tree { /* for testing purpose */ + partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; - partition@qspi-rootfs { /* for testing purpose */ + partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index 6655b86a802..9b38b8b919e 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -187,19 +187,19 @@ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@qspi-fsbl-uboot { /* for testing purpose */ + partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; - partition@qspi-linux { /* for testing purpose */ + partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; - partition@qspi-device-tree { /* for testing purpose */ + partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; - partition@qspi-rootfs { /* for testing purpose */ + partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index fd6dfdd3c22..d250681600a 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -614,19 +614,19 @@ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@qspi-fsbl-uboot { /* for testing purpose */ + partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; - partition@qspi-linux { /* for testing purpose */ + partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; - partition@qspi-device-tree { /* for testing purpose */ + partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; - partition@qspi-rootfs { /* for testing purpose */ + partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 6375b47ff85..3ceb39dce02 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -209,19 +209,19 @@ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@qspi-fsbl-uboot { /* for testing purpose */ + partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; - partition@qspi-linux { /* for testing purpose */ + partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; - partition@qspi-device-tree { /* for testing purpose */ + partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; - partition@qspi-rootfs { /* for testing purpose */ + partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 425d7605bf5..7dad4523deb 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -222,19 +222,19 @@ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@qspi-fsbl-uboot { /* for testing purpose */ + partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; - partition@qspi-linux { /* for testing purpose */ + partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; - partition@qspi-device-tree { /* for testing purpose */ + partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; - partition@qspi-rootfs { /* for testing purpose */ + partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index a5c4309f2f3..221685fd23b 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -612,19 +612,19 @@ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@qspi-fsbl-uboot { /* for testing purpose */ + partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; - partition@qspi-linux { /* for testing purpose */ + partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; - partition@qspi-device-tree { /* for testing purpose */ + partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; - partition@qspi-rootfs { /* for testing purpose */ + partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 755c30e9ff6..d16bf8ac7ac 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -525,19 +525,19 @@ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@qspi-fsbl-uboot { /* for testing purpose */ + partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; - partition@qspi-linux { /* for testing purpose */ + partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; - partition@qspi-device-tree { /* for testing purpose */ + partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; - partition@qspi-rootfs { /* for testing purpose */ + partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index 8755bc433b4..cdd5c341878 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -49,19 +49,19 @@ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@qspi-fsbl-uboot { /* for testing purpose */ + partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; - partition@qspi-linux { /* for testing purpose */ + partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; - partition@qspi-device-tree { /* for testing purpose */ + partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; - partition@qspi-rootfs { /* for testing purpose */ + partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index 16f609c7e5c..430fc5adb42 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -50,19 +50,19 @@ spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@qspi-fsbl-uboot { /* for testing purpose */ + partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; - partition@qspi-linux { /* for testing purpose */ + partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; - partition@qspi-device-tree { /* for testing purpose */ + partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; - partition@qspi-rootfs { /* for testing purpose */ + partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; -- cgit v1.2.3 From 0ac65007370530491129c134967d4beba76fcd27 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 19 Feb 2020 10:57:34 +0100 Subject: ARM: zynq: Fix addresses in partition definitions Node name should be @
which is not how partitions are described. Signed-off-by: Michal Simek --- arch/arm/dts/zynq-cse-qspi.dtsi | 10 +++++----- arch/arm/dts/zynq-topic-miami.dts | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/dts/zynq-cse-qspi.dtsi b/arch/arm/dts/zynq-cse-qspi.dtsi index 65af4081ff4..eb0e29e6cb6 100644 --- a/arch/arm/dts/zynq-cse-qspi.dtsi +++ b/arch/arm/dts/zynq-cse-qspi.dtsi @@ -67,23 +67,23 @@ spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; - partition@qspi-fsbl-uboot { + partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; - partition@qspi-linux { + partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; - partition@qspi-device-tree { + partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; - partition@qspi-rootfs { + partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; - partition@qspi-bitstream { + partition@c00000 { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; diff --git a/arch/arm/dts/zynq-topic-miami.dts b/arch/arm/dts/zynq-topic-miami.dts index f6f10fe1a15..ab6bde95fed 100644 --- a/arch/arm/dts/zynq-topic-miami.dts +++ b/arch/arm/dts/zynq-topic-miami.dts @@ -44,23 +44,23 @@ spi-max-frequency = <100000000>; #address-cells = <1>; #size-cells = <1>; - partition@qspi-u-boot-spl { + partition@0 { label = "qspi-u-boot-spl"; reg = <0x00000 0x10000>; }; - partition@qspi-u-boot-img { + partition@10000 { label = "qspi-u-boot-img"; reg = <0x10000 0x60000>; }; - partition@qspi-device-tree { + partition@70000 { label = "qspi-device-tree"; reg = <0x70000 0x10000>; }; - partition@qspi-linux { + partition@80000 { label = "qspi-linux"; reg = <0x80000 0x400000>; }; - partition@qspi-rootfs { + partition@480000 { label = "qspi-rootfs"; reg = <0x480000 0x1b80000>; }; -- cgit v1.2.3 From ba1969028753edc9934323e8fe229c248732e4de Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 18 Feb 2020 10:01:26 +0100 Subject: arm64: zynqmp: Fix GIC compatible property dtbs_check is showing warning around GIC compatible property as interrupt-controller@f9010000: compatible: ['arm,gic-400', 'arm,cortex-a15-gic'] is not valid under any of the given schemas Similar change has been done also by Linux kernel commit 5400cdc1410b ("ARM: dts: sunxi: Fix GIC compatible") Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 7d84a64b805..aa281582223 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -208,7 +208,7 @@ ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; + compatible = "arm,gic-400"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, -- cgit v1.2.3 From 00fb945cf56bfe3d8ca7b1c2e38740c4c94a15c7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 18 Feb 2020 13:04:06 +0100 Subject: arm64: zynqmp: Move pinctrl node under firmware node Pinctrl is handled via firmare interface that's why move it there without reg property and new compatible string. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index aa281582223..1634af0bd89 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -167,6 +167,11 @@ compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; + + pinctrl0: pinctrl { + compatible = "xlnx,zynqmp-pinctrl"; + status = "disabled"; + }; }; }; @@ -765,12 +770,6 @@ clock-output-names = "clk_out_sd1", "clk_in_sd1"; }; - pinctrl0: pinctrl@ff180000 { - compatible = "xlnx,pinctrl-zynqmp"; - status = "disabled"; - reg = <0x0 0xff180000 0x0 0x1000>; - }; - smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; -- cgit v1.2.3 From 63e988ed4e39af1d0a40c9cd5efe36e8e9b09206 Mon Sep 17 00:00:00 2001 From: Varalaxmi Bingi Date: Wed, 5 Feb 2020 03:58:20 -0700 Subject: env: Kconfig: Adding default values for Microblaze This patch will add default values for ENV_OFFSET and ENV_SECT_SIZE for Microblaze. Signed-off-by: Varalaxmi Bingi Signed-off-by: Michal Simek --- env/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/env/Kconfig b/env/Kconfig index 0d6f559b39d..2d972a5d4f3 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -500,6 +500,7 @@ config ENV_OFFSET default 0 if ARC default 0x140000 if ARCH_AT91 default 0x260000 if ARCH_OMAP2PLUS + default 0x1080000 if MICROBLAZE && ENV_IS_IN_SPI_FLASH help Offset from the start of the device (or partition) @@ -529,6 +530,7 @@ config ENV_SECT_SIZE default 0x2000 if ARCH_ROCKCHIP default 0x40000 if ARCH_ZYNQMP || ARCH_VERSAL default 0x20000 if ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91 + default 0x20000 if MICROBLAZE && ENV_IS_IN_SPI_FLASH help Size of the sector containing the environment. -- cgit v1.2.3 From f5a122e2abe9a4a589a4ae30145b1fdf4f5207d1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 18 Feb 2020 15:58:33 +0100 Subject: ARM: zynq: Change zc770 xm011 Nand x16 configurations Instead of symlink include origin file and just change model description. Difference is not in DT but in ps7_init configurations which is taken based on device tree name that's why the same DT can't be used. Also update model and update comments to match configurations. Signed-off-by: Michal Simek --- arch/arm/dts/zynq-zc770-xm011-x16.dts | 12 +++++++++++- arch/arm/dts/zynq-zc770-xm011.dts | 2 +- 2 files changed, 12 insertions(+), 2 deletions(-) mode change 120000 => 100644 arch/arm/dts/zynq-zc770-xm011-x16.dts diff --git a/arch/arm/dts/zynq-zc770-xm011-x16.dts b/arch/arm/dts/zynq-zc770-xm011-x16.dts deleted file mode 120000 index 5bd6af39a43..00000000000 --- a/arch/arm/dts/zynq-zc770-xm011-x16.dts +++ /dev/null @@ -1 +0,0 @@ -zynq-zc770-xm011.dts \ No newline at end of file diff --git a/arch/arm/dts/zynq-zc770-xm011-x16.dts b/arch/arm/dts/zynq-zc770-xm011-x16.dts new file mode 100644 index 00000000000..6ff8393d7eb --- /dev/null +++ b/arch/arm/dts/zynq-zc770-xm011-x16.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZC770 XM011 board DTS with NAND x16 + * + * Copyright (C) 2013-2018 Xilinx, Inc. + */ +#include "zynq-zc770-xm011.dts" + +/ { + model = "Xilinx ZC770 XM011 board (NAND x16)"; +}; diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index 61482017d65..b6e3e255d73 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Xilinx ZC770 XM013 board DTS + * Xilinx ZC770 XM011 board DTS * * Copyright (C) 2013-2018 Xilinx, Inc. */ -- cgit v1.2.3 From dacec83ce0f8c80b35ed9b4e18f4468ff8552069 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 18 Feb 2020 15:03:13 +0100 Subject: Makefile: Add environment variable DEVICE_TREE to header Users have option to overwrite default device tree (CONFIG_DEFAULT_DEVICE_TREE) via environment variable DEVICE_TREE. Feature has been added long time ago by commit 74de8c9a1672 ("dts/Makefile: Build the user specified dts") for a little bit different reason. But this variable can be also used for different purpose like choosing proper configuration from FIT image in SPL. And this is the functionality I would like to use on Xilinx Zynq devices that current u-boot.img can be composed in the same way based on OF_LIST and different configuration is taken based on platform specific SPL. SPL requires low level ps7_init_gpl configuration that's why different boards require different SPL with fixed board_fit_config_name_match(). Signed-off-by: Michal Simek Reviewed-by: Tom Rini Reviewed-by: Simon Glass --- Makefile | 14 +++++++++++++- arch/arm/mach-zynq/spl.c | 8 ++++++-- 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index 0db44d42494..c9ae31c80d4 100644 --- a/Makefile +++ b/Makefile @@ -483,6 +483,7 @@ endif version_h := include/generated/version_autogenerated.h timestamp_h := include/generated/timestamp_autogenerated.h defaultenv_h := include/generated/defaultenv_autogenerated.h +dt_h := include/generated/dt.h no-dot-config-targets := clean clobber mrproper distclean \ help %docs check% coccicheck \ @@ -1767,7 +1768,7 @@ endif # prepare2 creates a makefile if using a separate output directory prepare2: prepare3 outputmakefile cfg -prepare1: prepare2 $(version_h) $(timestamp_h) \ +prepare1: prepare2 $(version_h) $(timestamp_h) $(dt_h) \ include/config/auto.conf ifeq ($(wildcard $(LDSCRIPT)),) @echo >&2 " Could not find linker script." @@ -1833,12 +1834,23 @@ define filechk_defaultenv.h xxd -i ; echo ", 0x00" ; ) endef +define filechk_dt.h + (if test -n "$${DEVICE_TREE}"; then \ + echo \#define DEVICE_TREE \"$(DEVICE_TREE)\"; \ + else \ + echo \#define DEVICE_TREE CONFIG_DEFAULT_DEVICE_TREE; \ + fi) +endef + $(version_h): include/config/uboot.release FORCE $(call filechk,version.h) $(timestamp_h): $(srctree)/Makefile FORCE $(call filechk,timestamp.h) +$(dt_h): $(srctree)/Makefile FORCE + $(call filechk,dt.h) + $(defaultenv_h): $(CONFIG_DEFAULT_ENV_FILE:"%"=%) FORCE $(call filechk,defaultenv.h) diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c index 96ba90fb7a7..e89e46c1038 100644 --- a/arch/arm/mach-zynq/spl.c +++ b/arch/arm/mach-zynq/spl.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -89,8 +90,11 @@ void spl_board_prepare_for_boot(void) int board_fit_config_name_match(const char *name) { /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); + debug("%s: Check %s, default %s\n", __func__, name, DEVICE_TREE); - return 0; + if (!strcmp(name, DEVICE_TREE)) + return 0; + + return -1; } #endif -- cgit v1.2.3 From f7c6ee7fe7bcc387de4c92300f46cb725b845b53 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 Feb 2020 15:03:29 +0100 Subject: ARM: zynq: Switch to single zynq configurations There are a lot of zynq configurations which can be merged together and use only one for all. The similar change has been done for ZynqMP by commit be1b6c32d940 ("arm64: zynqmp: Use zynqmp_virt platform") Build SPL with u-boot.img for zc706 like this. export DEVICE_TREE=zynq-zc706 && make xilinx_zynq_virt_defconfig && make -j8 u-boot.img is generic for all boards. Tested on Zybo, zc702, zc706, zc770-xm011-x16, cc108 and microzed. Signed-off-by: Michal Simek --- .azure-pipelines.yml | 6 +-- .gitlab-ci.yml | 6 +-- .travis.yml | 6 +-- configs/xilinx_zynq_virt_defconfig | 19 +++++++- configs/zynq_cc108_defconfig | 61 ------------------------ configs/zynq_dlc20_rev1_0_defconfig | 76 ----------------------------- configs/zynq_microzed_defconfig | 66 -------------------------- configs/zynq_minized_defconfig | 67 -------------------------- configs/zynq_picozed_defconfig | 54 --------------------- configs/zynq_z_turn_defconfig | 67 -------------------------- configs/zynq_zc702_defconfig | 83 -------------------------------- configs/zynq_zc706_defconfig | 87 ---------------------------------- configs/zynq_zc770_xm010_defconfig | 61 ------------------------ configs/zynq_zc770_xm011_defconfig | 48 ------------------- configs/zynq_zc770_xm011_x16_defconfig | 48 ------------------- configs/zynq_zc770_xm012_defconfig | 50 ------------------- configs/zynq_zc770_xm013_defconfig | 53 --------------------- configs/zynq_zed_defconfig | 70 --------------------------- configs/zynq_zybo_defconfig | 69 --------------------------- configs/zynq_zybo_z7_defconfig | 66 -------------------------- doc/board/xilinx/zynq.rst | 3 +- 21 files changed, 29 insertions(+), 1037 deletions(-) delete mode 100644 configs/zynq_cc108_defconfig delete mode 100644 configs/zynq_dlc20_rev1_0_defconfig delete mode 100644 configs/zynq_microzed_defconfig delete mode 100644 configs/zynq_minized_defconfig delete mode 100644 configs/zynq_picozed_defconfig delete mode 100644 configs/zynq_z_turn_defconfig delete mode 100644 configs/zynq_zc702_defconfig delete mode 100644 configs/zynq_zc706_defconfig delete mode 100644 configs/zynq_zc770_xm010_defconfig delete mode 100644 configs/zynq_zc770_xm011_defconfig delete mode 100644 configs/zynq_zc770_xm011_x16_defconfig delete mode 100644 configs/zynq_zc770_xm012_defconfig delete mode 100644 configs/zynq_zc770_xm013_defconfig delete mode 100644 configs/zynq_zed_defconfig delete mode 100644 configs/zynq_zybo_defconfig delete mode 100644 configs/zynq_zybo_z7_defconfig diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index f66d58aa76f..7d2ffe3adec 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -227,11 +227,11 @@ jobs: TEST_PY_BD: "qemu-x86_64" TEST_PY_TEST_SPEC: "not sleep" BUILDMAN: "^qemu-x86_64$" - zynq_zc702: - TEST_PY_BD: "zynq_zc702" + xilinx_zynq_virt: + TEST_PY_BD: "xilinx_zynq_virt" TEST_PY_ID: "--id qemu" TEST_PY_TEST_SPEC: "not sleep" - BUILDMAN: "^zynq_zc702$" + BUILDMAN: "^xilinx_zynq_virt$" xilinx_versal_virt: TEST_PY_BD: "xilinx_versal_virt" TEST_PY_ID: "--id qemu" diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 55943bb3a24..89033587f24 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -320,13 +320,13 @@ qemu-x86_64 test.py: BUILDMAN: "^qemu-x86_64$" <<: *buildman_and_testpy_dfn -zynq_zc702 test.py: +xilinx_zynq_virt test.py: tags: [ 'all' ] variables: - TEST_PY_BD: "zynq_zc702" + TEST_PY_BD: "xilinx_zynq_virt" TEST_PY_TEST_SPEC: "not sleep" TEST_PY_ID: "--id qemu" - BUILDMAN: "^zynq_zc702$" + BUILDMAN: "^xilinx_zynq_virt$" <<: *buildman_and_testpy_dfn xilinx_versal_virt test.py: diff --git a/.travis.yml b/.travis.yml index c59bd7790b6..60cc62e7dac 100644 --- a/.travis.yml +++ b/.travis.yml @@ -504,13 +504,13 @@ matrix: BUILDMAN="^qemu-x86_64$" TOOLCHAIN="i386" BUILD_ROM="yes" - - name: "test/py zynq_zc702" + - name: "test/py xilinx_zynq_virt" env: - - TEST_PY_BD="zynq_zc702" + - TEST_PY_BD="xilinx_zynq_virt" TEST_PY_TEST_SPEC="not sleep" QEMU_TARGET="arm-softmmu" TEST_PY_ID="--id qemu" - BUILDMAN="^zynq_zc702$" + BUILDMAN="^xilinx_zynq_virt$" - name: "test/py xilinx_versal_virt" env: - TEST_PY_BD="xilinx_versal_virt" diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index ece619f239b..2e9f3a0f750 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -11,13 +11,17 @@ CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_PRINT=y +CONFIG_SPL_LOAD_FIT=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_FPGA_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 # CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_IMLS=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y @@ -28,12 +32,14 @@ CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_NAND_LOCK_UNLOCK=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_OF_BOARD=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706" +CONFIG_OF_LIST="zynq-zc702 zynq-zc706 zynq-zc770-xm010 zynq-zc770-xm011 zynq-zc770-xm011-x16 zynq-zc770-xm012 zynq-zc770-xm013 zynq-cc108 zynq-microzed zynq-minized zynq-picozed zynq-zed zynq-zturn zynq-zybo zynq-zybo-z7 zynq-dlc20-rev1.0" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y @@ -52,11 +58,19 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x0 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_ZYNQ=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_MARVELL=y CONFIG_PHY_REALTEK=y @@ -64,6 +78,7 @@ CONFIG_PHY_XILINX=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y CONFIG_ZYNQ_SERIAL=y +CONFIG_ZYNQ_SPI=y CONFIG_ZYNQ_QSPI=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y @@ -76,3 +91,5 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y +CONFIG_DISPLAY=y +CONFIG_SPL_GZIP=y diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig deleted file mode 100644 index 41771171996..00000000000 --- a/configs/zynq_cc108_defconfig +++ /dev/null @@ -1,61 +0,0 @@ -CONFIG_ARM=y -CONFIG_SPL_SYS_DCACHE_OFF=y -CONFIG_ARCH_ZYNQ=y -CONFIG_SYS_TEXT_BASE=0x4000000 -CONFIG_DM_GPIO=y -CONFIG_SPL_STACK_R_ADDR=0x200000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xe0000000 -CONFIG_DEBUG_UART_CLOCK=50000000 -CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_USE_PREBOOT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -# CONFIG_BOOTM_NETBSD is not set -CONFIG_CMD_DFU=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_DEFAULT_DEVICE_TREE="zynq-cc108" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQPL=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SF_DEFAULT_SPEED=30000000 -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_XILINX=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_ZYNQ_QSPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_FUNCTION_THOR=y diff --git a/configs/zynq_dlc20_rev1_0_defconfig b/configs/zynq_dlc20_rev1_0_defconfig deleted file mode 100644 index d52b4b8396b..00000000000 --- a/configs/zynq_dlc20_rev1_0_defconfig +++ /dev/null @@ -1,76 +0,0 @@ -CONFIG_ARM=y -CONFIG_SPL_SYS_DCACHE_OFF=y -CONFIG_ARCH_ZYNQ=y -CONFIG_SYS_TEXT_BASE=0x4000000 -CONFIG_DM_GPIO=y -CONFIG_SPL_STACK_R_ADDR=0x200000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xe0001000 -CONFIG_DEBUG_UART_CLOCK=50000000 -CONFIG_IDENT_STRING=" Xilinx Zynq DLC20 Rev1.0" -CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_USE_PREBOOT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -# CONFIG_BOOTM_NETBSD is not set -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADFS=y -CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_DEFAULT_DEVICE_TREE="zynq-dlc20-rev1.0" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_DFU_MMC=y -CONFIG_DFU_RAM=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQPL=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SF_DEFAULT_SPEED=30000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHY_REALTEK=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_ZYNQ_QSPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03fd -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_FUNCTION_THOR=y diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig deleted file mode 100644 index d4b484fda5d..00000000000 --- a/configs/zynq_microzed_defconfig +++ /dev/null @@ -1,66 +0,0 @@ -CONFIG_ARM=y -CONFIG_SPL_SYS_DCACHE_OFF=y -CONFIG_ARCH_ZYNQ=y -CONFIG_SYS_TEXT_BASE=0x4000000 -CONFIG_DM_GPIO=y -CONFIG_SPL_STACK_R_ADDR=0x200000 -CONFIG_SPL=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_USE_PREBOOT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -# CONFIG_BOOTM_NETBSD is not set -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADFS=y -CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_DFU_MMC=y -CONFIG_DFU_RAM=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQPL=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SF_DEFAULT_SPEED=30000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_XILINX=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_ZYNQ_QSPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03FD -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_FUNCTION_THOR=y diff --git a/configs/zynq_minized_defconfig b/configs/zynq_minized_defconfig deleted file mode 100644 index 6c936aa07d0..00000000000 --- a/configs/zynq_minized_defconfig +++ /dev/null @@ -1,67 +0,0 @@ -CONFIG_ARM=y -CONFIG_SPL_SYS_DCACHE_OFF=y -CONFIG_ARCH_ZYNQ=y -CONFIG_SYS_TEXT_BASE=0x4000000 -CONFIG_DM_GPIO=y -CONFIG_SPL_STACK_R_ADDR=0x200000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xe0001000 -CONFIG_DEBUG_UART_CLOCK=50000000 -CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_USE_PREBOOT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_OS_BOOT=y -# CONFIG_BOOTM_NETBSD is not set -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADFS=y -CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_DEFAULT_DEVICE_TREE="zynq-minized" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_DFU_MMC=y -CONFIG_DFU_RAM=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQPL=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SF_DEFAULT_SPEED=30000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_XILINX=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_ZYNQ_QSPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03fd -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_FUNCTION_THOR=y diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig deleted file mode 100644 index f9db660c8c3..00000000000 --- a/configs/zynq_picozed_defconfig +++ /dev/null @@ -1,54 +0,0 @@ -CONFIG_ARM=y -CONFIG_SPL_SYS_DCACHE_OFF=y -CONFIG_ARCH_ZYNQ=y -CONFIG_SYS_TEXT_BASE=0x4000000 -CONFIG_DM_GPIO=y -CONFIG_SPL_STACK_R_ADDR=0x200000 -CONFIG_SPL=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" -CONFIG_USE_PREBOOT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_OS_BOOT=y -# CONFIG_BOOTM_NETBSD is not set -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADFS=y -CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_DFU_MMC=y -CONFIG_DFU_RAM=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQPL=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_XILINX=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03fd -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_FUNCTION_THOR=y diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig deleted file mode 100644 index 8a22ecb729a..00000000000 --- a/configs/zynq_z_turn_defconfig +++ /dev/null @@ -1,67 +0,0 @@ -CONFIG_ARM=y -CONFIG_SPL_SYS_DCACHE_OFF=y -CONFIG_ARCH_ZYNQ=y -CONFIG_SYS_TEXT_BASE=0x4000000 -CONFIG_DM_GPIO=y -CONFIG_SPL_STACK_R_ADDR=0x200000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xe0001000 -CONFIG_DEBUG_UART_CLOCK=50000000 -CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_USE_PREBOOT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -# CONFIG_BOOTM_NETBSD is not set -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_DFU=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_DEFAULT_DEVICE_TREE="zynq-zturn" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_DFU_MMC=y -CONFIG_DFU_RAM=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQPL=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SF_DEFAULT_SPEED=30000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_XILINX=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_ZYNQ_QSPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03FD -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_FUNCTION_THOR=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig deleted file mode 100644 index cba34326bd4..00000000000 --- a/configs/zynq_zc702_defconfig +++ /dev/null @@ -1,83 +0,0 @@ -CONFIG_ARM=y -CONFIG_SPL_SYS_DCACHE_OFF=y -CONFIG_ARCH_ZYNQ=y -CONFIG_SYS_TEXT_BASE=0x4000000 -CONFIG_DM_GPIO=y -CONFIG_SPL_STACK_R_ADDR=0x200000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xe0001000 -CONFIG_DEBUG_UART_CLOCK=50000000 -CONFIG_IDENT_STRING=" Xilinx Zynq ZC702" -CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_USE_PREBOOT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -# CONFIG_BOOTM_NETBSD is not set -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADFS=y -CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_DFU_MMC=y -CONFIG_DFU_RAM=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQPL=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SF_DEFAULT_SPEED=30000000 -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_XILINX=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_ZYNQ_QSPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03fd -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_FUNCTION_THOR=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig deleted file mode 100644 index 146ef7d2343..00000000000 --- a/configs/zynq_zc706_defconfig +++ /dev/null @@ -1,87 +0,0 @@ -CONFIG_ARM=y -CONFIG_SPL_SYS_DCACHE_OFF=y -CONFIG_ARCH_ZYNQ=y -CONFIG_SYS_TEXT_BASE=0x4000000 -CONFIG_DM_GPIO=y -CONFIG_SPL_STACK_R_ADDR=0x200000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xe0001000 -CONFIG_DEBUG_UART_CLOCK=50000000 -CONFIG_IDENT_STRING=" Xilinx Zynq ZC706" -CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_FIT_PRINT=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_USE_PREBOOT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_FPGA_SUPPORT=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -# CONFIG_BOOTM_NETBSD is not set -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADFS=y -CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_DFU_MMC=y -CONFIG_DFU_RAM=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQPL=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SF_DEFAULT_SPEED=30000000 -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_XILINX=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_ZYNQ_QSPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03fd -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_FUNCTION_THOR=y -CONFIG_WDT=y -CONFIG_WDT_CDNS=y -CONFIG_SPL_GZIP=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig deleted file mode 100644 index 563985f42a8..00000000000 --- a/configs/zynq_zc770_xm010_defconfig +++ /dev/null @@ -1,61 +0,0 @@ -CONFIG_ARM=y -CONFIG_SPL_SYS_DCACHE_OFF=y -CONFIG_ARCH_ZYNQ=y -CONFIG_SYS_TEXT_BASE=0x4000000 -CONFIG_DM_GPIO=y -CONFIG_SPL_STACK_R_ADDR=0x200000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xe0001000 -CONFIG_DEBUG_UART_CLOCK=50000000 -CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM010" -CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_USE_PREBOOT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -# CONFIG_BOOTM_NETBSD is not set -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADFS=y -CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQPL=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SF_DEFAULT_SPEED=30000000 -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_XILINX=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_ZYNQ_SPI=y -CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig deleted file mode 100644 index d64f3d0c8df..00000000000 --- a/configs/zynq_zc770_xm011_defconfig +++ /dev/null @@ -1,48 +0,0 @@ -CONFIG_ARM=y -CONFIG_SPL_SYS_DCACHE_OFF=y -CONFIG_ARCH_ZYNQ=y -CONFIG_SYS_TEXT_BASE=0x4000000 -CONFIG_DM_GPIO=y -CONFIG_SPL_STACK_R_ADDR=0x200000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xe0001000 -CONFIG_DEBUG_UART_CLOCK=50000000 -CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM011" -# CONFIG_SPL_FS_FAT is not set -CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_USE_PREBOOT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_OS_BOOT=y -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADFS=y -CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_NAND_LOCK_UNLOCK=y -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -CONFIG_CMD_CACHE=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_BLK=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQPL=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_ZYNQ=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y diff --git a/configs/zynq_zc770_xm011_x16_defconfig b/configs/zynq_zc770_xm011_x16_defconfig deleted file mode 100644 index 7720d09c4f1..00000000000 --- a/configs/zynq_zc770_xm011_x16_defconfig +++ /dev/null @@ -1,48 +0,0 @@ -CONFIG_ARM=y -CONFIG_SPL_SYS_DCACHE_OFF=y -CONFIG_ARCH_ZYNQ=y -CONFIG_SYS_TEXT_BASE=0x4000000 -CONFIG_DM_GPIO=y -CONFIG_SPL_STACK_R_ADDR=0x200000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xe0001000 -CONFIG_DEBUG_UART_CLOCK=50000000 -CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM011 x16" -# CONFIG_SPL_FS_FAT is not set -CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_USE_PREBOOT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_OS_BOOT=y -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADFS=y -CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_NAND_LOCK_UNLOCK=y -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -CONFIG_CMD_CACHE=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011-x16" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_BLK=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQPL=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_ZYNQ=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig deleted file mode 100644 index f40a496d541..00000000000 --- a/configs/zynq_zc770_xm012_defconfig +++ /dev/null @@ -1,50 +0,0 @@ -CONFIG_ARM=y -CONFIG_SPL_SYS_DCACHE_OFF=y -CONFIG_ARCH_ZYNQ=y -CONFIG_SYS_TEXT_BASE=0x4000000 -CONFIG_DM_GPIO=y -CONFIG_SPL_STACK_R_ADDR=0x200000 -CONFIG_SPL=y -CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM012" -# CONFIG_SPL_FS_FAT is not set -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_USE_PREBOOT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_OS_BOOT=y -# CONFIG_BOOTM_NETBSD is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADFS=y -CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_GPIO=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_CACHE=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xE20E0000 -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_BLK=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQPL=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_XILINX=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_ZYNQ_SERIAL=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig deleted file mode 100644 index 3b73f4408cf..00000000000 --- a/configs/zynq_zc770_xm013_defconfig +++ /dev/null @@ -1,53 +0,0 @@ -CONFIG_ARM=y -CONFIG_SPL_SYS_DCACHE_OFF=y -CONFIG_ARCH_ZYNQ=y -CONFIG_SYS_TEXT_BASE=0x4000000 -CONFIG_DM_GPIO=y -CONFIG_SPL_STACK_R_ADDR=0x200000 -CONFIG_SPL=y -CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM013" -# CONFIG_SPL_FS_FAT is not set -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_USE_PREBOOT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -# CONFIG_BOOTM_NETBSD is not set -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADFS=y -CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_GPIO=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_CACHE=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_BLK=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQPL=y -# CONFIG_MMC is not set -CONFIG_SF_DEFAULT_SPEED=30000000 -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_XILINX=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig deleted file mode 100644 index 18b39b5e8de..00000000000 --- a/configs/zynq_zed_defconfig +++ /dev/null @@ -1,70 +0,0 @@ -CONFIG_ARM=y -CONFIG_SPL_SYS_DCACHE_OFF=y -CONFIG_ARCH_ZYNQ=y -CONFIG_SYS_TEXT_BASE=0x4000000 -CONFIG_DM_GPIO=y -CONFIG_SPL_STACK_R_ADDR=0x200000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xe0001000 -CONFIG_DEBUG_UART_CLOCK=50000000 -CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_USE_PREBOOT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -# CONFIG_BOOTM_NETBSD is not set -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADFS=y -CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_DEFAULT_DEVICE_TREE="zynq-zed" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_DFU_MMC=y -CONFIG_DFU_RAM=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQPL=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SF_DEFAULT_SPEED=30000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_XILINX=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_ZYNQ_QSPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03fd -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_FUNCTION_THOR=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig deleted file mode 100644 index fe1c412b468..00000000000 --- a/configs/zynq_zybo_defconfig +++ /dev/null @@ -1,69 +0,0 @@ -CONFIG_ARM=y -CONFIG_SPL_SYS_DCACHE_OFF=y -CONFIG_ARCH_ZYNQ=y -CONFIG_SYS_TEXT_BASE=0x4000000 -CONFIG_DM_GPIO=y -CONFIG_SPL_STACK_R_ADDR=0x200000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xe0001000 -CONFIG_DEBUG_UART_CLOCK=50000000 -CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_USE_PREBOOT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -# CONFIG_BOOTM_NETBSD is not set -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADFS=y -CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_DFU_MMC=y -CONFIG_DFU_RAM=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQPL=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SF_DEFAULT_SPEED=30000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_XILINX=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_ZYNQ_QSPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03fd -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_FUNCTION_THOR=y -CONFIG_DISPLAY=y diff --git a/configs/zynq_zybo_z7_defconfig b/configs/zynq_zybo_z7_defconfig deleted file mode 100644 index 1dee7570628..00000000000 --- a/configs/zynq_zybo_z7_defconfig +++ /dev/null @@ -1,66 +0,0 @@ -CONFIG_ARM=y -CONFIG_SPL_SYS_DCACHE_OFF=y -CONFIG_ARCH_ZYNQ=y -CONFIG_SYS_TEXT_BASE=0x4000000 -CONFIG_DM_GPIO=y -CONFIG_SPL_STACK_R_ADDR=0x200000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xe0001000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_USE_PREBOOT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -# CONFIG_BOOTM_NETBSD is not set -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADFS=y -CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo-z7" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_DFU_MMC=y -CONFIG_DFU_RAM=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQPL=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SF_DEFAULT_SPEED=30000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_REALTEK=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_ZYNQ_QSPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03fd -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_FUNCTION_THOR=y diff --git a/doc/board/xilinx/zynq.rst b/doc/board/xilinx/zynq.rst index 3f0513ed362..6a09df1d15f 100644 --- a/doc/board/xilinx/zynq.rst +++ b/doc/board/xilinx/zynq.rst @@ -32,7 +32,8 @@ Building configure and build for zc702 board:: - $ make zynq_zc702_config + $ export DEVICE_TREE=zynq-zc702 + $ make xilinx_zynq_virt_defconfig $ make Bootmode -- cgit v1.2.3 From 0f8defd8910ed1a64687f79507c8332b72844aee Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Sun, 23 Feb 2020 08:01:29 -0700 Subject: net: zynq_gem: Add cache flush to zynq_gem_free_pkt Add cache flush to zynq_gem_free_pkt. This is necessary because some net routines would modify this buffer in place. The cache_invalidate in the zynq_gem_recv function would cause the modifications to the buffer to overwrite the DMA from the GEM, if cache coherency is not enabled in the GEM, the next time the buffer is in use. Flushing the cache when the buffer is no longer in use by the net functions ensures that the GEM DMA is going to take place into a clean buffer. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 5f2f87d352c..cfd14665a70 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -578,6 +578,7 @@ static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) struct zynq_gem_priv *priv = dev_get_priv(dev); struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; struct emac_bd *first_bd; + dma_addr_t addr; if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { priv->rx_first_buf = priv->rxbd_current; @@ -592,6 +593,17 @@ static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) first_bd->status = 0xF0000000; } + /* Flush the cache for the packet as well */ +#if defined(CONFIG_PHYS_64BIT) + addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK) + | ((dma_addr_t)current_bd->addr_hi << 32)); +#else + addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; +#endif + flush_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, + ARCH_DMA_MINALIGN)); + barrier(); + if ((++priv->rxbd_current) >= RX_BUF) priv->rxbd_current = 0; -- cgit v1.2.3 From 7c49a6d08e6dbdcb004f9a1129b40b297a2ac2f2 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 26 Feb 2020 11:11:38 +0100 Subject: ARM: zynq: Do not include full zynq-7000.dtsi to cse-nor configuration There is no real need to include full DT when only some nodes are enough to use. It will save some space. Retested with FSBL for initial SoC setup. SPL didn't work. Signed-off-by: Michal Simek --- arch/arm/dts/zynq-cse-nor.dts | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts index 9710abadcf0..4030851eb36 100644 --- a/arch/arm/dts/zynq-cse-nor.dts +++ b/arch/arm/dts/zynq-cse-nor.dts @@ -5,7 +5,6 @@ * Copyright (C) 2018 Xilinx, Inc. */ /dts-v1/; -#include "zynq-7000.dtsi" / { #address-cells = <1>; @@ -33,27 +32,21 @@ }; amba: amba { + u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - interrupt-parent = <&intc>; ranges; - intc: interrupt-controller@f8f01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xF8F01000 0x1000>, - <0xF8F00100 0x100>; - }; - slcr: slcr@f8000000 { + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-bus"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { + u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; clock-output-names = "armpll", "ddrpll", -- cgit v1.2.3 From 36f1f3b640c52c9d28a92675b579c2905cee9c8f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 25 Feb 2020 14:51:48 +0100 Subject: nand: raw: Do not free xnand structure xnand structure is private data structure and it is handled by core and probe shouldn't touch it. Signed-off-by: Michal Simek Reviewed-by: Jagan Teki --- drivers/mtd/nand/raw/zynq_nand.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c index 28db4153f5e..70391496928 100644 --- a/drivers/mtd/nand/raw/zynq_nand.c +++ b/drivers/mtd/nand/raw/zynq_nand.c @@ -1081,18 +1081,18 @@ static int zynq_nand_probe(struct udevice *dev) u8 set_feature[4] = {ONDIE_ECC_FEATURE_ENABLE, 0x00, 0x00, 0x00}; unsigned long ecc_cfg; int ondie_ecc_enabled = 0; - int err = -1; int is_16bit_bw; smc->reg = (struct zynq_nand_smc_regs *)dev_read_addr(dev); of_nand = dev_read_subnode(dev, "flash@e1000000"); if (!ofnode_valid(of_nand)) { printf("Failed to find nand node in dt\n"); - goto fail; + return -ENODEV; } + if (ofnode_read_resource(of_nand, 0, &res)) { printf("Failed to get nand resource\n"); - goto fail; + return -ENODEV; } xnand->nand_base = (void __iomem *)res.start; @@ -1119,7 +1119,7 @@ static int zynq_nand_probe(struct udevice *dev) if (is_16bit_bw == NAND_BW_UNKNOWN) { printf("%s: Unable detect NAND based on MIO settings\n", __func__); - goto fail; + return -EINVAL; } if (is_16bit_bw == NAND_BW_16BIT) @@ -1130,13 +1130,13 @@ static int zynq_nand_probe(struct udevice *dev) /* Initialize the NAND flash interface on NAND controller */ if (zynq_nand_init_nand_flash(mtd, nand_chip->options) < 0) { printf("%s: nand flash init failed\n", __func__); - goto fail; + return -EINVAL; } /* first scan to find the device and get the page size */ if (nand_scan_ident(mtd, 1, NULL)) { printf("%s: nand_scan_ident failed\n", __func__); - goto fail; + return -EINVAL; } /* Send the command for reading device ID */ nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); @@ -1261,14 +1261,12 @@ static int zynq_nand_probe(struct udevice *dev) /* Second phase scan */ if (nand_scan_tail(mtd)) { printf("%s: nand_scan_tail failed\n", __func__); - goto fail; + return -EINVAL; } if (nand_register(0, mtd)) - goto fail; + return -EINVAL; + return 0; -fail: - free(xnand); - return err; } static const struct udevice_id zynq_nand_dt_ids[] = { -- cgit v1.2.3 From 3811746ed9b48c8a538fc6a6edfe91aaf9acb76a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 25 Feb 2020 14:40:42 +0100 Subject: nand: raw: zynq: Do not try to probe driver if nand flash is disabled There is no reason to continue when DT status property indicates that NAND flash is disabled. But that means that NOR flash should be present that's why try it find it out. Signed-off-by: Michal Simek Reviewed-by: Jagan Teki --- drivers/mtd/nand/raw/zynq_nand.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c index 70391496928..0aea83dac0e 100644 --- a/drivers/mtd/nand/raw/zynq_nand.c +++ b/drivers/mtd/nand/raw/zynq_nand.c @@ -1090,6 +1090,11 @@ static int zynq_nand_probe(struct udevice *dev) return -ENODEV; } + if (!ofnode_is_available(of_nand)) { + debug("Nand node in dt disabled\n"); + return dm_scan_fdt_dev(dev); + } + if (ofnode_read_resource(of_nand, 0, &res)) { printf("Failed to get nand resource\n"); return -ENODEV; -- cgit v1.2.3 From 5992f2579739c421cbdc1b6dd0054c636f376ba0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 25 Feb 2020 14:55:58 +0100 Subject: ARM: zynq: Do not report NOR flash detection failure With multi defconfig targeting several board configurations bug report like below is so verbose. Flash: ## Unknown flash on Bank 1 - Size = 0x00000000 = 0 MB 0 Bytes Do not report that message and simply say "Flash: 0 Bytes" because most of Zynq boards are using different type of flashes than NOR. Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index b1cef4d4695..33fac35f6e3 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -51,6 +51,7 @@ # define CONFIG_SYS_FLASH_WRITE_TOUT 5000 # define CONFIG_FLASH_SHOW_PROGRESS 10 # undef CONFIG_SYS_FLASH_EMPTY_INFO +# define CONFIG_SYS_FLASH_QUIET_TEST #endif #ifdef CONFIG_NAND_ZYNQ -- cgit v1.2.3 From f7375aff959d9d04bcbd2ac7443e62c450716b43 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 25 Feb 2020 15:29:40 +0100 Subject: ARM: zynq: Enable DM for CFI NOR flash With multi defconfig NOR flash information about NOR should be taken from DT that's why there is no reason to specify address and sizes via fixed config. Signed-off-by: Michal Simek --- arch/arm/dts/zynq-cse-nor.dts | 14 ++++++++++++++ configs/xilinx_zynq_virt_defconfig | 1 + configs/zynq_cse_nor_defconfig | 3 +++ include/configs/zynq-common.h | 2 -- 4 files changed, 18 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts index 4030851eb36..197fbd717aa 100644 --- a/arch/arm/dts/zynq-cse-nor.dts +++ b/arch/arm/dts/zynq-cse-nor.dts @@ -71,6 +71,20 @@ reg = <0x100 0x100>; }; }; + + /* + * This is partially hack because it is normally subnode of smcc + * but for mini U-Boot there is no reason to enable SMCC driver + * which does almost nothing in NOR flash configuration that's + * why place cfi-flash directly here. + */ + flash@e2000000 { + u-boot,dm-pre-reloc; + compatible = "cfi-flash"; + reg = <0xe2000000 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 2e9f3a0f750..08b43de103a 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -61,6 +61,7 @@ CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig index e2b9454c15c..3b4e2f93fa3 100644 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@ -52,8 +52,11 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y # CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y # CONFIG_EFI_LOADER is not set diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 33fac35f6e3..1eaf65b0a2a 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -43,8 +43,6 @@ /* NOR */ #ifdef CONFIG_MTD_NOR_FLASH -# define CONFIG_SYS_FLASH_BASE 0xE2000000 -# define CONFIG_SYS_FLASH_SIZE (16 * 1024 * 1024) # define CONFIG_SYS_MAX_FLASH_BANKS 1 # define CONFIG_SYS_MAX_FLASH_SECT 512 # define CONFIG_SYS_FLASH_ERASE_TOUT 1000 -- cgit v1.2.3 From 8d78211856fba41bde19831a35322527f09f8887 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 25 Feb 2020 15:50:33 +0100 Subject: env: Make mmc as default option for CONFIG_ENV_FAT_INTERFACE All configs are using mmc as default fat interface. That's why make it default for everybody. The reason for this patch is to make it default for Xilinx Zynq platform which is not listed there. Signed-off-by: Michal Simek --- env/Kconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/env/Kconfig b/env/Kconfig index 2d972a5d4f3..8ab7be11c5b 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -404,8 +404,7 @@ config SYS_REDUNDAND_ENVIRONMENT config ENV_FAT_INTERFACE string "Name of the block device for the environment" depends on ENV_IS_IN_FAT - default "mmc" if ARCH_SUNXI - default "mmc" if TI_COMMON_CMD_OPTIONS || ARCH_ZYNQMP || ARCH_AT91 + default "mmc" help Define this to a string that is the name of the block device. -- cgit v1.2.3 From 36cd899c0cf9b985748aed7a83121b81c232af4f Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Mon, 17 Feb 2020 04:49:40 -0700 Subject: arm64: versal: Enable support for Gigadevice/ISSI flashes Enable support for Gigadevice/ISSI flash parts for Versal platform. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek --- configs/xilinx_versal_virt_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index df29995edcd..1acd871e9ca 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -48,6 +48,9 @@ CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000 CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y -- cgit v1.2.3 From 66ef85da61b719a73754855b9707ecdd27f0bea2 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 4 Mar 2020 08:48:16 +0100 Subject: arm64: zynqmp: Check firmware node when driver is enabled ZynqMP mini configurations works without PMU firmware that's why there is no reason to enable the driver and check if it was probed properly. Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index ba1a126fbf8..c6c55caa1ce 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -341,11 +341,13 @@ static int multi_boot(void) int board_init(void) { +#if defined(CONFIG_ZYNQMP_FIRMWARE) struct udevice *dev; uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev); if (!dev) panic("PMU Firmware device not found - Enable it"); +#endif #if defined(CONFIG_SPL_BUILD) /* Check *at build time* if the filename is an non-empty string */ -- cgit v1.2.3 From 88f0dc32a7c9510999325f206a0f479a226337d7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 5 Mar 2020 11:01:50 +0100 Subject: ARM: zynq: Do not print message about boot device This information is shown already that's why there is no reason to print it again via custom prints. U-Boot SPL 2020.01-03080-ga6214d033bd0 (Mar 05 2020 - 09:59:05 +0100) mmc boot Trying to boot from MMC1 or U-Boot SPL 2020.01-03080-ga6214d033bd0 (Mar 05 2020 - 10:49:46 +0100) qspi boot Trying to boot from SPI Signed-off-by: Michal Simek --- arch/arm/mach-zynq/spl.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c index e89e46c1038..02a7dc98547 100644 --- a/arch/arm/mach-zynq/spl.c +++ b/arch/arm/mach-zynq/spl.c @@ -45,7 +45,6 @@ u32 spl_boot_device(void) switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { #ifdef CONFIG_SPL_SPI_SUPPORT case ZYNQ_BM_QSPI: - puts("qspi boot\n"); mode = BOOT_DEVICE_SPI; break; #endif @@ -57,7 +56,6 @@ u32 spl_boot_device(void) break; #ifdef CONFIG_SPL_MMC_SUPPORT case ZYNQ_BM_SD: - puts("mmc boot\n"); mode = BOOT_DEVICE_MMC1; break; #endif -- cgit v1.2.3 From 25de8a8d0fd41059a884cb6f5b5032e01bdf8be2 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 30 May 2016 10:43:11 +0200 Subject: net: zynq-gem: Setup and use mdio base separately Not all IPs have private MDIO bus and MDIO bus should be shared between several IPs. In past one patch tried to implement it (https://lists.denx.de/pipermail/u-boot/2018-February/319285.html) in pretty raw way but it is not the cleanest solution. This patch is just taking the part of that solution to be able to handle it over releases without conflicts. Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index cfd14665a70..a158824fc9f 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -197,6 +197,7 @@ struct zynq_gem_priv { int phyaddr; int init; struct zynq_gem_regs *iobase; + struct zynq_gem_regs *mdiobase; phy_interface_t interface; struct phy_device *phydev; ofnode phy_of_node; @@ -211,7 +212,7 @@ static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, u32 op, u16 *data) { u32 mgtcr; - struct zynq_gem_regs *regs = priv->iobase; + struct zynq_gem_regs *regs = priv->mdiobase; int err; err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, @@ -297,7 +298,7 @@ static int zynq_phy_init(struct udevice *dev) { int ret; struct zynq_gem_priv *priv = dev_get_priv(dev); - struct zynq_gem_regs *regs = priv->iobase; + struct zynq_gem_regs *regs_mdio = priv->mdiobase; const u32 supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half | @@ -306,7 +307,7 @@ static int zynq_phy_init(struct udevice *dev) SUPPORTED_1000baseT_Full; /* Enable only MDIO bus */ - writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); + writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s_mdio->nwctrl); priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); @@ -335,6 +336,7 @@ static int zynq_gem_init(struct udevice *dev) unsigned long clk_rate = 0; struct zynq_gem_priv *priv = dev_get_priv(dev); struct zynq_gem_regs *regs = priv->iobase; + struct zynq_gem_regs *regs_mdio = priv->mdiobase; struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; @@ -402,7 +404,7 @@ static int zynq_gem_init(struct udevice *dev) writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); /* Setup for Network Control register, MDIO, Rx and Tx enable */ - setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); + setbits_le32(®s_mdio->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); /* Disable the second priority queue */ dummy_tx_bd->addr = 0; @@ -743,6 +745,7 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev) pdata->iobase = (phys_addr_t)dev_read_addr(dev); priv->iobase = (struct zynq_gem_regs *)pdata->iobase; + priv->mdiobase = priv->iobase; /* Hardcode for now */ priv->phyaddr = -1; @@ -768,8 +771,9 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev) priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma"); - printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase, - priv->phyaddr, phy_string_for_interface(priv->interface)); + printf("\nZYNQ GEM: %lx, mdio bus %lx, phyaddr %d, interface %s\n", + (ulong)priv->iobase, (ulong)priv->mdiobase, priv->phyaddr, + phy_string_for_interface(priv->interface)); return 0; } -- cgit v1.2.3 From f7e296d6f5121b2d5e02294ee35fb725e3c28fed Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 9 Mar 2020 08:44:43 +0100 Subject: watchdog: cadence: Remove DECLARE_GLOBAL_DATA_PTR from driver gd is not used in the driver that's why declaration is not needed at all. Signed-off-by: Michal Simek --- drivers/watchdog/cdns_wdt.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/watchdog/cdns_wdt.c b/drivers/watchdog/cdns_wdt.c index 775f06a6e1c..5bf02605a88 100644 --- a/drivers/watchdog/cdns_wdt.c +++ b/drivers/watchdog/cdns_wdt.c @@ -15,8 +15,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - struct cdns_regs { u32 zmr; /* WD Zero mode register, offset - 0x0 */ u32 ccr; /* Counter Control Register offset - 0x4 */ -- cgit v1.2.3 From f1433d0dc929b277551cd6095252b67ebe75307c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 11 Mar 2020 15:00:51 +0100 Subject: arm64: zynqmp: Add third backup bootmode I found this issue when was running py/test.py on zcu102 which is for me by default setup to SD boot mode without any way to change boot mode. Alternative software bootmode selection to JTAG is not working because JTAG mode is 0 which also reset value for it. That's why saying SPL to take u-boot.itb from RAM instead of SD in SD boot mode is not possible via alternative bootmode selection. That's why setup third boot mode to JTAG(BOOT_DEVICE_RAM) as final fallback. Signed-off-by: Michal Simek --- arch/arm/mach-zynqmp/spl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index 896657f51c3..b3830182e25 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -66,6 +66,8 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[1] = BOOT_DEVICE_MMC2; if (spl_boot_list[0] == BOOT_DEVICE_MMC2) spl_boot_list[1] = BOOT_DEVICE_MMC1; + + spl_boot_list[2] = BOOT_DEVICE_RAM; } u32 spl_boot_device(void) -- cgit v1.2.3 From 47cc45a91ccc86c718fef7e8a00188e1047cf3dd Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 12 Mar 2020 09:03:13 +0100 Subject: arm64: zynqmp Add support for zcu102 rev1.1 rev1.1 has different DDR sodimm module that's why it requires different DDR configuration. Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 1 + arch/arm/dts/zynqmp-zcu102-rev1.1.dts | 15 + .../zynqmp/zynqmp-zcu102-rev1.1/psu_init_gpl.c | 1042 ++++++++++++++++++++ configs/xilinx_zynqmp_virt_defconfig | 2 +- 4 files changed, 1059 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/zynqmp-zcu102-rev1.1.dts create mode 100644 board/xilinx/zynqmp/zynqmp-zcu102-rev1.1/psu_init_gpl.c diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 820ee9733a0..ec8fd112f91 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -277,6 +277,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zcu102-revA.dtb \ zynqmp-zcu102-revB.dtb \ zynqmp-zcu102-rev1.0.dtb \ + zynqmp-zcu102-rev1.1.dtb \ zynqmp-zcu104-revA.dtb \ zynqmp-zcu104-revC.dtb \ zynqmp-zcu106-revA.dtb \ diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.1.dts b/arch/arm/dts/zynqmp-zcu102-rev1.1.dts new file mode 100644 index 00000000000..b6798394fcf --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu102-rev1.1.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU102 Rev1.1 + * + * (C) Copyright 2016 - 2020, Xilinx, Inc. + * + * Michal Simek + */ + +#include "zynqmp-zcu102-rev1.0.dts" + +/ { + model = "ZynqMP ZCU102 Rev1.1"; + compatible = "xlnx,zynqmp-zcu102-rev1.1", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; +}; diff --git a/board/xilinx/zynqmp/zynqmp-zcu102-rev1.1/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu102-rev1.1/psu_init_gpl.c new file mode 100644 index 00000000000..1f3f2e66b95 --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-zcu102-rev1.1/psu_init_gpl.c @@ -0,0 +1,1042 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + */ + +#include +#include + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014400U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015B00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010D00U); + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010700U); + psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010700U); + psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02022600U); + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010D00U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01011000U); + psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01011000U); + psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01011000U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01011000U); + psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01011000U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000402U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000702U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000402U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01001002U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000702U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000402U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01011000U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011F02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01001000U); + psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000300U); + psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000300U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01010F03U); + psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010E03U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000300U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000200U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000300U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0080808AU); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020103U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102311U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1107010EU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020192D5U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000909U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000801U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F0FD78U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42021010U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCE401290U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E0U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06220F08U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01132B07U); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_ddr_qos_init_data(void) +{ + psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x00000020U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x00000020U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x52240000U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B03000U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_peripherals_pre_init_data(void) +{ + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U); + + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x000F807EU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U); + psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); + psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000100U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); + psu_mask_write(0xFF000034, 0x000000FFU, 0x0000000CU); + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000003EU); + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF010034, 0x000000FFU, 0x0000000CU); + psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000003EU); + psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x0597F128U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + + mask_delay(1); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U); + + mask_delay(5); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000020U); + psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000020U); + psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U); + mask_delay(1); + psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0000U); + mask_delay(5); + psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000020U); + psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000020U); + psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0000U); + + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU); + psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U); + psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); + psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU); + psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD402864, 0x00000088U, 0x00000008U); + psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U); + psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); + psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U); + psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U); + psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU); + psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U); + psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); + psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); + psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U); + psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U); + psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U); + psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU); + psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU); + psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U); + psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U); + psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U); + psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU); + psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U); + psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U); + psu_mask_write(0xFD410010, 0x00000077U, 0x00000041U); + psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U); + psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U); + psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U); + psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU); + psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U); + psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U); + psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U); + + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U); + psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); + psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U); + psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480020, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x0000FFFFU); + psu_mask_write(0xFD480030, 0x0000FFFFU, 0x000000FFU); + psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480038, 0x0000FFFFU, 0x0000FFFFU); + psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x0000FFF0U); + psu_mask_write(0xFD480040, 0x0000FFFFU, 0x0000FFF0U); + psu_mask_write(0xFD480044, 0x0000FFFFU, 0x0000FFF1U); + psu_mask_write(0xFD480048, 0x0000FFFFU, 0x0000FFF1U); + psu_mask_write(0xFD48006C, 0x00000738U, 0x00000100U); + psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000040U); + psu_mask_write(0xFD4801A4, 0x000007FFU, 0x000000CDU); + psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000624U); + psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000018U); + psu_mask_write(0xFD4801B0, 0x000007FFU, 0x000000B5U); + psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E20U); + psu_mask_write(0xFD480088, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U); + psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000000U); + psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000041U); + psu_mask_write(0xFD480190, 0x00000040U, 0x00000000U); + psu_mask_write(0xFD480194, 0x0000FFE2U, 0x0000FFE2U); + psu_mask_write(0xFD480094, 0x00007E00U, 0x00004A00U); + psu_mask_write(0xFD480174, 0x0000FFFFU, 0x00009000U); + psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED021U); + psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U); + psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00000400U); + psu_mask_write(0xFD480064, 0x000001FFU, 0x00000006U); + psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U); + psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U); + psu_mask_write(0xFD48013C, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD4800AC, 0x00000100U, 0x00000000U); + psu_mask_write(0xFD4800C0, 0x000007FFU, 0x00000000U); + psu_mask_write(0xFD4800B8, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD4800BC, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD4800B0, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD4800B4, 0x0000FFF8U, 0x00000000U); + psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD48008C, 0x0000B000U, 0x00008000U); + psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U); + psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U); + mask_poll(0xFD4023E4, 0x00000010U); + mask_poll(0xFD4063E4, 0x00000010U); + mask_poll(0xFD40A3E4, 0x00000010U); + mask_poll(0xFD40E3E4, 0x00000010U); + psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U); + psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U); + psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U); + psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U); + + return 1; +} + +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U); + psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U); + + return 1; +} + +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + psu_mask_write(0xFD615000, 0x00000F00U, 0x00000A00U); + + return 1; +} + +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); + + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) + >> 16; + pll_retry--; + } + Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); + if (!pll_locked) + return 0; + + Xil_Out32(0xFD080004U, 0x00040063U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); + regval = Xil_In32(0xFD080030); + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0; + + Xil_Out32(0xFD080200U, 0x100091C7U); + int cur_R006_tREFPRD; + + cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U; + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + Xil_Out32(0xFD080004, 0x00060001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80004001) != 0x80004001) + regval = Xil_In32(0xFD080030); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); + + Xil_Out32(0xFD080200U, 0x800091C7U); + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + Xil_Out32(0xFD080004, 0x0000C001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80000C01) != 0x80000C01) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD070180U, 0x01000040U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + + return 1; +} + +static int serdes_enb_coarse_saturation(void) +{ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +static int serdes_fixcal_code(void) +{ + int maskstatus = 1; + unsigned int rdata = 0; + unsigned int match_pmos_code[23]; + unsigned int match_nmos_code[23]; + unsigned int match_ical_code[7]; + unsigned int match_rcal_code[7]; + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; + int i = 0; + int count = 0; + + rdata = Xil_In32(0xFD40289C); + rdata = rdata & ~0x03; + rdata = rdata | 0x1; + Xil_Out32(0xFD40289C, rdata); + + do { + if (count == 1100000) + break; + rdata = Xil_In32(0xFD402B1C); + count++; + } while ((rdata & 0x0000000E) != 0x0000000E); + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + do { + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + maskstatus = mask_poll(0xFD40EF14, 0x2); + if (maskstatus == 0) { + xil_printf("#SERDES initialization timed out\n\r"); + return maskstatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF); + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF); + + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF); + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF); + + if (p_code >= 0x26 && p_code <= 0x3C) + match_pmos_code[p_code - 0x26] += 1; + + if (n_code >= 0x26 && n_code <= 0x3C) + match_nmos_code[n_code - 0x26] += 1; + + if (i_code >= 0xC && i_code <= 0x12) + match_ical_code[i_code - 0xC] += 1; + + if (r_code >= 0x6 && r_code <= 0xC) + match_rcal_code[r_code - 0x6] += 1; + } while (repeat_count++ < 10); + + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0); + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18); + L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) + | 0x20 | 0x4 | ((n_code >> 3) & 0x3); + + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F); + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8); + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30); + L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) + | 0x40 | 0x8 | ((i_code >> 1) & 0x7); + + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F); + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return maskstatus; +} + +static int init_serdes(void) +{ + int status = 1; + + status &= psu_resetin_init_data(); + + status &= serdes_fixcal_code(); + status &= serdes_enb_coarse_saturation(); + + status &= psu_serdes_init_data(); + status &= psu_resetout_init_data(); + + return status; +} + +static void init_peripheral(void) +{ + psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU); +} + +int psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_peripherals_pre_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + + status &= psu_peripherals_init_data(); + status &= init_serdes(); + init_peripheral(); + + status &= psu_afi_config(); + psu_ddr_qos_init_data(); + + if (status == 0) + return 1; + return 0; +} diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 3f845bebad8..752c6822264 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -47,7 +47,7 @@ CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC" -CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA" +CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y -- cgit v1.2.3 From 001ad66324ba2613e04df5cc6ad8285622fd866b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 5 Mar 2020 08:17:49 +0100 Subject: ARM: zynq: Enable i2c mux support for all boards zc702/zc706 have pca9548 i2c muxes that's why enable the driver by default. Signed-off-by: Michal Simek --- configs/xilinx_zynq_virt_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 08b43de103a..76beea1927e 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -50,6 +50,8 @@ CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQPL=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y -- cgit v1.2.3 From d4172c940680c1c8aa370898a8d9e8ec0dceaeaf Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 16 Mar 2020 11:36:17 +0100 Subject: net: eth-uclass: Fix message if mac is coming from DT or ROM When local-mac-address DT property is specified it is reported the same way as address read from eeprom/ROM. Show properly if mac address is coming from DT or ROM. Signed-off-by: Michal Simek --- net/eth-uclass.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/net/eth-uclass.c b/net/eth-uclass.c index ed81cbd5374..8bf2eabe902 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -490,6 +490,7 @@ static int eth_post_probe(struct udevice *dev) struct eth_device_priv *priv = dev->uclass_priv; struct eth_pdata *pdata = dev->platdata; unsigned char env_enetaddr[ARP_HLEN]; + char *source = "DT"; #if defined(CONFIG_NEEDS_MANUAL_RELOC) struct eth_ops *ops = eth_get_ops(dev); @@ -522,6 +523,7 @@ static int eth_post_probe(struct udevice *dev) /* Check if the device has a valid MAC address in device tree */ if (!eth_dev_get_mac_address(dev, pdata->enetaddr) || !is_valid_ethaddr(pdata->enetaddr)) { + source = "ROM"; /* Check if the device has a MAC address in ROM */ if (eth_get_ops(dev)->read_rom_hwaddr) eth_get_ops(dev)->read_rom_hwaddr(dev); @@ -533,9 +535,9 @@ static int eth_post_probe(struct udevice *dev) memcmp(pdata->enetaddr, env_enetaddr, ARP_HLEN)) { printf("\nWarning: %s MAC addresses don't match:\n", dev->name); - printf("Address in ROM is %pM\n", - pdata->enetaddr); - printf("Address in environment is %pM\n", + printf("Address in %s is\t\t%pM\n", + source, pdata->enetaddr); + printf("Address in environment is\t%pM\n", env_enetaddr); } @@ -543,8 +545,8 @@ static int eth_post_probe(struct udevice *dev) memcpy(pdata->enetaddr, env_enetaddr, ARP_HLEN); } else if (is_valid_ethaddr(pdata->enetaddr)) { eth_env_set_enetaddr_by_index("eth", dev->seq, pdata->enetaddr); - printf("\nWarning: %s using MAC address from ROM\n", - dev->name); + printf("\nWarning: %s using MAC address from %s\n", + dev->name, source); } else if (is_zero_ethaddr(pdata->enetaddr) || !is_valid_ethaddr(pdata->enetaddr)) { #ifdef CONFIG_NET_RANDOM_ETHADDR -- cgit v1.2.3 From 387121c173da6998465b80876dae4c1cf38cdce1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 16 Mar 2020 12:40:16 +0100 Subject: arm64: zynqmp Add support for zcu111 revA Add low level configuration for zcu111 for easier SPL run. Signed-off-by: Michal Simek --- .../zynqmp/zynqmp-zcu111-revA/psu_init_gpl.c | 978 +++++++++++++++++++++ 1 file changed, 978 insertions(+) create mode 100644 board/xilinx/zynqmp/zynqmp-zcu111-revA/psu_init_gpl.c diff --git a/board/xilinx/zynqmp/zynqmp-zcu111-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu111-revA/psu_init_gpl.c new file mode 100644 index 00000000000..7c6664dc988 --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-zcu111-revA/psu_init_gpl.c @@ -0,0 +1,978 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + */ + +#include +#include + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E672C6CU); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00012D00U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); + psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U); + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01010F03U); + psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010E03U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x008180BBU); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102412U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002030BU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000909U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E0U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07240F08U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01762B07U); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00330F08U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_ddr_qos_init_data(void) +{ + psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x50040000U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_peripherals_pre_init_data(void) +{ + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U); + + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x00018046U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U); + psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); + psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); + psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + + mask_delay(1); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U); + + mask_delay(5); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U); + psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U); + psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); + psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU); + psu_mask_write(0xFD402860, 0x00000082U, 0x00000002U); + psu_mask_write(0xFD402864, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40286C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); + psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U); + psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U); + psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U); + psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU); + psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U); + psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU); + psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U); + psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); + psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); + psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U); + psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U); + psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U); + psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU); + psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU); + psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U); + psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU); + psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U); + psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U); + psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U); + psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U); + psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U); + psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U); + psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU); + psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U); + psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U); + psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U); + psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U); + + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U); + psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); + psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U); + psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + mask_poll(0xFD4063E4, 0x00000010U); + mask_poll(0xFD40A3E4, 0x00000010U); + mask_poll(0xFD40E3E4, 0x00000010U); + psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U); + psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U); + psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U); + psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U); + + return 1; +} + +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U); + + return 1; +} + +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + psu_mask_write(0xFD615000, 0x00000F00U, 0x00000A00U); + + return 1; +} + +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); + + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) + >> 16; + pll_retry--; + } + Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); + if (!pll_locked) + return 0; + + Xil_Out32(0xFD080004U, 0x00040063U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); + regval = Xil_In32(0xFD080030); + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0; + + Xil_Out32(0xFD080200U, 0x100091C7U); + int cur_R006_tREFPRD; + + cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U; + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + Xil_Out32(0xFD080004, 0x00060001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80004001) != 0x80004001) + regval = Xil_In32(0xFD080030); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); + + Xil_Out32(0xFD080200U, 0x800091C7U); + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + Xil_Out32(0xFD080004, 0x0000C001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80000C01) != 0x80000C01) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD070180U, 0x01000040U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + + return 1; +} + +static int serdes_enb_coarse_saturation(void) +{ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +static int serdes_fixcal_code(void) +{ + int maskstatus = 1; + unsigned int rdata = 0; + unsigned int match_pmos_code[23]; + unsigned int match_nmos_code[23]; + unsigned int match_ical_code[7]; + unsigned int match_rcal_code[7]; + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; + int i = 0; + int count = 0; + + rdata = Xil_In32(0xFD40289C); + rdata = rdata & ~0x03; + rdata = rdata | 0x1; + Xil_Out32(0xFD40289C, rdata); + + do { + if (count == 1100000) + break; + rdata = Xil_In32(0xFD402B1C); + count++; + } while ((rdata & 0x0000000E) != 0x0000000E); + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + do { + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + maskstatus = mask_poll(0xFD40EF14, 0x2); + if (maskstatus == 0) { + xil_printf("#SERDES initialization timed out\n\r"); + return maskstatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF); + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF); + ; + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF); + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF); + ; + + if (p_code >= 0x26 && p_code <= 0x3C) + match_pmos_code[p_code - 0x26] += 1; + + if (n_code >= 0x26 && n_code <= 0x3C) + match_nmos_code[n_code - 0x26] += 1; + + if (i_code >= 0xC && i_code <= 0x12) + match_ical_code[i_code - 0xC] += 1; + + if (r_code >= 0x6 && r_code <= 0xC) + match_rcal_code[r_code - 0x6] += 1; + + } while (repeat_count++ < 10); + + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0); + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18); + L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) + | 0x20 | 0x4 | ((n_code >> 3) & 0x3); + + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F); + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8); + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30); + L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) + | 0x40 | 0x8 | ((i_code >> 1) & 0x7); + + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F); + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return maskstatus; +} + +static int init_serdes(void) +{ + int status = 1; + + status &= psu_resetin_init_data(); + + status &= serdes_fixcal_code(); + status &= serdes_enb_coarse_saturation(); + + status &= psu_serdes_init_data(); + status &= psu_resetout_init_data(); + + return status; +} + +static void init_peripheral(void) +{ + psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU); +} + +int psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_peripherals_pre_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + + status &= psu_peripherals_init_data(); + status &= init_serdes(); + init_peripheral(); + + status &= psu_afi_config(); + psu_ddr_qos_init_data(); + + if (status == 0) + return 1; + return 0; +} -- cgit v1.2.3 From 352f86bf8658ec32d9e64f2d1b9134be6f8555e5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 18 Mar 2020 09:19:02 +0100 Subject: arm64: zynqmp: Enable netconsole for ZynqMP It is nice feature Signed-off-by: Michal Simek --- configs/xilinx_versal_virt_defconfig | 1 + configs/xilinx_zynq_virt_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 1acd871e9ca..e8c34926120 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_BOARD=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_CLK_VERSAL=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 76beea1927e..54cbd3e12b6 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -43,6 +43,7 @@ CONFIG_OF_LIST="zynq-zc702 zynq-zc706 zynq-zc770-xm010 zynq-zc770-xm011 zynq-zc7 CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 752c6822264..7b09edd78e1 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -50,6 +50,7 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC" CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SCSI_AHCI=y -- cgit v1.2.3 From 0486497e2b5f4d36fa968a1a60fea358cbf70b65 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 7 Feb 2020 13:04:10 +0100 Subject: lib: Improve _parse_integer_fixup_radix base 16 detection Base autodetection is failing for this case: if test 257 -gt 3ae; then echo first; else echo second; fi It is because base for 3ae is recognized by _parse_integer_fixup_radix() as 10. The code detects the first char which is not between 'a'/'A' or 'f'/'F' to change base from dec to hex. Signed-off-by: Michal Simek Signed-off-by: Shiril Tichkule --- lib/strto.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/lib/strto.c b/lib/strto.c index 55ff9f7437d..1ac2b09c725 100644 --- a/lib/strto.c +++ b/lib/strto.c @@ -22,9 +22,22 @@ static const char *_parse_integer_fixup_radix(const char *s, unsigned int *base) *base = 16; else *base = 8; - } else + } else { + int i = 0; + char var; + *base = 10; + + do { + var = tolower(s[i++]); + if (var >= 'a' && var <= 'f') { + *base = 16; + break; + } + } while (var); + } } + if (*base == 16 && s[0] == '0' && tolower(s[1]) == 'x') s += 2; return s; -- cgit v1.2.3 From c0adba572108677c23d6aa58173f9869ea3a5819 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 7 Jan 2020 09:02:52 +0100 Subject: arm64: zynqmp: Add support for debug uart also for U-Boot proper board_early_init_f() is the right location where debug uart can be configurated (after MIO initialization). The patch is taking this call from SPL to also make it available for U-Boot proper. Signed-off-by: Michal Simek --- arch/arm/mach-zynqmp/spl.c | 6 ------ board/xilinx/zynqmp/zynqmp.c | 15 ++++++++++++--- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index b3830182e25..c53945e57f3 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -6,7 +6,6 @@ */ #include -#include #include #include @@ -21,11 +20,6 @@ void board_init_f(ulong dummy) board_early_init_f(); board_early_init_r(); -#ifdef CONFIG_DEBUG_UART - /* Uart debug for sure */ - debug_uart_init(); - puts("Debug uart enabled\n"); /* or printch() */ -#endif /* Delay is required for clocks to be propagated */ udelay(1000000); } diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index c6c55caa1ce..04fd3bd0a44 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -319,13 +320,21 @@ static char *zynqmp_get_silicon_idcode_name(void) int board_early_init_f(void) { - int ret = 0; - #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED) + int ret; + ret = psu_init(); + if (ret) + return ret; #endif - return ret; +#ifdef CONFIG_DEBUG_UART + /* Uart debug for sure */ + debug_uart_init(); + puts("Debug uart enabled\n"); /* or printch() */ +#endif + + return 0; } static int multi_boot(void) -- cgit v1.2.3 From f8451f144e3d8fe704bd78416e93a68fd7781123 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 20 Mar 2020 08:59:02 +0100 Subject: arm64: zynqmp: Move timeout for clock propagation below psu_init Delay required for clock propagation is tighly coupled with initialization done in psu_init(). That's why call it also for u-boot proper with CONFIG_ZYNQMP_PSU_INIT_ENABLED enabled. Signed-off-by: Michal Simek --- arch/arm/mach-zynqmp/spl.c | 3 --- board/xilinx/zynqmp/zynqmp.c | 3 +++ 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index c53945e57f3..68df0a79c4e 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -19,9 +19,6 @@ void board_init_f(ulong dummy) { board_early_init_f(); board_early_init_r(); - - /* Delay is required for clocks to be propagated */ - udelay(1000000); } static void ps_mode_reset(ulong mode) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 04fd3bd0a44..eb1bc0861e2 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -326,6 +326,9 @@ int board_early_init_f(void) ret = psu_init(); if (ret) return ret; + + /* Delay is required for clocks to be propagated */ + udelay(1000000); #endif #ifdef CONFIG_DEBUG_UART -- cgit v1.2.3 From 73319eee878c3321a90ae0cc8e0ca8e6ebf0f1fd Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 23 Mar 2020 14:42:34 +0100 Subject: firmware: zynqmp: Enable IPI code calling also in EL3 U-Boot proper can still run in EL3 without using firmware interface wired via ATF. For supporting this use case there is a need to check EL level where U-Boot runs and based on that choose the way how to talk to firmware. Signed-off-by: Michal Simek --- drivers/firmware/firmware-zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 2a2aa2f4f16..c37642569dd 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -51,7 +51,7 @@ static int ipi_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen) static int send_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) return ipi_req(req, req_len, res, res_maxlen); return xilinx_pm_request(req[0], 0, 0, 0, 0, res); -- cgit v1.2.3 From 3d037524756ef2dce6a072975d6a73a5a89d414c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 23 Mar 2020 14:02:01 +0100 Subject: arm64: zynqmp: Reorder parameters for zynqmp_mmio_write() Parameter order is not correct based on zynqmp_mmio_write() declaration. Fixes: be52372ff1bb ("arm64: zynqmp: Use zynqmp_mmio_read/write functions") Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index eb1bc0861e2..3c92b1a5825 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -515,7 +515,7 @@ static int reset_reason(void) env_set("reset_reason", reason); - ret = zynqmp_mmio_write(~0, ~0, (ulong)&crlapb_base->reset_reason); + ret = zynqmp_mmio_write((ulong)&crlapb_base->reset_reason, ~0, ~0); if (ret) return -EINVAL; -- cgit v1.2.3 From b8c3d3f45fb3cfd164ecec2f34ab7fcb5985bcfc Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 23 Mar 2020 14:40:52 +0100 Subject: arm64: zynqmp: Add support for u-boot.itb generation without ATF If ATF doesn't exist generate u-boot.itb without it and let U-Boot run in EL3. Still keep warning to let user know that ATF/BL31 is missing. Signed-off-by: Michal Simek --- arch/arm/mach-zynqmp/mkimage_fit_atf.sh | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh index 1e770ba111d..92e31849f88 100755 --- a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh +++ b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh @@ -29,11 +29,8 @@ else fi if [ ! -f $BL31 ]; then - echo "WARNING: BL31 file $BL31 NOT found, resulting binary is non-functional" >&2 + echo "WARNING: BL31 file $BL31 NOT found, U-Boot will run in EL3" >&2 BL31=/dev/null - # But U-Boot proper could be loaded in EL3 by specifying - # firmware = "uboot"; - # instead of "atf" in config node fi cat << __HEADER_EOF @@ -58,6 +55,10 @@ cat << __HEADER_EOF algo = "md5"; }; }; +__HEADER_EOF + +if [ -f $BL31 ]; then +cat << __ATF atf { description = "ARM Trusted Firmware"; data = /incbin/("$BL31"); @@ -71,7 +72,8 @@ cat << __HEADER_EOF algo = "md5"; }; }; -__HEADER_EOF +__ATF +fi DEFAULT=1 cnt=1 @@ -106,6 +108,15 @@ __CONF_HEADER_EOF cnt=1 for dtname in $DT do +if [ ! -f $BL31 ]; then +cat << __CONF_SECTION1_EOF + config_$cnt { + description = "$(basename $dtname .dtb)"; + firmware = "uboot"; + fdt = "fdt_$cnt"; + }; +__CONF_SECTION1_EOF +else cat << __CONF_SECTION1_EOF config_$cnt { description = "$(basename $dtname .dtb)"; @@ -114,6 +125,8 @@ cat << __CONF_SECTION1_EOF fdt = "fdt_$cnt"; }; __CONF_SECTION1_EOF +fi + cnt=$((cnt+1)) done -- cgit v1.2.3 From 98da86681e5158195314fd5df4ff605d3bb63d75 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 18 Mar 2020 13:45:21 +0100 Subject: arm64: versal: Disable DDR cache mapping if DDR is not enabled Similar change was done in past by commit 3b644a3c2f69 ("arm64: zynqmp: Provide a config to not map DDR region in MMU table"). Signed-off-by: Michal Simek --- arch/arm/mach-versal/Kconfig | 6 ++++++ arch/arm/mach-versal/cpu.c | 9 +++++++++ 2 files changed, 15 insertions(+) diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig index a08e5ae4149..e1d66e8d32b 100644 --- a/arch/arm/mach-versal/Kconfig +++ b/arch/arm/mach-versal/Kconfig @@ -56,4 +56,10 @@ config DEFINE_TCM_OCM_MMAP This option if enabled defines the TCM and OCM memory and its memory attributes in MMU table entry. +config VERSAL_NO_DDR + bool "Disable DDR MMU mapping" + help + This option configures MMU with no DDR to avoid speculative + access to DDR memory where DDR is not present. + endif diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 6ee6cd43eca..829a6c1b3e5 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -81,6 +81,15 @@ void mem_map_fill(void) if (!gd->bd->bi_dram[i].size) break; +#if defined(CONFIG_VERSAL_NO_DDR) + if (gd->bd->bi_dram[i].start < 0x80000000UL || + gd->bd->bi_dram[i].start > 0x100000000UL) { + printf("Ignore caches over %llx/%llx\n", + gd->bd->bi_dram[i].start, + gd->bd->bi_dram[i].size); + continue; + } +#endif versal_mem_map[banks].virt = gd->bd->bi_dram[i].start; versal_mem_map[banks].phys = gd->bd->bi_dram[i].start; versal_mem_map[banks].size = gd->bd->bi_dram[i].size; -- cgit v1.2.3 From 453bb77d09c993a0690a045308aee9813b7dd58b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 19 Mar 2020 10:23:56 +0100 Subject: arm64: xilinx: Never touch DDR if system has no DDR If DDR is not mapped do not touch it. Default XILINX_OF_BOARD_DTB_ADDR is pointing to DDR. Signed-off-by: Michal Simek --- board/xilinx/common/board.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index f87e2e91059..e83c692f217 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -41,12 +41,16 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) #if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE) void *board_fdt_blob_setup(void) { - static void *fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR; + static void *fdt_blob; + +#if !defined(CONFIG_VERSAL_NO_DDR) && !defined(CONFIG_ZYNQMP_NO_DDR) + fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR; if (fdt_magic(fdt_blob) == FDT_MAGIC) return fdt_blob; debug("DTB is not passed via %p\n", fdt_blob); +#endif #ifdef CONFIG_SPL_BUILD /* FDT is at end of BSS unless it is in a different memory region */ -- cgit v1.2.3 From 5028358a6a5c3e7fd2d20b190a4205ba3e136ab8 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Wed, 11 Mar 2020 03:06:04 -0600 Subject: watchdog: versal: Add support for Xilinx window watchdog Add support for Xilinx window watchdog, which can be found on Versal platforms. Signed-off-by: Ashok Reddy Soma Reviewed-by: Stefan Roese --- MAINTAINERS | 1 + drivers/watchdog/Kconfig | 9 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/xilinx_wwdt.c | 179 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 190 insertions(+) create mode 100644 drivers/watchdog/xilinx_wwdt.c diff --git a/MAINTAINERS b/MAINTAINERS index b50652bd85d..d8d420f84f7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -447,6 +447,7 @@ M: Michal Simek S: Maintained T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/mach-versal/ +F: drivers/watchdog/xilinx_wwdt.c N: (? + * Ashok Reddy Soma + * + * Copyright (c) 2020, Xilinx Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Refresh Register Masks */ +#define XWT_WWREF_GWRR_MASK BIT(0) /* Refresh and start new period */ + +/* Generic Control/Status Register Masks */ +#define XWT_WWCSR_GWEN_MASK BIT(0) /* Enable Bit */ + +/* Register offsets for the Wdt device */ +#define XWT_WWREF_OFFSET 0x1000 /* Refresh Register */ +#define XWT_WWCSR_OFFSET 0x2000 /* Control/Status Register */ +#define XWT_WWOFF_OFFSET 0x2008 /* Offset Register */ +#define XWT_WWCMP0_OFFSET 0x2010 /* Compare Value Register0 */ +#define XWT_WWCMP1_OFFSET 0x2014 /* Compare Value Register1 */ +#define XWT_WWWRST_OFFSET 0x2FD0 /* Warm Reset Register */ + +struct xlnx_wwdt_priv { + bool enable_once; + struct regmap *regs; + struct clk clk; +}; + +struct xlnx_wwdt_platdata { + bool enable_once; +}; + +static int xlnx_wwdt_reset(struct udevice *dev) +{ + struct xlnx_wwdt_priv *wdt = dev_get_priv(dev); + + regmap_write(wdt->regs, XWT_WWREF_OFFSET, XWT_WWREF_GWRR_MASK); + + return 0; +} + +static int xlnx_wwdt_stop(struct udevice *dev) +{ + u32 csr; + struct xlnx_wwdt_priv *wdt = dev_get_priv(dev); + + if (wdt->enable_once) { + dev_warn(dev, "Can't stop Xilinx watchdog.\n"); + return -EBUSY; + } + + /* Disable the generic watchdog timer */ + regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr); + csr &= ~(XWT_WWCSR_GWEN_MASK); + regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr); + + clk_disable(&wdt->clk); + + dev_dbg(dev, "Watchdog disabled!\n"); + + return 0; +} + +static int xlnx_wwdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + int ret; + u32 csr; + u64 count; + unsigned long clock_f; + struct xlnx_wwdt_priv *wdt = dev_get_priv(dev); + + clock_f = clk_get_rate(&wdt->clk); + if (IS_ERR_VALUE(clock_f)) { + dev_err(dev, "failed to get rate\n"); + return clock_f; + } + + dev_dbg(dev, "%s: CLK %ld\n", __func__, clock_f); + + /* Calculate timeout count */ + count = timeout * clock_f; + + /* clk_enable will return -ENOSYS when it is not implemented */ + ret = clk_enable(&wdt->clk); + if (ret && ret != -ENOSYS) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + + /* + * Timeout count is half as there are two windows + * first window overflow is ignored (interrupt), + * reset is only generated at second window overflow + */ + count = count >> 1; + + /* Disable the generic watchdog timer */ + regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr); + csr &= ~(XWT_WWCSR_GWEN_MASK); + regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr); + + /* Set compare and offset registers for generic watchdog timeout */ + regmap_write(wdt->regs, XWT_WWCMP0_OFFSET, (u32)count); + regmap_write(wdt->regs, XWT_WWCMP1_OFFSET, 0); + regmap_write(wdt->regs, XWT_WWOFF_OFFSET, (u32)count); + + /* Enable the generic watchdog timer */ + regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr); + csr |= (XWT_WWCSR_GWEN_MASK); + regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr); + + return 0; +} + +static int xlnx_wwdt_probe(struct udevice *dev) +{ + int ret; + struct xlnx_wwdt_platdata *platdata = dev_get_platdata(dev); + struct xlnx_wwdt_priv *wdt = dev_get_priv(dev); + + dev_dbg(dev, "%s: Probing wdt%u\n", __func__, dev->seq); + + ret = regmap_init_mem(dev_ofnode(dev), &wdt->regs); + if (ret) { + dev_dbg(dev, "failed to get regbase of wwdt\n"); + return ret; + } + + wdt->enable_once = platdata->enable_once; + + ret = clk_get_by_index(dev, 0, &wdt->clk); + if (ret < 0) + dev_err(dev, "failed to get clock\n"); + + return ret; +} + +static int xlnx_wwdt_ofdata_to_platdata(struct udevice *dev) +{ + struct xlnx_wwdt_platdata *platdata = dev_get_platdata(dev); + + platdata->enable_once = dev_read_u32_default(dev, + "xlnx,wdt-enable-once", 0); + dev_dbg(dev, "wdt-enable-once %d\n", platdata->enable_once); + + return 0; +} + +static const struct wdt_ops xlnx_wwdt_ops = { + .start = xlnx_wwdt_start, + .reset = xlnx_wwdt_reset, + .stop = xlnx_wwdt_stop, +}; + +static const struct udevice_id xlnx_wwdt_ids[] = { + { .compatible = "xlnx,versal-wwdt-1.0", }, + {}, +}; + +U_BOOT_DRIVER(xlnx_wwdt) = { + .name = "xlnx_wwdt", + .id = UCLASS_WDT, + .of_match = xlnx_wwdt_ids, + .probe = xlnx_wwdt_probe, + .priv_auto_alloc_size = sizeof(struct xlnx_wwdt_priv), + .platdata_auto_alloc_size = sizeof(struct xlnx_wwdt_platdata), + .ofdata_to_platdata = xlnx_wwdt_ofdata_to_platdata, + .ops = &xlnx_wwdt_ops, +}; -- cgit v1.2.3 From 895a7866c20cf6c01779b5a60fbf2770b88930a4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 24 Mar 2020 11:31:42 +0100 Subject: serial: zynq: Change uart initialization logic The commit a673025535ae ("serial: zynq: Initialize uart only before relocation") introduced code which detects relocation which is working for single uart instance. With multiple instances in place there is a need to enable and setup every instance. That's why detect if TX is enabled. If it is then don't initialize uart again. In post probe setbrg is called to setup baudrate but values should be the same. As a side effect of this change is that DECLARE_GLOBAL_DATA_PTR can be removed completely. Signed-off-by: Michal Simek --- drivers/serial/serial_zynq.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index e4e4c392858..0dd6cec82a6 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -17,8 +17,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */ #define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */ #define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */ @@ -45,7 +43,7 @@ struct zynq_uart_platdata { struct uart_zynq *regs; }; -/* Set up the baud rate in gd struct */ +/* Set up the baud rate */ static void _uart_zynq_serial_setbrg(struct uart_zynq *regs, unsigned long clock, unsigned long baud) { @@ -140,9 +138,12 @@ static int zynq_serial_setbrg(struct udevice *dev, int baudrate) static int zynq_serial_probe(struct udevice *dev) { struct zynq_uart_platdata *platdata = dev_get_platdata(dev); + struct uart_zynq *regs = platdata->regs; + u32 val; - /* No need to reinitialize the UART after relocation */ - if (gd->flags & GD_FLG_RELOC) + /* No need to reinitialize the UART if TX already enabled */ + val = readl(®s->control); + if (val & ZYNQ_UART_CR_TX_EN) return 0; _uart_zynq_serial_init(platdata->regs); -- cgit v1.2.3