From 6ace36e19a8cfdd16ce7c02625edf36864897bf5 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 6 Aug 2018 19:00:22 +0300 Subject: Makefile: Don't generate position independent code Since gcc-8 the --enable-default-pie starts producing code which assembler can't translate in case of U-Boot. The build fails with {standard input}: Assembler messages: {standard input}:21100: Error: junk at end of line, first unrecognized character is `@' {standard input}:21120: Error: junk at end of line, first unrecognized character is `@' and so on. This is usually the case for x86 platform because in many cases it uses host compiler from the Linux distributions, where PIE is enabled by default. Previously (gcc-7 and earlier) that was a potential issue due to absence of constructions like .long end.5561@gotoff-start.5558@gotoff which are a cause of above error messages in gcc-8. Fix all these by disabling PIE on Makefile level. Reported-by: Heinrich Schuchardt Suggested-by: Mika Westerberg Signed-off-by: Andy Shevchenko Tested-by: Heinrich Schuchardt Tested-by: Bin Meng --- Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Makefile b/Makefile index 2f79204b239..b5bf8abc1f8 100644 --- a/Makefile +++ b/Makefile @@ -375,6 +375,10 @@ KBUILD_CFLAGS := -Wall -Wstrict-prototypes \ KBUILD_CFLAGS += -fshort-wchar KBUILD_AFLAGS := -D__ASSEMBLY__ +# Don't generate position independent code +KBUILD_CFLAGS += $(call cc-option,-fno-PIE) +KBUILD_AFLAGS += $(call cc-option,-fno-PIE) + # Read UBOOTRELEASE from include/config/uboot.release (if it exists) UBOOTRELEASE = $(shell cat include/config/uboot.release 2> /dev/null) UBOOTVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION) -- cgit v1.2.3 From ceeee8f7b5f10d7736840b169249e891da0f6a47 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 10 Aug 2018 02:39:33 -0700 Subject: x86: coreboot: Add generic coreboot payload support Currently building U-Boot as the coreboot payload requires user to change the build configuration for a specific board during menuconfig process. This uses the board's native device tree to configure the hardware. For example, the device tree provides PCI address range for the PCI host controller and U-Boot will re-program all PCI devices' BAR to be within this range. In order to make sure we don't mess up the hardware, we should guarantee the range matches what coreboot programs the chipset. But we really should make the coreboot payload support easier. Just like EFI payload, we can create a generic coreboot payload for all x86 boards as well. The payload is configured to include as many generic drivers as possible. All stuff that touches low level initialization are not allowed as such is the coreboot's responsibility. Platform specific drivers (like gpio, spi, etc) are not included. Signed-off-by: Bin Meng Reviewed-by: Christian Gmeiner --- arch/x86/cpu/coreboot/Kconfig | 20 ++++++++-------- arch/x86/cpu/coreboot/coreboot.c | 9 ++++--- arch/x86/dts/Makefile | 1 + arch/x86/dts/coreboot.dts | 41 ++++++++++++++++++++++++++++++++ board/coreboot/coreboot/Kconfig | 28 ++++------------------ board/coreboot/coreboot/Makefile | 2 +- board/coreboot/coreboot/coreboot.c | 17 +++++++++++++ board/coreboot/coreboot/coreboot_start.S | 12 ---------- board/coreboot/coreboot/start.S | 12 ++++++++++ configs/coreboot_defconfig | 18 +++++--------- doc/README.x86 | 15 ------------ include/configs/coreboot.h | 32 +++++++++++++++++++++++++ 12 files changed, 128 insertions(+), 79 deletions(-) create mode 100644 arch/x86/dts/coreboot.dts create mode 100644 board/coreboot/coreboot/coreboot.c delete mode 100644 board/coreboot/coreboot/coreboot_start.S create mode 100644 board/coreboot/coreboot/start.S create mode 100644 include/configs/coreboot.h diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig index 392c2589450..93f61f2fa4f 100644 --- a/arch/x86/cpu/coreboot/Kconfig +++ b/arch/x86/cpu/coreboot/Kconfig @@ -3,26 +3,26 @@ if TARGET_COREBOOT config SYS_COREBOOT bool default y + imply SYS_NS16550 + imply SCSI + imply SCSI_AHCI imply AHCI_PCI - imply E1000 - imply ICH_SPI imply MMC imply MMC_PCI imply MMC_SDHCI imply MMC_SDHCI_SDMA - imply SCSI - imply SCSI_AHCI - imply SPI_FLASH - imply SYS_NS16550 imply USB imply USB_EHCI_HCD imply USB_XHCI_HCD + imply USB_STORAGE + imply USB_KEYBOARD imply VIDEO_COREBOOT + imply E1000 + imply ETH_DESIGNWARE + imply PCH_GBE + imply RTL8169 imply CMD_CBFS imply FS_CBFS - -config CBMEM_CONSOLE - bool - default y + imply CBMEM_CONSOLE endif diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 69025c1537b..a6fd3a849a2 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -75,12 +76,10 @@ int last_stage_init(void) if (gd->flags & GD_FLG_COLD_BOOT) timestamp_add_to_bootstage(); - board_final_cleanup(); + /* start usb so that usb keyboard can be used as input device */ + usb_init(); - return 0; -} + board_final_cleanup(); -int misc_init_r(void) -{ return 0; } diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 37e4fdc7601..c62540fe74c 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -6,6 +6,7 @@ dtb-y += bayleybay.dtb \ chromebox_panther.dtb \ chromebook_samus.dtb \ conga-qeval20-qa3-e3845.dtb \ + coreboot.dtb \ cougarcanyon2.dtb \ crownbay.dtb \ dfi-bt700-q7x-151.dtb \ diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts new file mode 100644 index 00000000000..a94f7818331 --- /dev/null +++ b/arch/x86/dts/coreboot.dts @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + * + * Generic coreboot payload device tree for x86 targets + */ + +/dts-v1/; + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" +/include/ "keyboard.dtsi" +/include/ "reset.dtsi" +/include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" + +/ { + model = "coreboot x86 payload"; + compatible = "coreboot,x86-payload"; + + aliases { + serial0 = &serial; + }; + + config { + silent_console = <0>; + }; + + chosen { + stdout-path = "/serial"; + }; + + pci { + compatible = "pci-x86"; + u-boot,dm-pre-reloc; + }; + + coreboot-fb { + compatible = "coreboot-fb"; + }; +}; diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig index cfa1d50ee45..5bd6465d989 100644 --- a/board/coreboot/coreboot/Kconfig +++ b/board/coreboot/coreboot/Kconfig @@ -9,35 +9,15 @@ config SYS_VENDOR config SYS_SOC default "coreboot" +config SYS_CONFIG_NAME + default "coreboot" + config SYS_TEXT_BASE default 0x01110000 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - imply SPI_FLASH_ATMEL - imply SPI_FLASH_EON - imply SPI_FLASH_GIGADEVICE - imply SPI_FLASH_MACRONIX - imply SPI_FLASH_SPANSION - imply SPI_FLASH_STMICRO - imply SPI_FLASH_SST - imply SPI_FLASH_WINBOND - -comment "coreboot-specific options" - -config SYS_CONFIG_NAME - string "Board configuration file" - default "qemu-x86" - help - This option selects the board configuration file in include/configs/ - directory to be used to build U-Boot for coreboot. - -config DEFAULT_DEVICE_TREE - string "Board Device Tree Source (dts) file" - default "qemu-x86_i440fx" - help - This option selects the board Device Tree Source (dts) file in - arch/x86/dts/ directory to be used to build U-Boot for coreboot. + select BOARD_EARLY_INIT_R config SYS_CAR_ADDR hex "Board specific Cache-As-RAM (CAR) address" diff --git a/board/coreboot/coreboot/Makefile b/board/coreboot/coreboot/Makefile index ea0f3ee1ae0..8db7cc62f30 100644 --- a/board/coreboot/coreboot/Makefile +++ b/board/coreboot/coreboot/Makefile @@ -10,4 +10,4 @@ # (C) Copyright 2002 # Daniel Engström, Omicron Ceti AB, daniel@omicron.se. -obj-y += coreboot_start.o +obj-y += start.o coreboot.o diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c new file mode 100644 index 00000000000..ed5606d4a44 --- /dev/null +++ b/board/coreboot/coreboot/coreboot.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + */ + +#include + +int board_early_init_r(void) +{ + /* + * Make sure PCI bus is enumerated so that peripherals on the PCI bus + * can be discovered by their drivers + */ + pci_init(); + + return 0; +} diff --git a/board/coreboot/coreboot/coreboot_start.S b/board/coreboot/coreboot/coreboot_start.S deleted file mode 100644 index aa702622d48..00000000000 --- a/board/coreboot/coreboot/coreboot_start.S +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2008 - * Graeme Russ, graeme.russ@gmail.com. - */ - -/* board early intialization */ -.globl early_board_init -early_board_init: - /* No 32-bit board specific initialisation */ - jmp early_board_init_ret diff --git a/board/coreboot/coreboot/start.S b/board/coreboot/coreboot/start.S new file mode 100644 index 00000000000..aa702622d48 --- /dev/null +++ b/board/coreboot/coreboot/start.S @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + */ + +/* board early intialization */ +.globl early_board_init +early_board_init: + /* No 32-bit board specific initialisation */ + jmp early_board_init_ret diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index 114ac6115ea..ad0b35f2046 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -4,28 +4,25 @@ CONFIG_VENDOR_COREBOOT=y CONFIG_TARGET_COREBOOT=y CONFIG_NR_DRAM_BANKS=8 CONFIG_FIT=y -CONFIG_BOOTSTAGE=y -CONFIG_BOOTSTAGE_REPORT=y +CONFIG_FIT_SIGNATURE=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" +CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_PRE_CON_BUF_ADDR=0x100000 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y +CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_PING=y CONFIG_CMD_TIME=y -CONFIG_CMD_BOOTSTAGE=y -CONFIG_CMD_TPM=y -CONFIG_CMD_TPM_TEST=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -34,11 +31,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y +CONFIG_DEFAULT_DEVICE_TREE="coreboot" CONFIG_REGMAP=y CONFIG_SYSCON=y -CONFIG_SPI=y -CONFIG_TPM_TIS_LPC=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y +# CONFIG_PCI_PNP is not set CONFIG_CONSOLE_SCROLL_LINES=5 -CONFIG_TPM=y diff --git a/doc/README.x86 b/doc/README.x86 index 9162ea17d82..6015ca40115 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -47,21 +47,6 @@ on other architectures, like below: $ make coreboot_defconfig $ make all -Note this default configuration will build a U-Boot payload for the QEMU board. -To build a coreboot payload against another board, you can change the build -configuration during the 'make menuconfig' process. - -x86 architecture ---> - ... - (qemu-x86) Board configuration file - (qemu-x86_i440fx) Board Device Tree Source (dts) file - (0x01920000) Board specific Cache-As-RAM (CAR) address - (0x4000) Board specific Cache-As-RAM (CAR) size - -Change the 'Board configuration file' and 'Board Device Tree Source (dts) file' -to point to a new board. You can also change the Cache-As-RAM (CAR) related -settings here if the default values do not fit your new board. - Build Instructions for U-Boot as main bootloader ------------------------------------------------ diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h new file mode 100644 index 00000000000..1cf5c037e85 --- /dev/null +++ b/include/configs/coreboot.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018, Bin Meng + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +/* ATA/IDE support */ +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE 4 +#define CONFIG_SYS_ATA_BASE_ADDR 0 +#define CONFIG_SYS_ATA_DATA_OFFSET 0 +#define CONFIG_SYS_ATA_REG_OFFSET 0 +#define CONFIG_SYS_ATA_ALT_OFFSET 0 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 +#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 +#define CONFIG_ATAPI + +#endif /* __CONFIG_H */ -- cgit v1.2.3 From 6e71a6ab2d9e06a275e40a8c5c8e0b29cf6bb8fb Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 10 Aug 2018 02:39:34 -0700 Subject: x86: Remove support for Advantech SOM-6896 Now that we have generic coreboot payload support, remove the dedicated support for Advantech SOM-6896. Signed-off-by: Bin Meng --- arch/x86/dts/Makefile | 1 - arch/x86/dts/broadwell_som-6896.dts | 52 ------------------------------------- include/configs/som-6896.h | 26 ------------------- 3 files changed, 79 deletions(-) delete mode 100644 arch/x86/dts/broadwell_som-6896.dts delete mode 100644 include/configs/som-6896.h diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index c62540fe74c..fa717bc0966 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -18,7 +18,6 @@ dtb-y += bayleybay.dtb \ qemu-x86_i440fx.dtb \ qemu-x86_q35.dtb \ theadorable-x86-dfi-bt700.dtb \ - broadwell_som-6896.dtb \ baytrail_som-db5800-som-6867.dtb targets += $(dtb-y) diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts deleted file mode 100644 index ec691f136a7..00000000000 --- a/arch/x86/dts/broadwell_som-6896.dts +++ /dev/null @@ -1,52 +0,0 @@ -/dts-v1/; - -/include/ "skeleton.dtsi" -/include/ "serial.dtsi" -/include/ "reset.dtsi" -/include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" -/include/ "coreboot_fb.dtsi" - -/ { - model = "Advantech SOM-6896"; - compatible = "advantech,som-6896", "intel,broadwell"; - - aliases { - spi0 = &spi; - }; - - config { - silent_console = <0>; - }; - - chosen { - stdout-path = "/serial"; - }; - - pci { - compatible = "pci-x86"; - #address-cells = <3>; - #size-cells = <2>; - u-boot,dm-pre-reloc; - ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000 - 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 - 0x01000000 0x0 0x2000 0x2000 0 0xe000>; - - pch@1f,0 { - reg = <0x0000f800 0 0 0 0>; - compatible = "intel,pch9"; - - spi: spi { - #address-cells = <1>; - #size-cells = <0>; - compatible = "intel,ich9-spi"; - spi-flash@0 { - reg = <0>; - compatible = "winbond,w25q128", "spi-flash"; - memory-map = <0xff000000 0x01000000>; - }; - }; - }; - }; - -}; diff --git a/include/configs/som-6896.h b/include/configs/som-6896.h deleted file mode 100644 index 031b82bfb99..00000000000 --- a/include/configs/som-6896.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the SOM-6896 - * - * Copyright (C) 2015 NovaTech LLC - * George McCollister - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_SYS_MONITOR_LEN (1 << 20) - -#define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" - -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_OFFSET 0x00ff0000 - -#endif /* __CONFIG_H */ -- cgit v1.2.3 From 1cf6825a681c289032f6309d3ac5eab2fd71a703 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 10 Aug 2018 02:39:35 -0700 Subject: x86: dts: Remove coreboot_fb.dtsi There is no need to keep a separate coreboot_fb.dtsi since now we have a generic coreboot payload dts. While we are here, this also remove the out-of-date description in the documentation regarding to coreboot framebuffer driver with U-Boot loaded as a payload from coreboot. As the testing result with QEMU 2.5.0 shows, the driver just works like a charm. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/dts/bayleybay.dts | 1 - arch/x86/dts/chromebook_link.dts | 1 - arch/x86/dts/chromebook_samus.dts | 1 - arch/x86/dts/chromebox_panther.dts | 1 - arch/x86/dts/coreboot_fb.dtsi | 5 ----- arch/x86/dts/minnowmax.dts | 1 - doc/README.x86 | 7 ------- 7 files changed, 17 deletions(-) delete mode 100644 arch/x86/dts/coreboot_fb.dtsi diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 9683c525a7f..291dc07ff60 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -15,7 +15,6 @@ /include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" -/include/ "coreboot_fb.dtsi" / { model = "Intel Bayley Bay"; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 115a088a7af..f9f09797302 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -8,7 +8,6 @@ /include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" -/include/ "coreboot_fb.dtsi" / { model = "Google Link"; diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts index 9c48c9a3fa7..b58936b4ac9 100644 --- a/arch/x86/dts/chromebook_samus.dts +++ b/arch/x86/dts/chromebook_samus.dts @@ -8,7 +8,6 @@ /include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" -/include/ "coreboot_fb.dtsi" / { model = "Google Samus"; diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts index a72a85ef9c4..f56e482944b 100644 --- a/arch/x86/dts/chromebox_panther.dts +++ b/arch/x86/dts/chromebox_panther.dts @@ -5,7 +5,6 @@ /include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" -/include/ "coreboot_fb.dtsi" / { model = "Google Panther"; diff --git a/arch/x86/dts/coreboot_fb.dtsi b/arch/x86/dts/coreboot_fb.dtsi deleted file mode 100644 index 7d72f185373..00000000000 --- a/arch/x86/dts/coreboot_fb.dtsi +++ /dev/null @@ -1,5 +0,0 @@ -/ { - coreboot-fb { - compatible = "coreboot-fb"; - }; -}; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 02ab4c160ae..6c65fb9611c 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -14,7 +14,6 @@ /include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" -/include/ "coreboot_fb.dtsi" / { model = "Intel Minnowboard Max"; diff --git a/doc/README.x86 b/doc/README.x86 index 6015ca40115..8cc46725f2a 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -412,17 +412,10 @@ To enable video you must enable these options in coreboot: - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5)) - Keep VESA framebuffer -And include coreboot_fb.dtsi in your board's device tree source file, like: - - /include/ "coreboot_fb.dtsi" - At present it seems that for Minnowboard Max, coreboot does not pass through the video information correctly (it always says the resolution is 0x0). This works correctly for link though. -Note: coreboot framebuffer driver does not work on QEMU. The reason is unknown -at this point. Patches are welcome if you figure out anything wrong. - Test with QEMU for bare mode ---------------------------- QEMU is a fancy emulator that can enable us to test U-Boot without access to -- cgit v1.2.3 From 165db7c426f1946376c3643fd635afd6b167e3ee Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 10 Aug 2018 02:39:36 -0700 Subject: x86: tsc: Try hardware calibration first At present if TSC frequency is provided in the device tree, it takes precedence over hardware calibration result. This swaps the order to try hardware calibration first and uses device tree as last resort. This can be helpful when a generic dts (eg: coreboot/efi payload) is supposed to work on as many hardware as possible, including emulators like QEMU where TSC hardware calibration sometimes fails. Signed-off-by: Bin Meng Reviewed-by: Christian Gmeiner --- drivers/timer/tsc_timer.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index 747f190d384..6473de20f13 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -341,16 +341,12 @@ static int tsc_timer_get_count(struct udevice *dev, u64 *count) return 0; } -static void tsc_timer_ensure_setup(void) +static void tsc_timer_ensure_setup(bool stop) { if (gd->arch.tsc_base) return; gd->arch.tsc_base = rdtsc(); - /* - * If there is no clock frequency specified in the device tree, - * calibrate it by ourselves. - */ if (!gd->arch.clock_rate) { unsigned long fast_calibrate; @@ -366,7 +362,10 @@ static void tsc_timer_ensure_setup(void) if (fast_calibrate) goto done; - panic("TSC frequency is ZERO"); + if (stop) + panic("TSC frequency is ZERO"); + else + return; done: gd->arch.clock_rate = fast_calibrate * 1000000; @@ -377,11 +376,17 @@ static int tsc_timer_probe(struct udevice *dev) { struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); - if (!uc_priv->clock_rate) { - tsc_timer_ensure_setup(); - uc_priv->clock_rate = gd->arch.clock_rate; + /* Try hardware calibration first */ + tsc_timer_ensure_setup(false); + if (!gd->arch.clock_rate) { + /* + * Use the clock frequency specified in the + * device tree as last resort + */ + if (!uc_priv->clock_rate) + panic("TSC frequency is ZERO"); } else { - gd->arch.tsc_base = rdtsc(); + uc_priv->clock_rate = gd->arch.clock_rate; } return 0; @@ -394,7 +399,7 @@ unsigned long notrace timer_early_get_rate(void) * clock rate can only be calibrated via some hardware ways. Specifying * it in the device tree won't work for the early timer. */ - tsc_timer_ensure_setup(); + tsc_timer_ensure_setup(true); return gd->arch.clock_rate; } -- cgit v1.2.3 From 864915561b3273a4f8894804146d6739e8e49ab2 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 10 Aug 2018 02:39:37 -0700 Subject: x86: coreboot: Add default TSC frequency in the device tree It was observed sometimes U-Boot as the coreboot payload fails to boot on QEMU. This is because TSC calibration fails with no valid frequency. This adds default TSC frequency in the device tree. Signed-off-by: Bin Meng Reviewed-by: Christian Gmeiner --- arch/x86/dts/coreboot.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts index a94f7818331..e212f3dc7db 100644 --- a/arch/x86/dts/coreboot.dts +++ b/arch/x86/dts/coreboot.dts @@ -30,6 +30,10 @@ stdout-path = "/serial"; }; + tsc-timer { + clock-frequency = <1000000000>; + }; + pci { compatible = "pci-x86"; u-boot,dm-pre-reloc; -- cgit v1.2.3 From 7bdf39cfafd29fc1192dd1aa997b5937f92a3c74 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 10 Aug 2018 02:39:38 -0700 Subject: x86: efi: payload: Add default TSC frequency in the device tree It was observed sometimes U-Boot as the EFI payload fails to boot on QEMU. This is because TSC calibration fails with no valid frequency. This adds default TSC frequency in the device tree. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/dts/efi-x86_payload.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/dts/efi-x86_payload.dts b/arch/x86/dts/efi-x86_payload.dts index 19f253064bc..5ccb9867749 100644 --- a/arch/x86/dts/efi-x86_payload.dts +++ b/arch/x86/dts/efi-x86_payload.dts @@ -30,6 +30,10 @@ stdout-path = "/serial"; }; + tsc-timer { + clock-frequency = <1000000000>; + }; + pci { compatible = "pci-x86"; u-boot,dm-pre-reloc; -- cgit v1.2.3