From dcb1b7b6449e82a79b06e31af052628c3d58dc70 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 25 Jun 2024 10:26:15 +0200 Subject: ARM: imx: verdin-imx8mm: Set CAN oscillator frequency based on model The older i.MX8M Mini Verdin SoMs may came with 20 MHz SPI CAN controller oscillator, the newer SoMs always use 40 MHz oscillator. Handle both by overriding the oscillator frequency just before booting the kernel. These are the known variants with 20 MHz oscillator: - 0055, V1.1A, V1.1B, V1.1C and V1.1D, use a 20MHz oscillator - 0059, V1.1A and V1.1B, use a 20MHz oscillator Signed-off-by: Marek Vasut Reviewed-by: Francesco Dolcini --- board/toradex/verdin-imx8mm/verdin-imx8mm.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 4230f417d19..9359e0ac6bf 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -126,6 +126,35 @@ int board_phys_sdram_size(phys_size_t *size) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { + const char *canoscpath = "/oscillator"; + int freq = 40000000; /* 40 MHz is used on most variants */ + int canoscoff, ret; + + canoscoff = fdt_path_offset(blob, canoscpath); + if (canoscoff < 0) /* No CAN oscillator found. */ + goto exit; + + /* + * The following "prodid" (PID4 in Toradex naming) use + * a 20MHz CAN oscillator: + * - 0055, V1.1A, V1.1B, V1.1C and V1.1D + * - 0059, V1.1A and V1.1B + */ + if ((tdx_hw_tag.ver_major == 1 && tdx_hw_tag.ver_minor == 1) && + ((tdx_hw_tag.prodid == VERDIN_IMX8MMQ_IT && + tdx_hw_tag.ver_assembly <= 1) || /* 0059 rev. A or B */ + (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT && + tdx_hw_tag.ver_assembly <= 3))) { /* 0055 rev. A/B/C/D */ + freq = 20000000; + } + + ret = fdt_setprop_u32(blob, canoscoff, "clock-frequency", freq); + if (ret < 0) { + printf("Failed to set CAN oscillator clock-frequency, ret=%d\n", + ret); + } + +exit: return ft_common_board_setup(blob, bd); } #endif -- cgit v1.2.3 From 353b674fb2c4174ad759799e0f3f0e3a1a9a30f8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 27 Jun 2024 02:01:21 +0200 Subject: ARM: imx: Enable cat and xxd commands on DH i.MX8M Plus DHCOM Enable 'cat' command to print file from filesystem to stdout. Enable 'xxd' command to hexdump file from filesystem to stdout. Signed-off-by: Marek Vasut --- configs/imx8mp_dhcom_pdk2_defconfig | 2 ++ configs/imx8mp_dhcom_pdk3_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig index 0ad0e238767..cbc608dd912 100644 --- a/configs/imx8mp_dhcom_pdk2_defconfig +++ b/configs/imx8mp_dhcom_pdk2_defconfig @@ -108,6 +108,8 @@ CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CAT=y +CONFIG_CMD_XXD=y CONFIG_CMD_DHCP=y CONFIG_CMD_DHCP6=y CONFIG_CMD_TFTPPUT=y diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig index 5520a4dab73..8ef8bf4db27 100644 --- a/configs/imx8mp_dhcom_pdk3_defconfig +++ b/configs/imx8mp_dhcom_pdk3_defconfig @@ -111,6 +111,8 @@ CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CAT=y +CONFIG_CMD_XXD=y CONFIG_CMD_DHCP=y CONFIG_CMD_DHCP6=y CONFIG_CMD_TFTPPUT=y -- cgit v1.2.3 From 80c588f000cfa1f6c6c1b147a92fd894fa2f418b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 27 Jun 2024 02:13:15 +0200 Subject: ARM: imx: Enable PCA953x driver on DH i.MX8MP DHCOM PDK2 Enable PCA953x GPIO expander driver in DH i.MX8MP DHCOM PDK2 configuration. The PCA9539 GPIO expander is used on production DH i.MX8MP DHCOM SoM rev.200. This is already enabled in DH i.MX8MP DHCOM PDK3 configuration so align the two configurations. Fixes: 9de599ec3d59 ("arm64: dts: imx8mp: Update i.MX8MP DHCOM SoM DT to production rev.200") Signed-off-by: Marek Vasut --- configs/imx8mp_dhcom_pdk2_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig index cbc608dd912..79b3e96c8e3 100644 --- a/configs/imx8mp_dhcom_pdk2_defconfig +++ b/configs/imx8mp_dhcom_pdk2_defconfig @@ -182,6 +182,7 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_GPIO_HOG=y CONFIG_SPL_GPIO_HOG=y CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y # CONFIG_INPUT is not set CONFIG_LED=y -- cgit v1.2.3 From ddc869ebe9e62bcf7b028dcb2404df4c5a59a54b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 27 Jun 2024 02:13:16 +0200 Subject: ARM: imx: Update Fast ethernet PHY MDIO addresses to match DH i.MX8MP DHCOM rev.200 The production DH i.MX8MP DHCOM SoM rev.200 uses updated PHY MDIO addresses for the Fast ethernet PHYs. Update the base SoM DT and SoM rev.100 backward compatibility DTO to cater for this change. Since the MDIO address adjustment is now also in the rev.100 SoM DTO, not only in the rev.100 PDK3 DTO, update Makefile accordingly as well, else the DTC would complain about the DTO overriding the 'reg' property without also updating the node unit-address, which is not doable without duplicating the entire PHY node in the DTO, which leads to large amount of duplication with no gain. Fixes: 9de599ec3d59 ("arm64: dts: imx8mp: Update i.MX8MP DHCOM SoM DT to production rev.200") Signed-off-by: Marek Vasut --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts | 5 +++++ arch/arm/dts/imx8mp-dhcom-som.dtsi | 8 ++++---- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9968e819550..45af7662075 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1298,6 +1298,7 @@ targets += $(dtb-y) # Add any required device tree compiler flags here DTC_FLAGS += -a 0x8 +DTC_FLAGS_imx8mp-dhcom-som-overlay-rev100 += -Wno-avoid_default_addr_size -Wno-reg_format DTC_FLAGS_imx8mp-dhcom-pdk3-overlay-rev100 += -Wno-avoid_default_addr_size -Wno-reg_format PHONY += dtbs diff --git a/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts b/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts index 0e5d329b149..b2154d57e48 100644 --- a/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts +++ b/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts @@ -35,6 +35,7 @@ ðphy0f { /* SMSC LAN8740Ai */ pinctrl-0 = <&pinctrl_ethphy0 &pinctrl_ioexp>; reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + reg = <0>; }; ðphy0g { /* Micrel KSZ9131RNXI */ @@ -42,6 +43,10 @@ reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; }; +ðphy1f { /* SMSC LAN8740Ai */ + reg = <1>; +}; + &i2c3 { adc@48 { compatible = "ti,tla2024"; diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi b/arch/arm/dts/imx8mp-dhcom-som.dtsi index b504d36818b..f2d99d05854 100644 --- a/arch/arm/dts/imx8mp-dhcom-som.dtsi +++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi @@ -100,14 +100,14 @@ #size-cells = <0>; /* Up to one of these two PHYs may be populated. */ - ethphy0f: ethernet-phy@0 { /* SMSC LAN8740Ai */ + ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */ compatible = "ethernet-phy-id0007.c110", "ethernet-phy-ieee802.3-c22"; interrupt-parent = <&gpio3>; interrupts = <19 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&pinctrl_ethphy0>; pinctrl-names = "default"; - reg = <0>; + reg = <1>; reset-assert-us = <1000>; reset-deassert-us = <1000>; reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>; @@ -146,14 +146,14 @@ #size-cells = <0>; /* Up to one PHY may be populated. */ - ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */ + ethphy1f: ethernet-phy@2 { /* SMSC LAN8740Ai */ compatible = "ethernet-phy-id0007.c110", "ethernet-phy-ieee802.3-c22"; interrupt-parent = <&gpio4>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&pinctrl_ethphy1>; pinctrl-names = "default"; - reg = <1>; + reg = <2>; reset-assert-us = <1000>; reset-deassert-us = <1000>; reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; -- cgit v1.2.3 From 0515680497d15ba2904365b2bbeb095ef4973f96 Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Tue, 2 Jul 2024 12:26:17 +0200 Subject: clk: imx: Fix wrong flags assignment clk-composite-8m The mux flags (u8), div flags (u8), and gate flags (u8) are not the clk flags (unsigned long). They have different meanings Signed-off-by: Michael Trimarchi --- drivers/clk/imx/clk-composite-8m.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index 45f1bcaea28..a7f98393f2b 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -134,7 +134,6 @@ struct clk *imx8m_clk_composite_flags(const char *name, mux->shift = PCG_PCS_SHIFT; mux->mask = PCG_PCS_MASK; mux->num_parents = num_parents; - mux->flags = flags; mux->parent_names = parent_names; div = kzalloc(sizeof(*div), GFP_KERNEL); @@ -144,7 +143,7 @@ struct clk *imx8m_clk_composite_flags(const char *name, div->reg = reg; div->shift = PCG_PREDIV_SHIFT; div->width = PCG_PREDIV_WIDTH; - div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags; + div->flags = CLK_DIVIDER_ROUND_CLOSEST; gate = kzalloc(sizeof(*gate), GFP_KERNEL); if (!gate) @@ -152,7 +151,6 @@ struct clk *imx8m_clk_composite_flags(const char *name, gate->reg = reg; gate->bit_idx = PCG_CGC_SHIFT; - gate->flags = flags; clk = clk_register_composite(NULL, name, parent_names, num_parents, -- cgit v1.2.3 From a66b2ce6bda1c91754a4a0cfe9ec849a387b279e Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Tue, 2 Jul 2024 12:26:18 +0200 Subject: clk: imx: Fix wrong flags assignment clk-composite-93 The mux flags (u8), div flags (u8), and gate flags (u8) are not the clk flags (unsigned long). They have different meanings Signed-off-by: Michael Trimarchi --- drivers/clk/imx/clk-composite-93.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/imx/clk-composite-93.c b/drivers/clk/imx/clk-composite-93.c index 2cf20be2cca..61692d34f92 100644 --- a/drivers/clk/imx/clk-composite-93.c +++ b/drivers/clk/imx/clk-composite-93.c @@ -102,7 +102,6 @@ struct clk *imx93_clk_composite_flags(const char *name, mux->mask = CCM_MUX_MASK; mux->num_parents = num_parents; mux->parent_names = parent_names; - mux->flags = flags; div = kzalloc(sizeof(*div), GFP_KERNEL); if (!div) @@ -119,7 +118,6 @@ struct clk *imx93_clk_composite_flags(const char *name, gate->reg = reg; gate->bit_idx = CCM_OFF_SHIFT; - gate->flags = flags; clk = clk_register_composite(NULL, name, parent_names, num_parents, -- cgit v1.2.3 From 3a6a7a8dda69bc51c68be0f2287a6c1dbf9b41b6 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 4 Jul 2024 09:03:37 -0300 Subject: msc_sm2s_imx8mp: Adjust the initrd_addr location Booting an initramfs with the current initrd_addr address may lead to initramfs corruption and boot failure. Fix the initramfs problem by applying the following layout suggested by Tom Rini: loadaddr=0x40480000 --> Gets moved to 0x40600000 in run-time: Uncompressing Kernel Image Moving Image from 0x40480000 to 0x40600000, end=41e80000 fdt_addr_r= moved loadaddr + 128 MiB = 0x48600000 initrd_addr=fdt_addr_r + 512 KiB = 0x48680000 Signed-off-by: Fabio Estevam Tested-by: Stefano Babic Reviewed-by: Tom Rini --- include/configs/msc_sm2s_imx8mp.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h index 1325859b039..ea5c93ecf69 100644 --- a/include/configs/msc_sm2s_imx8mp.h +++ b/include/configs/msc_sm2s_imx8mp.h @@ -35,10 +35,10 @@ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "image=Image\0" \ "console=ttymxc1,115200\0" \ - "fdt_addr_r=0x43000000\0" \ + "fdt_addr_r=0x48600000\0" \ "boot_fdt=try\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "initrd_addr=0x43800000\0" \ + "initrd_addr=0x48680000\0" \ "bootm_size=0x10000000\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ -- cgit v1.2.3 From c619535eb5433110b5f39417f332cace81d9cff0 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 4 Jul 2024 16:22:46 -0500 Subject: ARM: dts: imx8mp-beacon-kit-u-boot: Drop EQoS clock work-around Since commit ecb1c37a7b64 ("clk: imx8mp: Add EQoS MAC clock"), the clocks for the DWMAC driver can be configured, and removing them breaks operation. Fixes: ecb1c37a7b64 ("clk: imx8mp: Add EQoS MAC clock") Suggested-by: Tim Harvey Signed-off-by: Adam Ford Reviewed-by: Peng Fan --- arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi index ed183f83a77..380146596c0 100644 --- a/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi @@ -32,12 +32,6 @@ bootph-pre-ram; }; -&eqos { - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-parents; - /delete-property/ assigned-clock-rates; -}; - ðphy0 { reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; reset-assert-us = <15000>; -- cgit v1.2.3 From 2aba1de6b5e76a697b17761dde14166a4d0b8cba Mon Sep 17 00:00:00 2001 From: Leonard Anderweit Date: Fri, 5 Jul 2024 14:11:21 +0200 Subject: configs: phycore-imx8mp_defconfig: Initialize caam Initialize the Cryptographic Accelerator and Assurance Module. Signed-off-by: Leonard Anderweit --- configs/phycore-imx8mp_defconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 57e320af603..8dd4963bdc0 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -32,6 +32,7 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_BOARD_INIT=y @@ -44,6 +45,7 @@ CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +# CONFIG_SPL_CRYPTO is not set CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y @@ -86,6 +88,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y +CONFIG_FSL_CAAM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x42800000 CONFIG_FASTBOOT_BUF_SIZE=0x13000000 @@ -101,7 +104,6 @@ CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y # CONFIG_SPL_DM_I2C is not set CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x51 CONFIG_SUPPORT_EMMC_BOOT=y @@ -151,3 +153,4 @@ CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_IMX_WATCHDOG=y +# CONFIG_SPL_SHA_HW_ACCEL is not set -- cgit v1.2.3 From d0e4f56c4793a24e4ee8300320fe53d627d5a234 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 5 Jul 2024 15:27:24 +0200 Subject: mmc: fsl_esdhc_imx: Fix error message Add missing newline character and also add the return code of regulator_set_value() to the output. Signed-off-by: Alexander Stein --- drivers/mmc/fsl_esdhc_imx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index a9b8d7dd67f..03de7dcd505 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -766,7 +766,7 @@ static int esdhc_set_voltage(struct mmc *mmc) ret = regulator_set_value(priv->vqmmc_dev, 3300000); if (ret) { - printf("Setting to 3.3V error"); + printf("Setting to 3.3V error: %d\n", ret); return -EIO; } mdelay(5); @@ -784,7 +784,7 @@ static int esdhc_set_voltage(struct mmc *mmc) ret = regulator_set_value(priv->vqmmc_dev, 1800000); if (ret) { - printf("Setting to 1.8V error"); + printf("Setting to 1.8V error: %d\n", ret); return -EIO; } } -- cgit v1.2.3 From 9a827d91495171f44563db9fe4e621fea43d8178 Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Fri, 5 Jul 2024 09:19:51 +0200 Subject: clk: clk-mux: Make public the clk_fetch_parent_index Make public the clk_fetch_parent_index and rename it. This allow us to be reused in driver specialization Signed-off-by: Michael Trimarchi --- drivers/clk/clk-mux.c | 5 ++--- include/linux/clk-provider.h | 1 + 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 39e01c3fbc6..62477e15d27 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -101,8 +101,7 @@ u8 clk_mux_get_parent(struct clk *clk) return clk_mux_val_to_index(clk, mux->table, mux->flags, val); } -static int clk_fetch_parent_index(struct clk *clk, - struct clk *parent) +int clk_mux_fetch_parent_index(struct clk *clk, struct clk *parent) { struct clk_mux *mux = to_clk_mux(clk); @@ -126,7 +125,7 @@ static int clk_mux_set_parent(struct clk *clk, struct clk *parent) u32 val; u32 reg; - index = clk_fetch_parent_index(clk, parent); + index = clk_mux_fetch_parent_index(clk, parent); if (index < 0) { log_err("Could not fetch index\n"); return index; diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index b8acacd49ee..59f9c241b84 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -74,6 +74,7 @@ struct clk_mux { #define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk) extern const struct clk_ops clk_mux_ops; u8 clk_mux_get_parent(struct clk *clk); +int clk_mux_fetch_parent_index(struct clk *clk, struct clk *parent); /** * clk_mux_index_to_val() - Convert the parent index to the register value -- cgit v1.2.3 From 3d4c29258f8b4c4a5cf4ce79fb1ac80f66e4cf65 Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Fri, 5 Jul 2024 09:19:52 +0200 Subject: clk: imx: add mux ops for i.MX8M composite clk Upstream Linux commit f90b68d6c8b0. The CORE/BUS root slice has following design, simplied graph: The difference is core not have pre_div block. A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7]. It support target(smart) interface and normal interface. Target interface is exported for programmer easy to configure ccm root. Normal interface is also exported, but we not use it in our driver, because it will introduce more complexity compared with target interface. The normal interface simplified as below: SEL_A GA +--+ +-+ | +->+ +------+ CLK[0-7]--->+ | +-+ | | | | +----v---+ +----+ | +--+ |pre_diva+----> | +---------+ | +--------+ |mux +--+post_div | | +--+ |pre_divb+--->+ | +---------+ | | | +----^---+ +----+ +--->+ | +-+ | | +->+ +------+ +--+ +-+ SEL_B GB The mux in the upper pic is not the target interface MUX, target interface MUX is hiding SEL_A and SEL_B. When you choose clk[0-7], you are actually writing SEL_A or SEL_B depends on the internal counter which will also control the internal "mux". The target interface simplified as below which is used by Linux Kernel: CLK[0-7]--->MUX-->Gate-->pre_div-->post_div A requirement of the Target Interface's software is that the target clock source is active, it means when setting SEL_A, the current input clk to SEL_A must be active, same to SEL_B. We touch target interface, but hardware logic actually also need configure normal interface. There will be system hang, when doing the following steps: The initial state: SEL_A/SEL_B are both sourcing from clk0, the internal counter choose SEL_A. 1. switch mux from clk0 to clk1 The hardware logic will choose SEL_B and configure SEL_B to clk1. SEL_A no changed. 2. gate off clk0 Disable clk0, then the input to SEL_A is off. 3. switch from clk1 to clk2 The hardware logic will choose SEL_A and configure SEL_A to clk2, however the current SEL_A input clk0 is off, the system hang. The solution to fix the issue is in step 1, write twice to target interface MUX, it will make SEL_A/SEL_B both sources from clk1, then no need to care about the state of clk0. And finally system performs well. Signed-off-by: Peng Fan Reviewed-by: Dong Aisheng Signed-off-by: Shawn Guo Signed-off-by: Michael Trimarchi --- drivers/clk/imx/clk-composite-8m.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index a7f98393f2b..64bffa3b181 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -116,6 +116,41 @@ static const struct clk_ops imx8m_clk_composite_divider_ops = { .set_rate = imx8m_clk_composite_divider_set_rate, }; +static int imx8m_clk_mux_set_parent(struct clk *clk, struct clk *parent) +{ + struct clk_mux *mux = to_clk_mux(clk); + int index; + u32 val; + u32 reg; + + index = clk_mux_fetch_parent_index(clk, parent); + if (index < 0) { + log_err("Could not fetch index\n"); + return index; + } + + val = clk_mux_index_to_val(mux->table, mux->flags, index); + + reg = readl(mux->reg); + reg &= ~(mux->mask << mux->shift); + val = val << mux->shift; + reg |= val; + + /* + * write twice to make sure non-target interface + * SEL_A/B point the same clk input. + */ + writel(reg, mux->reg); + writel(reg, mux->reg); + + return 0; +} + +const struct clk_ops imx8m_clk_mux_ops = { + .get_rate = clk_generic_get_rate, + .set_parent = imx8m_clk_mux_set_parent, +}; + struct clk *imx8m_clk_composite_flags(const char *name, const char * const *parent_names, int num_parents, void __iomem *reg, @@ -154,7 +189,7 @@ struct clk *imx8m_clk_composite_flags(const char *name, clk = clk_register_composite(NULL, name, parent_names, num_parents, - &mux->clk, &clk_mux_ops, &div->clk, + &mux->clk, &imx8m_clk_mux_ops, &div->clk, &imx8m_clk_composite_divider_ops, &gate->clk, &clk_gate_ops, flags); if (IS_ERR(clk)) -- cgit v1.2.3