From 54f5f056aa1daa3e39bad1c5c3fb43a72cdb9e84 Mon Sep 17 00:00:00 2001 From: Mike Nuss Date: Mon, 5 Oct 2009 12:33:28 -0400 Subject: PPC4xx: Denali core: Fix incorrect DDR row bits The SPD detection code for the Denali memory controller used on some ppc4xx processors incorrectly encodes DDR0_42. With certain memory configurations, this can cause the bootwrapper to incorrectly calculate the installed memory size, because the number of row bits is wrong. This patch fixes that encoding. Signed-off-by: Mike Nuss Signed-off-by: Stefan Roese --- cpu/ppc4xx/denali_spd_ddr2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c index 4705e21b57c..5858cb36a5a 100644 --- a/cpu/ppc4xx/denali_spd_ddr2.c +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -1159,7 +1159,7 @@ phys_size_t initdram(int board_type) mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000)); - mtsdram(DDR0_42, DDR0_42_ADDR_PINS_DECODE(14 - rows) | + mtsdram(DDR0_42, DDR0_42_ADDR_PINS_ENCODE(14 - rows) | DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency)); program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq, -- cgit v1.2.3