From 67180fe10102815924375d34bf6c6799e5ede8eb Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 1 May 2019 18:20:00 +0200 Subject: serial: sh: Add RZ/A1 support Add support for RZ/A1 SoC specifics. Signed-off-by: Marek Vasut Cc: Chris Brandt Cc: Nobuhiro Iwamatsu --- drivers/serial/serial_sh.c | 3 +++ drivers/serial/serial_sh.h | 3 ++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index e6fe5c7c677..8f52f9dce48 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -62,6 +62,9 @@ static void sh_serial_init_generic(struct uart_port *port) sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST); sci_in(port, SCFCR); sci_out(port, SCFCR, 0); +#if defined(CONFIG_RZA1) + sci_out(port, SCSPTR, 0x0003); +#endif } static void diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 887dd19ff58..8aa80d4a371 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -195,7 +195,7 @@ struct uart_port { # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ # endif # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ -#elif defined(CONFIG_CPU_SH7269) +#elif defined(CONFIG_CPU_SH7269) || defined(CONFIG_RZA1) # define SCSPTR0 0xe8007020 /* 16 bit SCIF */ # define SCSPTR1 0xe8007820 /* 16 bit SCIF */ # define SCSPTR2 0xe8008020 /* 16 bit SCIF */ @@ -205,6 +205,7 @@ struct uart_port { # define SCSPTR6 0xe800a020 /* 16 bit SCIF */ # define SCSPTR7 0xe800a820 /* 16 bit SCIF */ # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ +# define SCIF_ORER 0x0001 /* overrun error bit */ #elif defined(CONFIG_CPU_SH7619) # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ -- cgit v1.2.3