From 382de4a7e9278cdd086897ef94b02d35cbd8aa5e Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 26 Jun 2019 13:51:46 +0900 Subject: arm64: add an option to switch visibility of CONFIG_SYS_INIT_SP_BSS_OFFSET By default, CONFIG_SYS_INIT_SP_BSS_OFFSET was made invisible by not giving a prompt to it. The only way to define it is to hard-code an extra entry in SoC/board Kconfig, like arch/arm/mach-tegra/tegra{186,210}/Kconfig. Add a prompt to it in order to allow defconfig files to specify the value of CONFIG_SYS_INIT_SP_BSS_OFFSET. With this, CONFIG_SYS_INIT_SP_BSS_OFFSET would become always visible. So, we need a new bool option to turn it off by default. I move the 'default 524288' to the common place. This value is not too big, but is big enough to avoid the overwrap of DT in most platforms. If 512KB is not a suitable choice for your platform, you can change it from your defconfig or menuconfig etc. Signed-off-by: Masahiro Yamada Acked-by: Stephen Warren --- Makefile | 4 ++-- arch/arm/Kconfig | 20 +++++++++++++++----- arch/arm/cpu/armv8/linux-kernel-image-header-vars.h | 2 +- arch/arm/lib/crt0_64.S | 2 +- arch/arm/mach-tegra/Kconfig | 1 + arch/arm/mach-tegra/tegra186/Kconfig | 3 --- arch/arm/mach-tegra/tegra210/Kconfig | 3 --- 7 files changed, 20 insertions(+), 15 deletions(-) diff --git a/Makefile b/Makefile index 516260f46d0..73fdf70cddf 100644 --- a/Makefile +++ b/Makefile @@ -874,7 +874,7 @@ ifneq ($(CONFIG_BUILD_TARGET),) ALL-y += $(CONFIG_BUILD_TARGET:"%"=%) endif -ifneq ($(CONFIG_SYS_INIT_SP_BSS_OFFSET),) +ifdef CONFIG_INIT_SP_RELATIVE ALL-y += init_sp_bss_offset_check endif @@ -1155,7 +1155,7 @@ binary_size_check: u-boot-nodtb.bin FORCE fi \ fi -ifneq ($(CONFIG_SYS_INIT_SP_BSS_OFFSET),) +ifdef CONFIG_INIT_SP_RELATIVE ifneq ($(CONFIG_SYS_MALLOC_F_LEN),) subtract_sys_malloc_f_len = space=$$(($${space} - $(CONFIG_SYS_MALLOC_F_LEN))) else diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f5a7630e4f9..87541977259 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -20,15 +20,25 @@ config POSITION_INDEPENDENT information that is embedded into the binary to support U-Boot relocating itself to the top-of-RAM later during execution. -config SYS_INIT_SP_BSS_OFFSET - int +config INIT_SP_RELATIVE + bool "Specify the early stack pointer relative to the .bss section" help U-Boot typically uses a hard-coded value for the stack pointer - before relocation. Define this option to instead calculate the + before relocation. Enable this option to instead calculate the initial SP at run-time. This is useful to avoid hard-coding addresses into U-Boot, so that can be loaded and executed at arbitrary - addresses and thus avoid using arbitrary addresses at runtime. This - option's value is the offset added to &_bss_start in order to + addresses and thus avoid using arbitrary addresses at runtime. + + If this option is enabled, the early stack pointer is set to + &_bss_start with a offset value added. The offset is specified by + SYS_INIT_SP_BSS_OFFSET. + +config SYS_INIT_SP_BSS_OFFSET + int "Early stack offset from the .bss base address" + depends on INIT_SP_RELATIVE + default 524288 + help + This option's value is the offset added to &_bss_start in order to calculate the stack pointer. This offset should be large enough so that the early malloc region, global data (gd), and early stack usage do not overlap any appended DTB. diff --git a/arch/arm/cpu/armv8/linux-kernel-image-header-vars.h b/arch/arm/cpu/armv8/linux-kernel-image-header-vars.h index fa6e86d1c24..b4220e4936f 100644 --- a/arch/arm/cpu/armv8/linux-kernel-image-header-vars.h +++ b/arch/arm/cpu/armv8/linux-kernel-image-header-vars.h @@ -48,7 +48,7 @@ #define __MAX(a, b) (((a) > (b)) ? (a) : (b)) #define __CODE_DATA_SIZE (__bss_start - _start) #define __BSS_SIZE (__bss_end - __bss_start) -#ifdef CONFIG_SYS_INIT_SP_BSS_OFFSET +#ifdef CONFIG_INIT_SP_RELATIVE #define __MAX_EXTRA_RAM_USAGE __MAX(__BSS_SIZE, CONFIG_SYS_INIT_SP_BSS_OFFSET) #else #define __MAX_EXTRA_RAM_USAGE __BSS_SIZE diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index d6b632aa87d..e76b25a03e8 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -72,7 +72,7 @@ ENTRY(_main) ldr x0, =(CONFIG_TPL_STACK) #elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) ldr x0, =(CONFIG_SPL_STACK) -#elif defined(CONFIG_SYS_INIT_SP_BSS_OFFSET) +#elif defined(CONFIG_INIT_SP_RELATIVE) adr x0, __bss_start add x0, x0, #CONFIG_SYS_INIT_SP_BSS_OFFSET #else diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 97e22ead598..ff9f29f2d5d 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -86,6 +86,7 @@ config TEGRA_ARMV7_COMMON config TEGRA_ARMV8_COMMON bool "Tegra 64-bit common options" select ARM64 + select INIT_SP_RELATIVE select LINUX_KERNEL_IMAGE_HEADER select POSITION_INDEPENDENT select TEGRA_COMMON diff --git a/arch/arm/mach-tegra/tegra186/Kconfig b/arch/arm/mach-tegra/tegra186/Kconfig index 479c0955eec..b2e53b58caf 100644 --- a/arch/arm/mach-tegra/tegra186/Kconfig +++ b/arch/arm/mach-tegra/tegra186/Kconfig @@ -21,9 +21,6 @@ endchoice config SYS_SOC default "tegra186" -config SYS_INIT_SP_BSS_OFFSET - default 524288 - source "board/nvidia/p2771-0000/Kconfig" endif diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig index 250738aed31..3637473051b 100644 --- a/arch/arm/mach-tegra/tegra210/Kconfig +++ b/arch/arm/mach-tegra/tegra210/Kconfig @@ -40,9 +40,6 @@ endchoice config SYS_SOC default "tegra210" -config SYS_INIT_SP_BSS_OFFSET - default 524288 - source "board/nvidia/e2220-1170/Kconfig" source "board/nvidia/p2371-0000/Kconfig" source "board/nvidia/p2371-2180/Kconfig" -- cgit v1.2.3 From 92edfff6c63f08a29a5b5deb7b11121954a2f6b9 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 26 Jun 2019 13:51:47 +0900 Subject: ARM: uniphier_v8_defconfig: make 64bit SoC image position independent For a planned new SoC in this SoC family, the base address of the DRAM will be changed from 0x80000000 to 0x20000000. The PIE support will be useful to maintain multiple similar SoCs whose DRAM addresses differ. Now CONFIG_SYS_TEXT_BASE is not important. I just set it to 0 to ensure CONFIG_POSITION_INDEPENDENT is working. Signed-off-by: Masahiro Yamada --- configs/uniphier_v8_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig index 83f78776b7d..3908ff80d6b 100644 --- a/configs/uniphier_v8_defconfig +++ b/configs/uniphier_v8_defconfig @@ -1,7 +1,9 @@ CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_INIT_SP_RELATIVE=y CONFIG_ARM_SMCCC=y CONFIG_ARCH_UNIPHIER=y -CONFIG_SYS_TEXT_BASE=0x84000000 +CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ARCH_UNIPHIER_V8_MULTI=y -- cgit v1.2.3 From 9424ecd735e73af7d47ca18b705af3a90804c676 Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Fri, 5 Jul 2019 10:03:18 +0900 Subject: spi: Add SPI controller driver for UniPhier SoCs Add SPI controller driver implemented in Socionext UniPhier SoCs. This controller has the SPI master mode only. Signed-off-by: Kunihiko Hayashi --- drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/uniphier_spi.c | 413 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 422 insertions(+) create mode 100644 drivers/spi/uniphier_spi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index f9b282313a2..509dd0ec589 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -293,6 +293,14 @@ config TI_QSPI Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms. This driver support spi flash single, quad and memory reads. +config UNIPHIER_SPI + bool "Socionext UniPhier SPI driver" + depends on ARCH_UNIPHIER + help + Enable the Socionext UniPhier SPI driver. This driver can + be used to access SPI chips on platforms embedding this + UniPhier IP core. + config XILINX_SPI bool "Xilinx SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 64c407e2edd..ab84122f083 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o obj-$(CONFIG_TEGRA210_QSPI) += tegra210_qspi.o +obj-$(CONFIG_UNIPHIER_SPI) += uniphier_spi.o obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o diff --git a/drivers/spi/uniphier_spi.c b/drivers/spi/uniphier_spi.c new file mode 100644 index 00000000000..ef02d07aa46 --- /dev/null +++ b/drivers/spi/uniphier_spi.c @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * uniphier_spi.c - Socionext UniPhier SPI driver + * Copyright 2019 Socionext, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define SSI_CTL 0x00 +#define SSI_CTL_EN BIT(0) + +#define SSI_CKS 0x04 +#define SSI_CKS_CKRAT_MASK GENMASK(7, 0) +#define SSI_CKS_CKPHS BIT(14) +#define SSI_CKS_CKINIT BIT(13) +#define SSI_CKS_CKDLY BIT(12) + +#define SSI_TXWDS 0x08 +#define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8) +#define SSI_TXWDS_TDTF_MASK GENMASK(7, 6) +#define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0) + +#define SSI_RXWDS 0x0c +#define SSI_RXWDS_RDTF_MASK GENMASK(7, 6) +#define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0) + +#define SSI_FPS 0x10 +#define SSI_FPS_FSPOL BIT(15) +#define SSI_FPS_FSTRT BIT(14) + +#define SSI_SR 0x14 +#define SSI_SR_BUSY BIT(7) +#define SSI_SR_TNF BIT(5) +#define SSI_SR_RNE BIT(0) + +#define SSI_IE 0x18 + +#define SSI_IC 0x1c +#define SSI_IC_TCIC BIT(4) +#define SSI_IC_RCIC BIT(3) +#define SSI_IC_RORIC BIT(0) + +#define SSI_FC 0x20 +#define SSI_FC_TXFFL BIT(12) +#define SSI_FC_TXFTH_MASK GENMASK(11, 8) +#define SSI_FC_RXFFL BIT(4) +#define SSI_FC_RXFTH_MASK GENMASK(3, 0) + +#define SSI_XDR 0x24 /* TXDR for write, RXDR for read */ + +#define SSI_FIFO_DEPTH 8U + +#define SSI_REG_TIMEOUT (CONFIG_SYS_HZ / 100) /* 10 ms */ +#define SSI_XFER_TIMEOUT (CONFIG_SYS_HZ) /* 1 sec */ + +#define SSI_CLK 50000000 /* internal I/O clock: 50MHz */ + +struct uniphier_spi_platdata { + void __iomem *base; + u32 frequency; /* input frequency */ + u32 speed_hz; + uint deactivate_delay_us; /* Delay to wait after deactivate */ + uint activate_delay_us; /* Delay to wait after activate */ +}; + +struct uniphier_spi_priv { + void __iomem *base; + u8 mode; + u8 fifo_depth; + u8 bits_per_word; + ulong last_transaction_us; /* Time of last transaction end */ +}; + +static void uniphier_spi_enable(struct uniphier_spi_priv *priv, int enable) +{ + u32 val; + + val = readl(priv->base + SSI_CTL); + if (enable) + val |= SSI_CTL_EN; + else + val &= ~SSI_CTL_EN; + writel(val, priv->base + SSI_CTL); +} + +static void uniphier_spi_regdump(struct uniphier_spi_priv *priv) +{ + pr_debug("CTL %08x\n", readl(priv->base + SSI_CTL)); + pr_debug("CKS %08x\n", readl(priv->base + SSI_CKS)); + pr_debug("TXWDS %08x\n", readl(priv->base + SSI_TXWDS)); + pr_debug("RXWDS %08x\n", readl(priv->base + SSI_RXWDS)); + pr_debug("FPS %08x\n", readl(priv->base + SSI_FPS)); + pr_debug("SR %08x\n", readl(priv->base + SSI_SR)); + pr_debug("IE %08x\n", readl(priv->base + SSI_IE)); + pr_debug("IC %08x\n", readl(priv->base + SSI_IC)); + pr_debug("FC %08x\n", readl(priv->base + SSI_FC)); + pr_debug("XDR %08x\n", readl(priv->base + SSI_XDR)); +} + +static void spi_cs_activate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct uniphier_spi_platdata *plat = bus->platdata; + struct uniphier_spi_priv *priv = dev_get_priv(bus); + ulong delay_us; /* The delay completed so far */ + u32 val; + + /* If it's too soon to do another transaction, wait */ + if (plat->deactivate_delay_us && priv->last_transaction_us) { + delay_us = timer_get_us() - priv->last_transaction_us; + if (delay_us < plat->deactivate_delay_us) + udelay(plat->deactivate_delay_us - delay_us); + } + + val = readl(priv->base + SSI_FPS); + if (priv->mode & SPI_CS_HIGH) + val |= SSI_FPS_FSPOL; + else + val &= ~SSI_FPS_FSPOL; + writel(val, priv->base + SSI_FPS); + + if (plat->activate_delay_us) + udelay(plat->activate_delay_us); +} + +static void spi_cs_deactivate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct uniphier_spi_platdata *plat = bus->platdata; + struct uniphier_spi_priv *priv = dev_get_priv(bus); + u32 val; + + val = readl(priv->base + SSI_FPS); + if (priv->mode & SPI_CS_HIGH) + val &= ~SSI_FPS_FSPOL; + else + val |= SSI_FPS_FSPOL; + writel(val, priv->base + SSI_FPS); + + /* Remember time of this transaction so we can honour the bus delay */ + if (plat->deactivate_delay_us) + priv->last_transaction_us = timer_get_us(); +} + +static int uniphier_spi_claim_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct uniphier_spi_priv *priv = dev_get_priv(bus); + u32 val, size; + + uniphier_spi_enable(priv, false); + + /* disable interrupts */ + writel(0, priv->base + SSI_IE); + + /* bits_per_word */ + size = priv->bits_per_word; + val = readl(priv->base + SSI_TXWDS); + val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK); + val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size); + val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size); + writel(val, priv->base + SSI_TXWDS); + + val = readl(priv->base + SSI_RXWDS); + val &= ~SSI_RXWDS_DTLEN_MASK; + val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size); + writel(val, priv->base + SSI_RXWDS); + + /* reset FIFOs */ + val = SSI_FC_TXFFL | SSI_FC_RXFFL; + writel(val, priv->base + SSI_FC); + + /* FIFO threthold */ + val = readl(priv->base + SSI_FC); + val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK); + val |= FIELD_PREP(SSI_FC_TXFTH_MASK, priv->fifo_depth); + val |= FIELD_PREP(SSI_FC_RXFTH_MASK, priv->fifo_depth); + writel(val, priv->base + SSI_FC); + + /* clear interrupts */ + writel(SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC, + priv->base + SSI_IC); + + uniphier_spi_enable(priv, true); + + return 0; +} + +static int uniphier_spi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct uniphier_spi_priv *priv = dev_get_priv(bus); + + uniphier_spi_enable(priv, false); + + return 0; +} + +static int uniphier_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct uniphier_spi_priv *priv = dev_get_priv(bus); + const u8 *tx_buf = dout; + u8 *rx_buf = din, buf; + u32 len = bitlen / 8; + u32 tx_len, rx_len; + u32 ts, status; + int ret = 0; + + if (bitlen % 8) { + dev_err(dev, "Non byte aligned SPI transfer\n"); + return -EINVAL; + } + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(dev); + + uniphier_spi_enable(priv, true); + + ts = get_timer(0); + tx_len = len; + rx_len = len; + + uniphier_spi_regdump(priv); + + while (tx_len || rx_len) { + ret = wait_for_bit_le32(priv->base + SSI_SR, SSI_SR_BUSY, false, + SSI_REG_TIMEOUT * 1000, false); + if (ret) { + if (ret == -ETIMEDOUT) + dev_err(dev, "access timeout\n"); + break; + } + + status = readl(priv->base + SSI_SR); + /* write the data into TX */ + if (tx_len && (status & SSI_SR_TNF)) { + buf = tx_buf ? *tx_buf++ : 0; + writel(buf, priv->base + SSI_XDR); + tx_len--; + } + + /* read the data from RX */ + if (rx_len && (status & SSI_SR_RNE)) { + buf = readl(priv->base + SSI_XDR); + if (rx_buf) + *rx_buf++ = buf; + rx_len--; + } + + if (get_timer(ts) >= SSI_XFER_TIMEOUT) { + dev_err(dev, "transfer timeout\n"); + ret = -ETIMEDOUT; + break; + } + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(dev); + + uniphier_spi_enable(priv, false); + + return ret; +} + +static int uniphier_spi_set_speed(struct udevice *bus, uint speed) +{ + struct uniphier_spi_platdata *plat = bus->platdata; + struct uniphier_spi_priv *priv = dev_get_priv(bus); + u32 val, ckdiv; + + if (speed > plat->frequency) + speed = plat->frequency; + + /* baudrate */ + ckdiv = DIV_ROUND_UP(SSI_CLK, speed); + ckdiv = round_up(ckdiv, 2); + + val = readl(priv->base + SSI_CKS); + val &= ~SSI_CKS_CKRAT_MASK; + val |= ckdiv & SSI_CKS_CKRAT_MASK; + writel(val, priv->base + SSI_CKS); + + return 0; +} + +static int uniphier_spi_set_mode(struct udevice *bus, uint mode) +{ + struct uniphier_spi_priv *priv = dev_get_priv(bus); + u32 val1, val2; + + /* + * clock setting + * CKPHS capture timing. 0:rising edge, 1:falling edge + * CKINIT clock initial level. 0:low, 1:high + * CKDLY clock delay. 0:no delay, 1:delay depending on FSTRT + * (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock) + * + * frame setting + * FSPOL frame signal porarity. 0: low, 1: high + * FSTRT start frame timing + * 0: rising edge of clock, 1: falling edge of clock + */ + val1 = readl(priv->base + SSI_CKS); + val2 = readl(priv->base + SSI_FPS); + + switch (mode & (SPI_CPOL | SPI_CPHA)) { + case SPI_MODE_0: + /* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */ + val1 |= SSI_CKS_CKPHS | SSI_CKS_CKDLY; + val1 &= ~SSI_CKS_CKINIT; + val2 &= ~SSI_FPS_FSTRT; + break; + case SPI_MODE_1: + /* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */ + val1 &= ~(SSI_CKS_CKPHS | SSI_CKS_CKINIT | SSI_CKS_CKDLY); + val2 |= SSI_FPS_FSTRT; + break; + case SPI_MODE_2: + /* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */ + val1 |= SSI_CKS_CKINIT | SSI_CKS_CKDLY; + val1 &= ~SSI_CKS_CKPHS; + val2 |= SSI_FPS_FSTRT; + break; + case SPI_MODE_3: + /* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */ + val1 |= SSI_CKS_CKPHS | SSI_CKS_CKINIT; + val1 &= ~SSI_CKS_CKDLY; + val2 &= ~SSI_FPS_FSTRT; + break; + } + + writel(val1, priv->base + SSI_CKS); + writel(val2, priv->base + SSI_FPS); + + /* format */ + val1 = readl(priv->base + SSI_TXWDS); + val2 = readl(priv->base + SSI_RXWDS); + if (mode & SPI_LSB_FIRST) { + val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1); + val2 |= FIELD_PREP(SSI_RXWDS_RDTF_MASK, 1); + } + writel(val1, priv->base + SSI_TXWDS); + writel(val2, priv->base + SSI_RXWDS); + + priv->mode = mode; + + return 0; +} + +static int uniphier_spi_ofdata_to_platdata(struct udevice *bus) +{ + struct uniphier_spi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = dev_of_offset(bus); + + plat->base = devfdt_get_addr_ptr(bus); + + plat->frequency = + fdtdec_get_int(blob, node, "spi-max-frequency", 12500000); + plat->deactivate_delay_us = + fdtdec_get_int(blob, node, "spi-deactivate-delay", 0); + plat->activate_delay_us = + fdtdec_get_int(blob, node, "spi-activate-delay", 0); + plat->speed_hz = plat->frequency / 2; + + return 0; +} + +static int uniphier_spi_probe(struct udevice *bus) +{ + struct uniphier_spi_platdata *plat = dev_get_platdata(bus); + struct uniphier_spi_priv *priv = dev_get_priv(bus); + + priv->base = plat->base; + priv->fifo_depth = SSI_FIFO_DEPTH; + priv->bits_per_word = 8; + + return 0; +} + +static const struct dm_spi_ops uniphier_spi_ops = { + .claim_bus = uniphier_spi_claim_bus, + .release_bus = uniphier_spi_release_bus, + .xfer = uniphier_spi_xfer, + .set_speed = uniphier_spi_set_speed, + .set_mode = uniphier_spi_set_mode, +}; + +static const struct udevice_id uniphier_spi_ids[] = { + { .compatible = "socionext,uniphier-scssi" }, + { /* Sentinel */ } +}; + +U_BOOT_DRIVER(uniphier_spi) = { + .name = "uniphier_spi", + .id = UCLASS_SPI, + .of_match = uniphier_spi_ids, + .ops = &uniphier_spi_ops, + .ofdata_to_platdata = uniphier_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct uniphier_spi_platdata), + .priv_auto_alloc_size = sizeof(struct uniphier_spi_priv), + .probe = uniphier_spi_probe, +}; -- cgit v1.2.3 From 47eb8add270419722a562acd7e78088eddcf9488 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:29 +0900 Subject: arm64: dts: uniphier: add reserved-memory for secure memory [ Linux commit aa38571246c6ac279ebebd141157297bcb959d76 ] The memory regions specified by /memreserve/ are passed to early_init_dt_reserve_memory_arch() with nomap=false, so it is not suitable for reserving memory for Trusted Firmware-A etc. Use the more robust /reserved-memory node with the no-map property to prevent the kernel from mapping it. Signed-off-by: Masahiro Yamada --- arch/arm/dts/uniphier-ld11.dtsi | 13 +++++++++++-- arch/arm/dts/uniphier-ld20.dtsi | 13 +++++++++++-- arch/arm/dts/uniphier-pxs3.dtsi | 13 +++++++++++-- 3 files changed, 33 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi index a3cd475b48d..337a3537ed2 100644 --- a/arch/arm/dts/uniphier-ld11.dtsi +++ b/arch/arm/dts/uniphier-ld11.dtsi @@ -8,8 +8,6 @@ #include #include -/memreserve/ 0x80000000 0x02000000; - / { compatible = "socionext,uniphier-ld11"; #address-cells = <2>; @@ -110,6 +108,17 @@ <1 10 4>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure-memory@81000000 { + reg = <0x0 0x81000000 0x0 0x01000000>; + no-map; + }; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi index baf23268366..3721110b17a 100644 --- a/arch/arm/dts/uniphier-ld20.dtsi +++ b/arch/arm/dts/uniphier-ld20.dtsi @@ -9,8 +9,6 @@ #include #include -/memreserve/ 0x80000000 0x02000000; - / { compatible = "socionext,uniphier-ld20"; #address-cells = <2>; @@ -215,6 +213,17 @@ }; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure-memory@81000000 { + reg = <0x0 0x81000000 0x0 0x01000000>; + no-map; + }; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi index 961d4d3621f..b1aff285c8b 100644 --- a/arch/arm/dts/uniphier-pxs3.dtsi +++ b/arch/arm/dts/uniphier-pxs3.dtsi @@ -8,8 +8,6 @@ #include #include -/memreserve/ 0x80000000 0x02000000; - / { compatible = "socionext,uniphier-pxs3"; #address-cells = <2>; @@ -138,6 +136,17 @@ <1 10 4>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure-memory@81000000 { + reg = <0x0 0x81000000 0x0 0x01000000>; + no-map; + }; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; -- cgit v1.2.3 From 7f283213a6959ee1312dc9f6c35f2b5c77594cb4 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:30 +0900 Subject: ARM: uniphier: remove empty #ifdef block This is a remnant of commit f89d6133eef2 ("configs: move CONFIG_SPL_TEXT_BASE to Kconfig"). Signed-off-by: Masahiro Yamada --- include/configs/uniphier.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 5b42e0c1dee..6979165260c 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -220,10 +220,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) /* only for SPL */ -#if defined(CONFIG_ARCH_UNIPHIER_LD4) || \ - defined(CONFIG_ARCH_UNIPHIER_SLD8) -#endif - #define CONFIG_SPL_STACK (0x00200000) #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 -- cgit v1.2.3 From 40c1a466ced81274e4abf8fd51c77f804dff6751 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:31 +0900 Subject: ARM: uniphier: remove unused uniphier_ld11_boot_device_fixup() The .boot_device_fixup() is only called by SPL. Now that 64-bit SoCs of this SoC family no longer support SPL, debug-uart-ld20.c is never compiled. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/boot-device/boot-device-ld11.c | 8 -------- arch/arm/mach-uniphier/boot-device/boot-device.c | 2 -- arch/arm/mach-uniphier/boot-device/boot-device.h | 1 - 3 files changed, 11 deletions(-) diff --git a/arch/arm/mach-uniphier/boot-device/boot-device-ld11.c b/arch/arm/mach-uniphier/boot-device/boot-device-ld11.c index 10093be0e43..11e70a926fc 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device-ld11.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device-ld11.c @@ -58,11 +58,3 @@ int uniphier_ld20_boot_device_is_usb(u32 pinmon) { return !!(~pinmon & 0x00000780); } - -unsigned int uniphier_ld11_boot_device_fixup(unsigned int mode) -{ - if (mode == BOOT_DEVICE_MMC1 || mode == BOOT_DEVICE_USB) - mode = BOOT_DEVICE_BOARD; - - return mode; -} diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c index 23be8cfcf00..3c7643302d9 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device.c @@ -91,7 +91,6 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_table = uniphier_ld11_boot_device_table, .boot_device_count = &uniphier_ld11_boot_device_count, .boot_device_is_usb = uniphier_ld11_boot_device_is_usb, - .boot_device_fixup = uniphier_ld11_boot_device_fixup, .have_internal_stm = 1, }, #endif @@ -102,7 +101,6 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_table = uniphier_ld11_boot_device_table, .boot_device_count = &uniphier_ld11_boot_device_count, .boot_device_is_usb = uniphier_ld20_boot_device_is_usb, - .boot_device_fixup = uniphier_ld11_boot_device_fixup, .have_internal_stm = 1, }, #endif diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.h b/arch/arm/mach-uniphier/boot-device/boot-device.h index 44579f17d3e..bbb634316b3 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.h +++ b/arch/arm/mach-uniphier/boot-device/boot-device.h @@ -30,6 +30,5 @@ int uniphier_ld20_boot_device_is_usb(u32 pinmon); int uniphier_pxs3_boot_device_is_usb(u32 pinmon); unsigned int uniphier_pxs2_boot_device_fixup(unsigned int mode); -unsigned int uniphier_ld11_boot_device_fixup(unsigned int mode); #endif /* _UNIPHIER_BOOT_DEVICE_H_ */ -- cgit v1.2.3 From a179669c4ea8f7b4942eb3c4d306ce2e7947ffaa Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:32 +0900 Subject: ARM: uniphier: clean up clk/Makefile Now that 64-bit SoCs of this SoC family no longer support SPL, this Makefile can be slightly simpler. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/Makefile | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index 3d741b4c4d1..d12f49e5230 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -17,12 +17,8 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o pll-ld4.o dpll-tail.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o -obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o pll-ld11.o -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-ld20.o -obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += clk-pxs3.o pll-pxs3.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o pll-base-ld20.o pll-ld11.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-base-ld20.o pll-ld20.o +obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += clk-pxs3.o pll-base-ld20.o pll-pxs3.o endif - -obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pll-base-ld20.o -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-base-ld20.o -obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += pll-base-ld20.o -- cgit v1.2.3 From ef866f6f480720c3507145d02fa1e84d7d1bb9b3 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:33 +0900 Subject: ARM: uniphier: use bool type for have_internal_stm parameter This is boolean logic. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/boot-device/boot-device.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c index 3c7643302d9..c8339dbe1ba 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device.c @@ -22,7 +22,7 @@ struct uniphier_boot_device_info { const unsigned int *boot_device_count; int (*boot_device_is_usb)(u32 pinmon); unsigned int (*boot_device_fixup)(unsigned int mode); - int have_internal_stm; + bool have_internal_stm; }; static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { @@ -32,7 +32,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_sel_shift = 1, .boot_device_table = uniphier_ld4_boot_device_table, .boot_device_count = &uniphier_ld4_boot_device_count, - .have_internal_stm = 1, + .have_internal_stm = true, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO4) @@ -41,7 +41,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_sel_shift = 1, .boot_device_table = uniphier_ld4_boot_device_table, .boot_device_count = &uniphier_ld4_boot_device_count, - .have_internal_stm = 0, + .have_internal_stm = false, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_SLD8) @@ -50,7 +50,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_sel_shift = 1, .boot_device_table = uniphier_ld4_boot_device_table, .boot_device_count = &uniphier_ld4_boot_device_count, - .have_internal_stm = 1, + .have_internal_stm = true, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO5) @@ -59,7 +59,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_sel_shift = 1, .boot_device_table = uniphier_pro5_boot_device_table, .boot_device_count = &uniphier_pro5_boot_device_count, - .have_internal_stm = 0, + .have_internal_stm = false, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PXS2) @@ -70,7 +70,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_count = &uniphier_pxs2_boot_device_count, .boot_device_is_usb = uniphier_pxs2_boot_device_is_usb, .boot_device_fixup = uniphier_pxs2_boot_device_fixup, - .have_internal_stm = 0, + .have_internal_stm = false, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD6B) @@ -81,7 +81,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_count = &uniphier_pxs2_boot_device_count, .boot_device_is_usb = uniphier_pxs2_boot_device_is_usb, .boot_device_fixup = uniphier_pxs2_boot_device_fixup, - .have_internal_stm = 1, /* STM on A-chip */ + .have_internal_stm = true, /* STM on A-chip */ }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD11) @@ -91,7 +91,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_table = uniphier_ld11_boot_device_table, .boot_device_count = &uniphier_ld11_boot_device_count, .boot_device_is_usb = uniphier_ld11_boot_device_is_usb, - .have_internal_stm = 1, + .have_internal_stm = true, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD20) @@ -101,7 +101,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_table = uniphier_ld11_boot_device_table, .boot_device_count = &uniphier_ld11_boot_device_count, .boot_device_is_usb = uniphier_ld20_boot_device_is_usb, - .have_internal_stm = 1, + .have_internal_stm = true, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PXS3) @@ -111,7 +111,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_table = uniphier_pxs3_boot_device_table, .boot_device_count = &uniphier_pxs3_boot_device_count, .boot_device_is_usb = uniphier_pxs3_boot_device_is_usb, - .have_internal_stm = 0, + .have_internal_stm = false, }, #endif }; -- cgit v1.2.3 From b521ea395803732784227bac1b6bad452db896d6 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:34 +0900 Subject: ARM: uniphier: include from boot-device.c This file calls readl(), so needs to include . Currently, it relies on someone else including it. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/boot-device/boot-device.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c index c8339dbe1ba..59302150b89 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include "../init.h" -- cgit v1.2.3 From 9a2f0e5ccd8749e9cdb27c4f4edf07dd44ff36b7 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:35 +0900 Subject: clk: uniphier: add EMMC clock for LD11, LD20, and PXs3 I also added comments for NAND clocks. Signed-off-by: Masahiro Yamada --- drivers/clk/uniphier/clk-uniphier-sys.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index 487b43ebdab..c627a4bf851 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -18,8 +18,8 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_SLD8) ||\ defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\ defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B) - UNIPHIER_LD4_SYS_CLK_NAND(2), - UNIPHIER_CLK_RATE(3, 200000000), + UNIPHIER_LD4_SYS_CLK_NAND(2), /* nand */ + UNIPHIER_CLK_RATE(3, 200000000), /* nand-4x */ UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */ UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */ UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */ @@ -35,8 +35,9 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) - UNIPHIER_LD11_SYS_CLK_NAND(2), - UNIPHIER_CLK_RATE(3, 200000000), + UNIPHIER_LD11_SYS_CLK_NAND(2), /* nand */ + UNIPHIER_CLK_RATE(3, 200000000), /* nand-4x */ + UNIPHIER_CLK_GATE_SIMPLE(4, 0x210c, 2), /* emmc */ UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */ UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */ UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */ @@ -48,8 +49,9 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_PXS3) - UNIPHIER_LD11_SYS_CLK_NAND(2), - UNIPHIER_CLK_RATE(3, 200000000), + UNIPHIER_LD11_SYS_CLK_NAND(2), /* nand */ + UNIPHIER_CLK_RATE(3, 200000000), /* nand-4x */ + UNIPHIER_CLK_GATE_SIMPLE(4, 0x210c, 2), /* emmc */ UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */ UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */ UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */ -- cgit v1.2.3 From 92d6524b4f19cac08dd47f656bce59a7db6d3c47 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:36 +0900 Subject: ARM: uniphier: check DT to determine whether to use support card If CONFIG_MICRO_SUPPORT_CARD is enabled, U-Boot tries to get access to the devices on the support card, which may not actually exist. Check the DT and search for the on-board devices run-time. If the nodes are not found in DT, then disable the code. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/micro-support-card.c | 33 +++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/mach-uniphier/micro-support-card.c b/arch/arm/mach-uniphier/micro-support-card.c index 1be5685c6fb..46879019fda 100644 --- a/arch/arm/mach-uniphier/micro-support-card.c +++ b/arch/arm/mach-uniphier/micro-support-card.c @@ -18,6 +18,25 @@ #define MICRO_SUPPORT_CARD_RESET ((MICRO_SUPPORT_CARD_BASE) + 0xd0034) #define MICRO_SUPPORT_CARD_REVISION ((MICRO_SUPPORT_CARD_BASE) + 0xd00E0) +static bool support_card_found; + +static void support_card_detect(void) +{ + DECLARE_GLOBAL_DATA_PTR; + const void *fdt = gd->fdt_blob; + int offset; + + offset = fdt_node_offset_by_compatible(fdt, 0, "smsc,lan9118"); + if (offset < 0) + return; + + offset = fdt_node_offset_by_compatible(fdt, 0, "ns16550a"); + if (offset < 0) + return; + + support_card_found = true; +} + /* * 0: reset deassert, 1: reset * @@ -51,6 +70,11 @@ static int support_card_show_revision(void) void support_card_init(void) { + support_card_detect(); + + if (!support_card_found) + return; + support_card_reset(); /* * After power on, we need to keep the LAN controller in reset state @@ -67,6 +91,9 @@ void support_card_init(void) int board_eth_init(bd_t *bis) { + if (!support_card_found) + return 0; + return smc911x_initialize(0, SMC911X_BASE); } #endif @@ -161,6 +188,9 @@ static void detect_num_flash_banks(void) void support_card_late_init(void) { + if (!support_card_found) + return; + detect_num_flash_banks(); } @@ -221,6 +251,9 @@ void led_puts(const char *s) int i; u32 val = 0; + if (!support_card_found) + return; + if (!s) return; -- cgit v1.2.3 From f7f390576d063f9fc6c2a00792acd835a75c88aa Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:37 +0900 Subject: ARM: uniphier: check DT to determine whether to initialize SBC If CONFIG_MICRO_SUPPORT_CARD is enabled, U-Boot initialize SBC (System Bus Controller), which may not be really necessary. Check the "socionext,uniphier-system-bus" node in DT run-time. If and only if it is found and its "status" property is okay, initialize the SBC block. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/Makefile | 3 ++- arch/arm/mach-uniphier/sbc/Makefile | 4 ++++ arch/arm/mach-uniphier/sbc/sbc-ld11.c | 3 +++ arch/arm/mach-uniphier/sbc/sbc-ld4.c | 3 +++ arch/arm/mach-uniphier/sbc/sbc-pxs2.c | 3 +++ arch/arm/mach-uniphier/sbc/sbc-regs.h | 2 ++ arch/arm/mach-uniphier/sbc/sbc.c | 16 ++++++++++++++++ 7 files changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index d0c39d42737..caa79d1e53e 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -18,13 +18,14 @@ ifndef CONFIG_SYSRESET obj-y += reset.o endif -obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/ micro-support-card.o +obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o obj-y += pinctrl-glue.o obj-$(CONFIG_MMC) += mmc-first-dev.o obj-y += fdt-fixup.o endif +obj-y += sbc/ obj-y += soc-info.o obj-y += boot-device/ obj-y += clk/ diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile index 912e05a725d..4efdd419f04 100644 --- a/arch/arm/mach-uniphier/sbc/Makefile +++ b/arch/arm/mach-uniphier/sbc/Makefile @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0+ +obj- += dummy.o + +ifndef CONFIG_SPL_BUILD obj-y += sbc.o obj-$(CONFIG_ARCH_UNIPHIER_LD4) += sbc-ld4.o @@ -9,3 +12,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD11) += sbc-ld11.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-ld11.o obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += sbc-pxs2.o +endif diff --git a/arch/arm/mach-uniphier/sbc/sbc-ld11.c b/arch/arm/mach-uniphier/sbc/sbc-ld11.c index 44d8a1e3bd9..21972ac9494 100644 --- a/arch/arm/mach-uniphier/sbc/sbc-ld11.c +++ b/arch/arm/mach-uniphier/sbc/sbc-ld11.c @@ -12,6 +12,9 @@ void uniphier_ld11_sbc_init(void) { + if (!uniphier_sbc_is_enabled()) + return; + uniphier_sbc_init_savepin(); /* necessary for ROM boot ?? */ diff --git a/arch/arm/mach-uniphier/sbc/sbc-ld4.c b/arch/arm/mach-uniphier/sbc/sbc-ld4.c index d08b571e23c..72e9743c8f8 100644 --- a/arch/arm/mach-uniphier/sbc/sbc-ld4.c +++ b/arch/arm/mach-uniphier/sbc/sbc-ld4.c @@ -13,6 +13,9 @@ void uniphier_ld4_sbc_init(void) { u32 tmp; + if (!uniphier_sbc_is_enabled()) + return; + uniphier_sbc_init_savepin(); /* system bus output enable */ diff --git a/arch/arm/mach-uniphier/sbc/sbc-pxs2.c b/arch/arm/mach-uniphier/sbc/sbc-pxs2.c index 8c167ef0698..3275f22ce96 100644 --- a/arch/arm/mach-uniphier/sbc/sbc-pxs2.c +++ b/arch/arm/mach-uniphier/sbc/sbc-pxs2.c @@ -10,6 +10,9 @@ void uniphier_pxs2_sbc_init(void) { + if (!uniphier_sbc_is_enabled()) + return; + uniphier_sbc_init_savepin(); /* necessary for ROM boot ?? */ diff --git a/arch/arm/mach-uniphier/sbc/sbc-regs.h b/arch/arm/mach-uniphier/sbc/sbc-regs.h index 853015acbca..e866816472b 100644 --- a/arch/arm/mach-uniphier/sbc/sbc-regs.h +++ b/arch/arm/mach-uniphier/sbc/sbc-regs.h @@ -84,4 +84,6 @@ static inline int boot_is_swapped(void) } #endif +int uniphier_sbc_is_enabled(void); + #endif /* ARCH_SBC_REGS_H */ diff --git a/arch/arm/mach-uniphier/sbc/sbc.c b/arch/arm/mach-uniphier/sbc/sbc.c index df01e5c01d5..6cf8cf2af80 100644 --- a/arch/arm/mach-uniphier/sbc/sbc.c +++ b/arch/arm/mach-uniphier/sbc/sbc.c @@ -5,7 +5,9 @@ * Author: Masahiro Yamada */ +#include #include +#include #include "../init.h" #include "sbc-regs.h" @@ -31,6 +33,20 @@ #define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009 #define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210 +int uniphier_sbc_is_enabled(void) +{ + DECLARE_GLOBAL_DATA_PTR; + const void *fdt = gd->fdt_blob; + int offset; + + offset = fdt_node_offset_by_compatible(fdt, 0, + "socionext,uniphier-system-bus"); + if (offset < 0) + return 0; + + return fdtdec_get_is_enabled(fdt, offset); +} + static void __uniphier_sbc_init(int savepin) { /* -- cgit v1.2.3 From 539d6e0dbc9634cbf0e14a383d2907e6e462558a Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:38 +0900 Subject: ARM: uniphier: make boot_is_swapped() code optional The planned new SoC does not have SBC (System Bus Controller) block. Make boot_is_swapped() an optional hook. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/boot-device/boot-device.c | 16 ++++++++++++++-- arch/arm/mach-uniphier/sbc/Makefile | 2 +- arch/arm/mach-uniphier/sbc/sbc-boot.c | 13 +++++++++++++ arch/arm/mach-uniphier/sbc/sbc-regs.h | 9 +-------- arch/arm/mach-uniphier/sbc/sbc.c | 2 +- 5 files changed, 30 insertions(+), 12 deletions(-) create mode 100644 arch/arm/mach-uniphier/sbc/sbc-boot.c diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c index 59302150b89..3c2e7b660f3 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device.c @@ -23,6 +23,7 @@ struct uniphier_boot_device_info { const unsigned int *boot_device_count; int (*boot_device_is_usb)(u32 pinmon); unsigned int (*boot_device_fixup)(unsigned int mode); + int (*boot_is_swapped)(void); bool have_internal_stm; }; @@ -33,6 +34,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_sel_shift = 1, .boot_device_table = uniphier_ld4_boot_device_table, .boot_device_count = &uniphier_ld4_boot_device_count, + .boot_is_swapped = uniphier_sbc_boot_is_swapped, .have_internal_stm = true, }, #endif @@ -42,6 +44,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_sel_shift = 1, .boot_device_table = uniphier_ld4_boot_device_table, .boot_device_count = &uniphier_ld4_boot_device_count, + .boot_is_swapped = uniphier_sbc_boot_is_swapped, .have_internal_stm = false, }, #endif @@ -51,6 +54,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_sel_shift = 1, .boot_device_table = uniphier_ld4_boot_device_table, .boot_device_count = &uniphier_ld4_boot_device_count, + .boot_is_swapped = uniphier_sbc_boot_is_swapped, .have_internal_stm = true, }, #endif @@ -60,6 +64,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_sel_shift = 1, .boot_device_table = uniphier_pro5_boot_device_table, .boot_device_count = &uniphier_pro5_boot_device_count, + .boot_is_swapped = uniphier_sbc_boot_is_swapped, .have_internal_stm = false, }, #endif @@ -71,6 +76,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_count = &uniphier_pxs2_boot_device_count, .boot_device_is_usb = uniphier_pxs2_boot_device_is_usb, .boot_device_fixup = uniphier_pxs2_boot_device_fixup, + .boot_is_swapped = uniphier_sbc_boot_is_swapped, .have_internal_stm = false, }, #endif @@ -82,6 +88,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_count = &uniphier_pxs2_boot_device_count, .boot_device_is_usb = uniphier_pxs2_boot_device_is_usb, .boot_device_fixup = uniphier_pxs2_boot_device_fixup, + .boot_is_swapped = uniphier_sbc_boot_is_swapped, .have_internal_stm = true, /* STM on A-chip */ }, #endif @@ -92,6 +99,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_table = uniphier_ld11_boot_device_table, .boot_device_count = &uniphier_ld11_boot_device_count, .boot_device_is_usb = uniphier_ld11_boot_device_is_usb, + .boot_is_swapped = uniphier_sbc_boot_is_swapped, .have_internal_stm = true, }, #endif @@ -102,6 +110,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_table = uniphier_ld11_boot_device_table, .boot_device_count = &uniphier_ld11_boot_device_count, .boot_device_is_usb = uniphier_ld20_boot_device_is_usb, + .boot_is_swapped = uniphier_sbc_boot_is_swapped, .have_internal_stm = true, }, #endif @@ -112,6 +121,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_table = uniphier_pxs3_boot_device_table, .boot_device_count = &uniphier_pxs3_boot_device_count, .boot_device_is_usb = uniphier_pxs3_boot_device_is_usb, + .boot_is_swapped = uniphier_sbc_boot_is_swapped, .have_internal_stm = false, }, #endif @@ -125,7 +135,7 @@ static unsigned int __uniphier_boot_device_raw( u32 pinmon; unsigned int boot_sel; - if (boot_is_swapped()) + if (info->boot_is_swapped && info->boot_is_swapped()) return BOOT_DEVICE_NOR; pinmon = readl(SG_PINMON0); @@ -208,7 +218,9 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("STB Micon: %s\n", uniphier_boot_from_backend() ? "OFF" : "ON"); - printf("Boot Swap: %s\n", boot_is_swapped() ? "ON" : "OFF"); + if (info->boot_is_swapped) + printf("Boot Swap: %s\n", + info->boot_is_swapped() ? "ON" : "OFF"); pinmon = readl(SG_PINMON0); diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile index 4efdd419f04..6c698a39225 100644 --- a/arch/arm/mach-uniphier/sbc/Makefile +++ b/arch/arm/mach-uniphier/sbc/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -obj- += dummy.o +obj-y += sbc-boot.o ifndef CONFIG_SPL_BUILD obj-y += sbc.o diff --git a/arch/arm/mach-uniphier/sbc/sbc-boot.c b/arch/arm/mach-uniphier/sbc/sbc-boot.c new file mode 100644 index 00000000000..ec22b453e0f --- /dev/null +++ b/arch/arm/mach-uniphier/sbc/sbc-boot.c @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2011-2014 Panasonic Corporation +// Copyright (C) 2015-2019 Socionext Inc. + +#include + +#include "sbc-regs.h" + +int uniphier_sbc_boot_is_swapped(void) +{ + return !(readl(SBBASE0) & SBBASE_BANK_ENABLE); +} diff --git a/arch/arm/mach-uniphier/sbc/sbc-regs.h b/arch/arm/mach-uniphier/sbc/sbc-regs.h index e866816472b..1e9618653f2 100644 --- a/arch/arm/mach-uniphier/sbc/sbc-regs.h +++ b/arch/arm/mach-uniphier/sbc/sbc-regs.h @@ -76,14 +76,7 @@ #define PC0CTRL 0x598000c0 -#ifndef __ASSEMBLY__ -#include -static inline int boot_is_swapped(void) -{ - return !(readl(SBBASE0) & SBBASE_BANK_ENABLE); -} -#endif - +int uniphier_sbc_boot_is_swapped(void); int uniphier_sbc_is_enabled(void); #endif /* ARCH_SBC_REGS_H */ diff --git a/arch/arm/mach-uniphier/sbc/sbc.c b/arch/arm/mach-uniphier/sbc/sbc.c index 6cf8cf2af80..af8d6f4f9dc 100644 --- a/arch/arm/mach-uniphier/sbc/sbc.c +++ b/arch/arm/mach-uniphier/sbc/sbc.c @@ -64,7 +64,7 @@ static void __uniphier_sbc_init(int savepin) writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12); } - if (boot_is_swapped()) { + if (uniphier_sbc_boot_is_swapped()) { /* * Boot Swap On: boot from external NOR/SRAM * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. -- cgit v1.2.3 From c3d8f1e8e92fd70abb912942300cf44fff9e9d86 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:39 +0900 Subject: ARM: uniphier: detect SD boot mode The planned new SoC supports the SD boot mode. Detect and display it. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/board_late_init.c | 4 ++++ arch/arm/mach-uniphier/boot-device/boot-device.c | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index 972dbe8ae55..86b128a91f9 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -68,6 +68,10 @@ int board_late_init(void) printf("eMMC Boot"); env_set("bootdev", "emmc"); break; + case BOOT_DEVICE_MMC2: + printf("SD Boot"); + env_set("bootdev", "sd"); + break; case BOOT_DEVICE_NAND: printf("NAND Boot"); env_set("bootdev", "nand"); diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c index 3c2e7b660f3..c9dfe13ed9c 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device.c @@ -21,6 +21,7 @@ struct uniphier_boot_device_info { unsigned int boot_device_sel_shift; const struct uniphier_boot_device *boot_device_table; const unsigned int *boot_device_count; + int (*boot_device_is_sd)(u32 pinmon); int (*boot_device_is_usb)(u32 pinmon); unsigned int (*boot_device_fixup)(unsigned int mode); int (*boot_is_swapped)(void); @@ -140,6 +141,9 @@ static unsigned int __uniphier_boot_device_raw( pinmon = readl(SG_PINMON0); + if (info->boot_device_is_sd && info->boot_device_is_sd(pinmon)) + return BOOT_DEVICE_MMC2; + if (info->boot_device_is_usb && info->boot_device_is_usb(pinmon)) return BOOT_DEVICE_USB; @@ -224,6 +228,10 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) pinmon = readl(SG_PINMON0); + if (info->boot_device_is_sd) + printf("SD Boot: %s\n", + info->boot_device_is_sd(pinmon) ? "ON" : "OFF"); + if (info->boot_device_is_usb) printf("USB Boot: %s\n", info->boot_device_is_usb(pinmon) ? "ON" : "OFF"); -- cgit v1.2.3 From d41b358fb331c2907f1f217686d38eeaf17eece4 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:40 +0900 Subject: ARM: uniphier: de-couple SG macros into base address and offset The SG_* macros represent the address of SoC-glue registers. For a planned new SoC, its base address will be changed. Turn the SG_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/arm32/debug_ll.S | 16 ++++++------- .../mach-uniphier/boot-device/boot-device-pxs3.c | 2 +- arch/arm/mach-uniphier/boot-device/boot-device.c | 6 ++--- arch/arm/mach-uniphier/clk/clk-ld11.c | 14 +++++------ arch/arm/mach-uniphier/clk/pll-ld4.c | 4 ++-- arch/arm/mach-uniphier/clk/pll-pro4.c | 2 +- .../arm/mach-uniphier/debug-uart/debug-uart-pro4.c | 2 +- .../arm/mach-uniphier/debug-uart/debug-uart-pro5.c | 2 +- arch/arm/mach-uniphier/debug-uart/debug-uart.c | 5 ++-- arch/arm/mach-uniphier/dram_init.c | 2 +- arch/arm/mach-uniphier/memconf.c | 2 +- arch/arm/mach-uniphier/sg-regs.h | 28 ++++++++++++---------- arch/arm/mach-uniphier/soc-info.c | 2 +- 13 files changed, 46 insertions(+), 41 deletions(-) diff --git a/arch/arm/mach-uniphier/arm32/debug_ll.S b/arch/arm/mach-uniphier/arm32/debug_ll.S index e56e1f679ca..c155246ae8c 100644 --- a/arch/arm/mach-uniphier/arm32/debug_ll.S +++ b/arch/arm/mach-uniphier/arm32/debug_ll.S @@ -22,7 +22,7 @@ #define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d)) .macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd - ldr \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride) + ldr \ra, =(SG_BASE + SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride) ldr \rd, [\ra] and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32)) orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32)) @@ -30,7 +30,7 @@ .endm ENTRY(debug_ll_init) - ldr r0, =SG_REVISION + ldr r0, =(SG_BASE + SG_REVISION) ldr r1, [r0] and r1, r1, #SG_REVISION_TYPE_MASK mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT @@ -40,7 +40,7 @@ ENTRY(debug_ll_init) cmp r1, #0x26 bne ld4_end - ldr r0, =SG_IECTRL + ldr r0, =(SG_BASE + SG_IECTRL) ldr r1, [r0] orr r1, r1, #1 str r1, [r0] @@ -59,7 +59,7 @@ ld4_end: sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0 - ldr r0, =SG_LOADPINCTRL + ldr r0, =(SG_BASE + SG_LOADPINCTRL) mov r1, #1 str r1, [r0] @@ -78,7 +78,7 @@ pro4_end: cmp r1, #0x29 bne sld8_end - ldr r0, =SG_IECTRL + ldr r0, =(SG_BASE + SG_IECTRL) ldr r1, [r0] orr r1, r1, #1 str r1, [r0] @@ -100,7 +100,7 @@ sld8_end: sg_set_pinsel 51, 0, 4, 8, r0, r1 @ TXD2 -> TXD2 sg_set_pinsel 53, 0, 4, 8, r0, r1 @ TXD3 -> TXD3 - ldr r0, =SG_LOADPINCTRL + ldr r0, =(SG_BASE + SG_LOADPINCTRL) mov r1, #1 str r1, [r0] @@ -119,7 +119,7 @@ pro5_end: cmp r1, #0x2E bne pxs2_end - ldr r0, =SG_IECTRL + ldr r0, =(SG_BASE + SG_IECTRL) ldr r1, [r0] orr r1, r1, #1 str r1, [r0] @@ -144,7 +144,7 @@ pxs2_end: cmp r1, #0x2F bne ld6b_end - ldr r0, =SG_IECTRL + ldr r0, =(SG_BASE + SG_IECTRL) ldr r1, [r0] orr r1, r1, #1 str r1, [r0] diff --git a/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c b/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c index 01a72c03505..2edf66d5c10 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c @@ -36,5 +36,5 @@ const unsigned uniphier_pxs3_boot_device_count = int uniphier_pxs3_boot_device_is_usb(u32 pinmon) { - return !!(readl(SG_PINMON2) & BIT(31)); + return !!(readl(sg_base + SG_PINMON2) & BIT(31)); } diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c index c9dfe13ed9c..83f8c6a428c 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device.c @@ -139,7 +139,7 @@ static unsigned int __uniphier_boot_device_raw( if (info->boot_is_swapped && info->boot_is_swapped()) return BOOT_DEVICE_NOR; - pinmon = readl(SG_PINMON0); + pinmon = readl(sg_base + SG_PINMON0); if (info->boot_device_is_sd && info->boot_device_is_sd(pinmon)) return BOOT_DEVICE_MMC2; @@ -200,7 +200,7 @@ int uniphier_have_internal_stm(void) int uniphier_boot_from_backend(void) { - return !!(readl(SG_PINMON0) & BIT(27)); + return !!(readl(sg_base + SG_PINMON0) & BIT(27)); } #ifndef CONFIG_SPL_BUILD @@ -226,7 +226,7 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("Boot Swap: %s\n", info->boot_is_swapped() ? "ON" : "OFF"); - pinmon = readl(SG_PINMON0); + pinmon = readl(sg_base + SG_PINMON0); if (info->boot_device_is_sd) printf("SD Boot: %s\n", diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c index e997acf1b7d..0917b33c254 100644 --- a/arch/arm/mach-uniphier/clk/clk-ld11.c +++ b/arch/arm/mach-uniphier/clk/clk-ld11.c @@ -17,16 +17,16 @@ void uniphier_ld11_clk_init(void) { /* if booted from a device other than USB, without stand-by MPU */ - if ((readl(SG_PINMON0) & BIT(27)) && + if ((readl(sg_base + SG_PINMON0) & BIT(27)) && uniphier_boot_device_raw() != BOOT_DEVICE_USB) { - writel(1, SG_ETPHYPSHUT); - writel(1, SG_ETPHYCNT); + writel(1, sg_base + SG_ETPHYPSHUT); + writel(1, sg_base + SG_ETPHYCNT); udelay(1); /* wait for regulator level 1.1V -> 2.5V */ - writel(3, SG_ETPHYCNT); - writel(3, SG_ETPHYPSHUT); - writel(7, SG_ETPHYCNT); + writel(3, sg_base + SG_ETPHYCNT); + writel(3, sg_base + SG_ETPHYPSHUT); + writel(7, sg_base + SG_ETPHYCNT); } /* TODO: use "mmc-pwrseq-emmc" */ @@ -37,7 +37,7 @@ void uniphier_ld11_clk_init(void) int ch; for (ch = 0; ch < 3; ch++) { - void __iomem *phyctrl = (void __iomem *)SG_USBPHYCTRL; + void __iomem *phyctrl = sg_base + SG_USBPHYCTRL; writel(0x82280600, phyctrl + 8 * ch); writel(0x00000106, phyctrl + 8 * ch + 4); diff --git a/arch/arm/mach-uniphier/clk/pll-ld4.c b/arch/arm/mach-uniphier/clk/pll-ld4.c index 6a145a3baa1..34f1c9cc289 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld4.c +++ b/arch/arm/mach-uniphier/clk/pll-ld4.c @@ -16,7 +16,7 @@ static void upll_init(void) { u32 tmp, clk_mode_upll, clk_mode_axosel; - tmp = readl(SG_PINMON0); + tmp = readl(sg_base + SG_PINMON0); clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; @@ -56,7 +56,7 @@ static void vpll_init(void) { u32 tmp, clk_mode_axosel; - tmp = readl(SG_PINMON0); + tmp = readl(sg_base + SG_PINMON0); clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; /* set 1 to VPLA27WP and VPLA27WP */ diff --git a/arch/arm/mach-uniphier/clk/pll-pro4.c b/arch/arm/mach-uniphier/clk/pll-pro4.c index 2ee2ed6bd66..312a5fcfdfc 100644 --- a/arch/arm/mach-uniphier/clk/pll-pro4.c +++ b/arch/arm/mach-uniphier/clk/pll-pro4.c @@ -17,7 +17,7 @@ static void vpll_init(void) u32 tmp, clk_mode_axosel; /* Set VPLL27A & VPLL27B */ - tmp = readl(SG_PINMON0); + tmp = readl(sg_base + SG_PINMON0); clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */ diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c index 0d6629918ac..9017a24a104 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c @@ -20,7 +20,7 @@ unsigned int uniphier_pro4_debug_uart_init(void) sg_set_iectrl(0); sg_set_pinsel(128, 0, 4, 8); /* TXD0 -> TXD0 */ - writel(1, SG_LOADPINCTRL); + writel(1, sg_base + SG_LOADPINCTRL); tmp = readl(SC_CLKCTRL); tmp |= SC_CLKCTRL_CEN_PERI; diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c index 1a0a942f2dc..8e4d15c2913 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c @@ -23,7 +23,7 @@ unsigned int uniphier_pro5_debug_uart_init(void) sg_set_pinsel(51, 0, 4, 8); /* TXD2 -> TXD2 */ sg_set_pinsel(53, 0, 4, 8); /* TXD3 -> TXD3 */ - writel(1, SG_LOADPINCTRL); + writel(1, sg_base + SG_LOADPINCTRL); tmp = readl(SC_CLKCTRL); tmp |= SC_CLKCTRL_CEN_PERI; diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart.c b/arch/arm/mach-uniphier/debug-uart/debug-uart.c index bc96b2e7be1..a70ce59accd 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.c @@ -32,7 +32,8 @@ void sg_set_pinsel(unsigned int pin, unsigned int muxval, unsigned int mux_bits, unsigned int reg_stride) { unsigned int shift = pin * mux_bits % 32; - unsigned long reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride; + void __iomem *reg = sg_base + SG_PINCTRL_BASE + + pin * mux_bits / 32 * reg_stride; u32 mask = (1U << mux_bits) - 1; u32 tmp; @@ -45,7 +46,7 @@ void sg_set_pinsel(unsigned int pin, unsigned int muxval, void sg_set_iectrl(unsigned int pin) { unsigned int bit = pin % 32; - unsigned long reg = SG_IECTRL + pin / 32 * 4; + void __iomem *reg = sg_base + SG_IECTRL + pin / 32 * 4; u32 tmp; tmp = readl(reg); diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index fa4b3e386b8..eca340b094e 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -85,7 +85,7 @@ static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map) return -EINVAL; } - val = readl(SG_MEMCONF); + val = readl(sg_base + SG_MEMCONF); /* set up ch0 */ dram_map[0].base = CONFIG_SYS_SDRAM_BASE; diff --git a/arch/arm/mach-uniphier/memconf.c b/arch/arm/mach-uniphier/memconf.c index 8105368df14..f69b489b76e 100644 --- a/arch/arm/mach-uniphier/memconf.c +++ b/arch/arm/mach-uniphier/memconf.c @@ -140,7 +140,7 @@ static int __uniphier_memconf_init(const struct uniphier_board_data *bd, } out: - writel(val, SG_MEMCONF); + writel(val, sg_base + SG_MEMCONF); return 0; } diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h index 39ffed5885d..cba02d1f4ae 100644 --- a/arch/arm/mach-uniphier/sg-regs.h +++ b/arch/arm/mach-uniphier/sg-regs.h @@ -10,15 +10,19 @@ #ifndef UNIPHIER_SG_REGS_H #define UNIPHIER_SG_REGS_H +#ifndef __ASSEMBLY__ +#include +#define sg_base ((void __iomem *)SG_BASE) +#endif + /* Base Address */ -#define SG_CTRL_BASE 0x5f800000 -#define SG_DBG_BASE 0x5f900000 +#define SG_BASE 0x5f800000 /* Revision */ -#define SG_REVISION (SG_CTRL_BASE | 0x0000) +#define SG_REVISION 0x0000 /* Memory Configuration */ -#define SG_MEMCONF (SG_CTRL_BASE | 0x0400) +#define SG_MEMCONF 0x0400 #define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0)) #define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0)) @@ -54,22 +58,22 @@ #define SG_MEMCONF_SPARSEMEM (0x1 << 4) -#define SG_USBPHYCTRL (SG_CTRL_BASE | 0x500) -#define SG_ETPHYPSHUT (SG_CTRL_BASE | 0x554) -#define SG_ETPHYCNT (SG_CTRL_BASE | 0x550) +#define SG_USBPHYCTRL 0x0500 +#define SG_ETPHYPSHUT 0x0554 +#define SG_ETPHYCNT 0x0550 /* Pin Control */ -#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000) +#define SG_PINCTRL_BASE 0x1000 /* PH1-Pro4, PH1-Pro5 */ -#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700) +#define SG_LOADPINCTRL 0x1700 /* Input Enable */ -#define SG_IECTRL (SG_CTRL_BASE | 0x1d00) +#define SG_IECTRL 0x1d00 /* Pin Monitor */ -#define SG_PINMON0 (SG_DBG_BASE | 0x0100) -#define SG_PINMON2 (SG_DBG_BASE | 0x0108) +#define SG_PINMON0 0x00100100 +#define SG_PINMON2 0x00100108 #define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19) #define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19) diff --git a/arch/arm/mach-uniphier/soc-info.c b/arch/arm/mach-uniphier/soc-info.c index ce2d4b6dea4..f021a8cab33 100644 --- a/arch/arm/mach-uniphier/soc-info.c +++ b/arch/arm/mach-uniphier/soc-info.c @@ -13,7 +13,7 @@ static unsigned int __uniphier_get_revision_field(unsigned int mask, unsigned int shift) { - u32 revision = readl(SG_REVISION); + u32 revision = readl(sg_base + SG_REVISION); return (revision >> shift) & mask; } -- cgit v1.2.3 From 739ba41d5a0964a9bc0d5705055ddb706d7e070d Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:41 +0900 Subject: ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/arm32/debug_ll.S | 8 +-- arch/arm/mach-uniphier/clk/clk-dram-ld4.c | 12 ++-- arch/arm/mach-uniphier/clk/clk-dram-pro5.c | 12 ++-- arch/arm/mach-uniphier/clk/clk-dram-pxs2.c | 12 ++-- arch/arm/mach-uniphier/clk/clk-early-ld4.c | 10 +-- arch/arm/mach-uniphier/clk/clk-ld20.c | 8 +-- arch/arm/mach-uniphier/clk/clk-ld4.c | 12 ++-- arch/arm/mach-uniphier/clk/clk-pro4.c | 18 ++--- arch/arm/mach-uniphier/clk/clk-pro5.c | 18 ++--- arch/arm/mach-uniphier/clk/clk-pxs2.c | 22 +++--- arch/arm/mach-uniphier/clk/clk-pxs3.c | 8 +-- arch/arm/mach-uniphier/clk/dpll-ld4.c | 8 +-- arch/arm/mach-uniphier/clk/dpll-pro4.c | 8 +-- arch/arm/mach-uniphier/clk/dpll-sld8.c | 12 ++-- arch/arm/mach-uniphier/clk/dpll-tail.c | 4 +- arch/arm/mach-uniphier/clk/pll-base-ld20.c | 41 ++--------- arch/arm/mach-uniphier/clk/pll-ld11.c | 18 ++--- arch/arm/mach-uniphier/clk/pll-ld20.c | 26 +++---- arch/arm/mach-uniphier/clk/pll-ld4.c | 82 +++++++++++----------- arch/arm/mach-uniphier/clk/pll-pro4.c | 64 ++++++++--------- arch/arm/mach-uniphier/clk/pll-pxs3.c | 30 ++++---- .../arm/mach-uniphier/debug-uart/debug-uart-ld6b.c | 4 +- .../arm/mach-uniphier/debug-uart/debug-uart-pro4.c | 4 +- .../arm/mach-uniphier/debug-uart/debug-uart-pro5.c | 4 +- .../arm/mach-uniphier/debug-uart/debug-uart-pxs2.c | 4 +- arch/arm/mach-uniphier/reset.c | 10 +-- arch/arm/mach-uniphier/sc-regs.h | 49 +++++++------ arch/arm/mach-uniphier/sc64-regs.h | 43 +++++++----- 28 files changed, 266 insertions(+), 285 deletions(-) diff --git a/arch/arm/mach-uniphier/arm32/debug_ll.S b/arch/arm/mach-uniphier/arm32/debug_ll.S index c155246ae8c..3fed7985fcd 100644 --- a/arch/arm/mach-uniphier/arm32/debug_ll.S +++ b/arch/arm/mach-uniphier/arm32/debug_ll.S @@ -63,7 +63,7 @@ ld4_end: mov r1, #1 str r1, [r0] - ldr r0, =SC_CLKCTRL + ldr r0, =(SC_BASE + SC_CLKCTRL) ldr r1, [r0] orr r1, r1, #SC_CLKCTRL_CEN_PERI str r1, [r0] @@ -104,7 +104,7 @@ sld8_end: mov r1, #1 str r1, [r0] - ldr r0, =SC_CLKCTRL + ldr r0, =(SC_BASE + SC_CLKCTRL) ldr r1, [r0] orr r1, r1, #SC_CLKCTRL_CEN_PERI str r1, [r0] @@ -129,7 +129,7 @@ pro5_end: sg_set_pinsel 113, 8, 8, 4, r0, r1 @ TXD2 -> TXD2 sg_set_pinsel 219, 8, 8, 4, r0, r1 @ TXD3 -> TXD3 - ldr r0, =SC_CLKCTRL + ldr r0, =(SC_BASE + SC_CLKCTRL) ldr r1, [r0] orr r1, r1, #SC_CLKCTRL_CEN_PERI str r1, [r0] @@ -153,7 +153,7 @@ pxs2_end: sg_set_pinsel 115, 0, 8, 4, r0, r1 @ TXD1 -> TXD1 sg_set_pinsel 113, 2, 8, 4, r0, r1 @ SBO0 -> TXD2 - ldr r0, =SC_CLKCTRL + ldr r0, =(SC_BASE + SC_CLKCTRL) ldr r1, [r0] orr r1, r1, #SC_CLKCTRL_CEN_PERI str r1, [r0] diff --git a/arch/arm/mach-uniphier/clk/clk-dram-ld4.c b/arch/arm/mach-uniphier/clk/clk-dram-ld4.c index 39cde4400b4..c796d364bb1 100644 --- a/arch/arm/mach-uniphier/clk/clk-dram-ld4.c +++ b/arch/arm/mach-uniphier/clk/clk-dram-ld4.c @@ -16,14 +16,14 @@ void uniphier_ld4_dram_clk_init(void) u32 tmp; /* deassert reset */ - tmp = readl(SC_RSTCTRL); + tmp = readl(sc_base + SC_RSTCTRL); tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0; - writel(tmp, SC_RSTCTRL); - readl(SC_RSTCTRL); /* dummy read */ + writel(tmp, sc_base + SC_RSTCTRL); + readl(sc_base + SC_RSTCTRL); /* dummy read */ /* provide clocks */ - tmp = readl(SC_CLKCTRL); + tmp = readl(sc_base + SC_CLKCTRL); tmp |= SC_CLKCTRL_CEN_UMC; - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ + writel(tmp, sc_base + SC_CLKCTRL); + readl(sc_base + SC_CLKCTRL); /* dummy read */ } diff --git a/arch/arm/mach-uniphier/clk/clk-dram-pro5.c b/arch/arm/mach-uniphier/clk/clk-dram-pro5.c index 7674ceb885f..808d1ebfe19 100644 --- a/arch/arm/mach-uniphier/clk/clk-dram-pro5.c +++ b/arch/arm/mach-uniphier/clk/clk-dram-pro5.c @@ -18,17 +18,17 @@ void uniphier_pro5_dram_clk_init(void) * UMCA1, UMC31: Ch0 (WIO1) * UMCA0, UMC30: Ch0 (WIO0) */ - tmp = readl(SC_RSTCTRL4); + tmp = readl(sc_base + SC_RSTCTRL4); tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 | SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 | SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30; - writel(tmp, SC_RSTCTRL4); - readl(SC_RSTCTRL4); /* dummy read */ + writel(tmp, sc_base + SC_RSTCTRL4); + readl(sc_base + SC_RSTCTRL4); /* dummy read */ /* provide clocks */ - tmp = readl(SC_CLKCTRL4); + tmp = readl(sc_base + SC_CLKCTRL4); tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 | SC_CLKCTRL4_CEN_UMC0; - writel(tmp, SC_CLKCTRL4); - readl(SC_CLKCTRL4); /* dummy read */ + writel(tmp, sc_base + SC_CLKCTRL4); + readl(sc_base + SC_CLKCTRL4); /* dummy read */ } diff --git a/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c b/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c index ad4e83a84a2..b78bd016721 100644 --- a/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c +++ b/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c @@ -15,18 +15,18 @@ void uniphier_pxs2_dram_clk_init(void) u32 tmp; /* deassert reset */ - tmp = readl(SC_RSTCTRL4); + tmp = readl(sc_base + SC_RSTCTRL4); tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 | SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 | SC_RSTCTRL4_NRST_UMC32 | SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30; - writel(tmp, SC_RSTCTRL4); - readl(SC_RSTCTRL4); /* dummy read */ + writel(tmp, sc_base + SC_RSTCTRL4); + readl(sc_base + SC_RSTCTRL4); /* dummy read */ /* provide clocks */ - tmp = readl(SC_CLKCTRL4); + tmp = readl(sc_base + SC_CLKCTRL4); tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC2 | SC_CLKCTRL4_CEN_UMC1 | SC_CLKCTRL4_CEN_UMC0; - writel(tmp, SC_CLKCTRL4); - readl(SC_CLKCTRL4); /* dummy read */ + writel(tmp, sc_base + SC_CLKCTRL4); + readl(sc_base + SC_CLKCTRL4); /* dummy read */ } diff --git a/arch/arm/mach-uniphier/clk/clk-early-ld4.c b/arch/arm/mach-uniphier/clk/clk-early-ld4.c index eb36a9e7ae4..f32f78dd26d 100644 --- a/arch/arm/mach-uniphier/clk/clk-early-ld4.c +++ b/arch/arm/mach-uniphier/clk/clk-early-ld4.c @@ -17,14 +17,14 @@ void uniphier_ld4_early_clk_init(void) /* deassert reset */ if (spl_boot_device() != BOOT_DEVICE_NAND) { - tmp = readl(SC_RSTCTRL); + tmp = readl(sc_base + SC_RSTCTRL); tmp &= ~SC_RSTCTRL_NRST_NAND; - writel(tmp, SC_RSTCTRL); + writel(tmp, sc_base + SC_RSTCTRL); }; /* provide clocks */ - tmp = readl(SC_CLKCTRL); + tmp = readl(sc_base + SC_CLKCTRL); tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI; - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ + writel(tmp, sc_base + SC_CLKCTRL); + readl(sc_base + SC_CLKCTRL); /* dummy read */ } diff --git a/arch/arm/mach-uniphier/clk/clk-ld20.c b/arch/arm/mach-uniphier/clk/clk-ld20.c index 02a14ddfb8b..397b2d7384f 100644 --- a/arch/arm/mach-uniphier/clk/clk-ld20.c +++ b/arch/arm/mach-uniphier/clk/clk-ld20.c @@ -15,13 +15,13 @@ void uniphier_ld20_clk_init(void) { u32 tmp; - tmp = readl(SC_RSTCTRL6); + tmp = readl(sc_base + SC_RSTCTRL6); tmp |= BIT(8); /* Mali */ - writel(tmp, SC_RSTCTRL6); + writel(tmp, sc_base + SC_RSTCTRL6); - tmp = readl(SC_CLKCTRL6); + tmp = readl(sc_base + SC_CLKCTRL6); tmp |= BIT(8); /* Mali */ - writel(tmp, SC_CLKCTRL6); + writel(tmp, sc_base + SC_CLKCTRL6); /* TODO: use "mmc-pwrseq-emmc" */ writel(1, SDCTRL_EMMC_HW_RESET); diff --git a/arch/arm/mach-uniphier/clk/clk-ld4.c b/arch/arm/mach-uniphier/clk/clk-ld4.c index 9c88cde5e25..03939425039 100644 --- a/arch/arm/mach-uniphier/clk/clk-ld4.c +++ b/arch/arm/mach-uniphier/clk/clk-ld4.c @@ -15,18 +15,18 @@ void uniphier_ld4_clk_init(void) u32 tmp; /* deassert reset */ - tmp = readl(SC_RSTCTRL); + tmp = readl(sc_base + SC_RSTCTRL); #ifdef CONFIG_NAND_DENALI tmp |= SC_RSTCTRL_NRST_NAND; #endif - writel(tmp, SC_RSTCTRL); - readl(SC_RSTCTRL); /* dummy read */ + writel(tmp, sc_base + SC_RSTCTRL); + readl(sc_base + SC_RSTCTRL); /* dummy read */ /* provide clocks */ - tmp = readl(SC_CLKCTRL); + tmp = readl(sc_base + SC_CLKCTRL); #ifdef CONFIG_NAND_DENALI tmp |= SC_CLKCTRL_CEN_NAND; #endif - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ + writel(tmp, sc_base + SC_CLKCTRL); + readl(sc_base + SC_CLKCTRL); /* dummy read */ } diff --git a/arch/arm/mach-uniphier/clk/clk-pro4.c b/arch/arm/mach-uniphier/clk/clk-pro4.c index 32d44c0b667..2b364dca410 100644 --- a/arch/arm/mach-uniphier/clk/clk-pro4.c +++ b/arch/arm/mach-uniphier/clk/clk-pro4.c @@ -15,7 +15,7 @@ void uniphier_pro4_clk_init(void) u32 tmp; /* deassert reset */ - tmp = readl(SC_RSTCTRL); + tmp = readl(sc_base + SC_RSTCTRL); #ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 | SC_RSTCTRL_NRST_GIO; @@ -23,18 +23,18 @@ void uniphier_pro4_clk_init(void) #ifdef CONFIG_NAND_DENALI tmp |= SC_RSTCTRL_NRST_NAND; #endif - writel(tmp, SC_RSTCTRL); - readl(SC_RSTCTRL); /* dummy read */ + writel(tmp, sc_base + SC_RSTCTRL); + readl(sc_base + SC_RSTCTRL); /* dummy read */ #ifdef CONFIG_USB_DWC3_UNIPHIER - tmp = readl(SC_RSTCTRL2); + tmp = readl(sc_base + SC_RSTCTRL2); tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1; - writel(tmp, SC_RSTCTRL2); - readl(SC_RSTCTRL2); /* dummy read */ + writel(tmp, sc_base + SC_RSTCTRL2); + readl(sc_base + SC_RSTCTRL2); /* dummy read */ #endif /* provide clocks */ - tmp = readl(SC_CLKCTRL); + tmp = readl(sc_base + SC_CLKCTRL); #ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | SC_CLKCTRL_CEN_GIO; @@ -42,6 +42,6 @@ void uniphier_pro4_clk_init(void) #ifdef CONFIG_NAND_DENALI tmp |= SC_CLKCTRL_CEN_NAND; #endif - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ + writel(tmp, sc_base + SC_CLKCTRL); + readl(sc_base + SC_CLKCTRL); /* dummy read */ } diff --git a/arch/arm/mach-uniphier/clk/clk-pro5.c b/arch/arm/mach-uniphier/clk/clk-pro5.c index 338d73d0708..874964b2d5b 100644 --- a/arch/arm/mach-uniphier/clk/clk-pro5.c +++ b/arch/arm/mach-uniphier/clk/clk-pro5.c @@ -13,25 +13,25 @@ void uniphier_pro5_clk_init(void) u32 tmp; /* deassert reset */ - tmp = readl(SC_RSTCTRL); + tmp = readl(sc_base + SC_RSTCTRL); #ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO; #endif #ifdef CONFIG_NAND_DENALI tmp |= SC_RSTCTRL_NRST_NAND; #endif - writel(tmp, SC_RSTCTRL); - readl(SC_RSTCTRL); /* dummy read */ + writel(tmp, sc_base + SC_RSTCTRL); + readl(sc_base + SC_RSTCTRL); /* dummy read */ #ifdef CONFIG_USB_DWC3_UNIPHIER - tmp = readl(SC_RSTCTRL2); + tmp = readl(sc_base + SC_RSTCTRL2); tmp |= SC_RSTCTRL2_NRST_USB3B1; - writel(tmp, SC_RSTCTRL2); - readl(SC_RSTCTRL2); /* dummy read */ + writel(tmp, sc_base + SC_RSTCTRL2); + readl(sc_base + SC_RSTCTRL2); /* dummy read */ #endif /* provide clocks */ - tmp = readl(SC_CLKCTRL); + tmp = readl(sc_base + SC_CLKCTRL); #ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | SC_CLKCTRL_CEN_GIO; @@ -39,6 +39,6 @@ void uniphier_pro5_clk_init(void) #ifdef CONFIG_NAND_DENALI tmp |= SC_CLKCTRL_CEN_NAND; #endif - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ + writel(tmp, sc_base + SC_CLKCTRL); + readl(sc_base + SC_CLKCTRL); /* dummy read */ } diff --git a/arch/arm/mach-uniphier/clk/clk-pxs2.c b/arch/arm/mach-uniphier/clk/clk-pxs2.c index afa12fa071e..8cb4f87ae54 100644 --- a/arch/arm/mach-uniphier/clk/clk-pxs2.c +++ b/arch/arm/mach-uniphier/clk/clk-pxs2.c @@ -14,29 +14,29 @@ void uniphier_pxs2_clk_init(void) u32 tmp; /* deassert reset */ - tmp = readl(SC_RSTCTRL); + tmp = readl(sc_base + SC_RSTCTRL); #ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO; #endif #ifdef CONFIG_NAND_DENALI tmp |= SC_RSTCTRL_NRST_NAND; #endif - writel(tmp, SC_RSTCTRL); - readl(SC_RSTCTRL); /* dummy read */ + writel(tmp, sc_base + SC_RSTCTRL); + readl(sc_base + SC_RSTCTRL); /* dummy read */ #ifdef CONFIG_USB_DWC3_UNIPHIER - tmp = readl(SC_RSTCTRL2); + tmp = readl(sc_base + SC_RSTCTRL2); tmp |= SC_RSTCTRL2_NRST_USB3B1; - writel(tmp, SC_RSTCTRL2); - readl(SC_RSTCTRL2); /* dummy read */ + writel(tmp, sc_base + SC_RSTCTRL2); + readl(sc_base + SC_RSTCTRL2); /* dummy read */ - tmp = readl(SC_RSTCTRL6); + tmp = readl(sc_base + SC_RSTCTRL6); tmp |= 0x37; - writel(tmp, SC_RSTCTRL6); + writel(tmp, sc_base + SC_RSTCTRL6); #endif /* provide clocks */ - tmp = readl(SC_CLKCTRL); + tmp = readl(sc_base + SC_CLKCTRL); #ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | SC_CLKCTRL_CEN_GIO; @@ -44,6 +44,6 @@ void uniphier_pxs2_clk_init(void) #ifdef CONFIG_NAND_DENALI tmp |= SC_CLKCTRL_CEN_NAND; #endif - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ + writel(tmp, sc_base + SC_CLKCTRL); + readl(sc_base + SC_CLKCTRL); /* dummy read */ } diff --git a/arch/arm/mach-uniphier/clk/clk-pxs3.c b/arch/arm/mach-uniphier/clk/clk-pxs3.c index 73824e9ace6..33b9c5b73d1 100644 --- a/arch/arm/mach-uniphier/clk/clk-pxs3.c +++ b/arch/arm/mach-uniphier/clk/clk-pxs3.c @@ -15,13 +15,13 @@ void uniphier_pxs3_clk_init(void) { u32 tmp; - tmp = readl(SC_RSTCTRL6); + tmp = readl(sc_base + SC_RSTCTRL6); tmp |= BIT(8); /* Mali */ - writel(tmp, SC_RSTCTRL6); + writel(tmp, sc_base + SC_RSTCTRL6); - tmp = readl(SC_CLKCTRL6); + tmp = readl(sc_base + SC_CLKCTRL6); tmp |= BIT(8); /* Mali */ - writel(tmp, SC_CLKCTRL6); + writel(tmp, sc_base + SC_CLKCTRL6); /* TODO: use "mmc-pwrseq-emmc" */ writel(1, SDCTRL_EMMC_HW_RESET); diff --git a/arch/arm/mach-uniphier/clk/dpll-ld4.c b/arch/arm/mach-uniphier/clk/dpll-ld4.c index 4b9ec075a84..72fe8db8dd1 100644 --- a/arch/arm/mach-uniphier/clk/dpll-ld4.c +++ b/arch/arm/mach-uniphier/clk/dpll-ld4.c @@ -23,7 +23,7 @@ int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd) * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) * to FOUT (DPLLCTRL.bit[29:20]) */ - tmp = readl(SC_DPLLCTRL); + tmp = readl(sc_base + SC_DPLLCTRL); tmp &= ~0x000f0000; switch (dram_freq) { case 1333: @@ -42,11 +42,11 @@ int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd) #else tmp |= SC_DPLLCTRL_SSC_RATE; #endif - writel(tmp, SC_DPLLCTRL); + writel(tmp, sc_base + SC_DPLLCTRL); - tmp = readl(SC_DPLLCTRL2); + tmp = readl(sc_base + SC_DPLLCTRL2); tmp |= SC_DPLLCTRL2_NRSTDS; - writel(tmp, SC_DPLLCTRL2); + writel(tmp, sc_base + SC_DPLLCTRL2); /* Wait 500 usec until dpll gets stable */ udelay(500); diff --git a/arch/arm/mach-uniphier/clk/dpll-pro4.c b/arch/arm/mach-uniphier/clk/dpll-pro4.c index 29659464b57..62594954848 100644 --- a/arch/arm/mach-uniphier/clk/dpll-pro4.c +++ b/arch/arm/mach-uniphier/clk/dpll-pro4.c @@ -23,7 +23,7 @@ int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd) * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) * to FOUT ( DPLLCTRL.bit[29:20] ) */ - tmp = readl(SC_DPLLCTRL); + tmp = readl(sc_base + SC_DPLLCTRL); tmp &= ~(0x000f0000); switch (dram_freq) { case 1333: @@ -46,11 +46,11 @@ int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd) #else tmp |= 0x00008000; #endif - writel(tmp, SC_DPLLCTRL); + writel(tmp, sc_base + SC_DPLLCTRL); - tmp = readl(SC_DPLLCTRL2); + tmp = readl(sc_base + SC_DPLLCTRL2); tmp |= SC_DPLLCTRL2_NRSTDS; - writel(tmp, SC_DPLLCTRL2); + writel(tmp, sc_base + SC_DPLLCTRL2); /* Wait until dpll gets stable */ udelay(500); diff --git a/arch/arm/mach-uniphier/clk/dpll-sld8.c b/arch/arm/mach-uniphier/clk/dpll-sld8.c index 1d7b7521984..1ac52d11f34 100644 --- a/arch/arm/mach-uniphier/clk/dpll-sld8.c +++ b/arch/arm/mach-uniphier/clk/dpll-sld8.c @@ -22,10 +22,10 @@ int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd) * [4] ICPD_TEST 0x1 * [3:0] ICPD 0xb */ - tmp = readl(SC_DPLLCTRL3); + tmp = readl(sc_base + SC_DPLLCTRL3); tmp &= ~0x00ff0717; tmp |= 0x00d0061b; - writel(tmp, SC_DPLLCTRL3); + writel(tmp, sc_base + SC_DPLLCTRL3); /* * Set DPLL SSC parameters for DPLLCTRL @@ -33,14 +33,14 @@ int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd) * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084) * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6) */ - tmp = readl(SC_DPLLCTRL); + tmp = readl(sc_base + SC_DPLLCTRL); tmp &= ~0x3ff07fff; #ifdef DPLL_SSC_RATE_1PER tmp |= 0x084018bf; #else tmp |= 0x084031a6; #endif - writel(tmp, SC_DPLLCTRL); + writel(tmp, sc_base + SC_DPLLCTRL); /* * Set DPLL SSC parameters for DPLLCTRL2 @@ -49,10 +49,10 @@ int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd) * [26:20] SSC_M 79 (0x4f) * [19:0] SSC_K 964689 (0xeb851) */ - tmp = readl(SC_DPLLCTRL2); + tmp = readl(sc_base + SC_DPLLCTRL2); tmp &= ~0xefffffff; tmp |= 0x0cfeb851; - writel(tmp, SC_DPLLCTRL2); + writel(tmp, sc_base + SC_DPLLCTRL2); /* Wait 500 usec until dpll gets stable */ udelay(500); diff --git a/arch/arm/mach-uniphier/clk/dpll-tail.c b/arch/arm/mach-uniphier/clk/dpll-tail.c index 7f434f66962..6ba5a367274 100644 --- a/arch/arm/mach-uniphier/clk/dpll-tail.c +++ b/arch/arm/mach-uniphier/clk/dpll-tail.c @@ -14,7 +14,7 @@ void uniphier_ld4_dpll_ssc_en(void) { u32 tmp; - tmp = readl(SC_DPLLCTRL); + tmp = readl(sc_base + SC_DPLLCTRL); tmp |= SC_DPLLCTRL_SSC_EN; - writel(tmp, SC_DPLLCTRL); + writel(tmp, sc_base + SC_DPLLCTRL); } diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c index 67b8ee7c3e3..ea96d739c53 100644 --- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c @@ -12,6 +12,7 @@ #include #include +#include "../sc64-regs.h" #include "pll.h" /* PLL type: SSC */ @@ -31,13 +32,9 @@ int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, unsigned int ssc_rate, unsigned int divn) { - void __iomem *base; + void __iomem *base = sc_base + reg_base; u32 tmp; - base = ioremap(reg_base, SZ_16); - if (!base) - return -ENOMEM; - if (freq != UNIPHIER_PLL_FREQ_DEFAULT) { tmp = readl(base); /* SSCPLLCTRL */ tmp &= ~SC_PLLCTRL_SSC_DK_MASK; @@ -60,57 +57,39 @@ int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, tmp |= SC_PLLCTRL2_NRSTDS; writel(tmp, base + 4); - iounmap(base); - return 0; } int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base) { - void __iomem *base; + void __iomem *base = sc_base + reg_base; u32 tmp; - base = ioremap(reg_base, SZ_16); - if (!base) - return -ENOMEM; - tmp = readl(base); /* SSCPLLCTRL */ tmp |= SC_PLLCTRL_SSC_EN; writel(tmp, base); - iounmap(base); - return 0; } int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) { - void __iomem *base; + void __iomem *base = sc_base + reg_base; u32 tmp; - base = ioremap(reg_base, SZ_16); - if (!base) - return -ENOMEM; - tmp = readl(base + 8); /* SSCPLLCTRL3 */ tmp &= ~SC_PLLCTRL3_REGI_MASK; tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); writel(tmp, base + 8); - iounmap(base); - return 0; } int uniphier_ld20_vpll27_init(unsigned long reg_base) { - void __iomem *base; + void __iomem *base = sc_base + reg_base; u32 tmp; - base = ioremap(reg_base, SZ_16); - if (!base) - return -ENOMEM; - tmp = readl(base); /* VPLL27CTRL */ tmp |= SC_VPLL27CTRL_WP; /* write protect off */ writel(tmp, base); @@ -123,25 +102,17 @@ int uniphier_ld20_vpll27_init(unsigned long reg_base) tmp &= ~SC_VPLL27CTRL_WP; /* write protect on */ writel(tmp, base); - iounmap(base); - return 0; } int uniphier_ld20_dspll_init(unsigned long reg_base) { - void __iomem *base; + void __iomem *base = sc_base + reg_base; u32 tmp; - base = ioremap(reg_base, SZ_16); - if (!base) - return -ENOMEM; - tmp = readl(base + 4); /* DSPLLCTRL2 */ tmp |= SC_DSPLLCTRL2_K_LD; writel(tmp, base + 4); - iounmap(base); - return 0; } diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c index fd724f3e8c2..7f07e3e92b8 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld11.c +++ b/arch/arm/mach-uniphier/clk/pll-ld11.c @@ -11,15 +11,15 @@ #include "pll.h" /* PLL type: SSC */ -#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */ -#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */ -#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* DSP */ -#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* Video codec, VPE etc. */ -#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* DDR memory */ +#define SC_CPLLCTRL 0x1400 /* CPU/ARM */ +#define SC_SPLLCTRL 0x1410 /* misc */ +#define SC_MPLLCTRL 0x1430 /* DSP */ +#define SC_VSPLLCTRL 0x1440 /* Video codec, VPE etc. */ +#define SC_DPLLCTRL 0x1460 /* DDR memory */ /* PLL type: VPLL27 */ -#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) -#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) +#define SC_VPLL27FCTRL 0x1500 +#define SC_VPLL27ACTRL 0x1520 void uniphier_ld11_pll_init(void) { @@ -40,6 +40,6 @@ void uniphier_ld11_pll_init(void) uniphier_ld20_vpll27_init(SC_VPLL27FCTRL); uniphier_ld20_vpll27_init(SC_VPLL27ACTRL); - writel(0, SC_CA53_GEARSET); /* Gear0: CPLL/2 */ - writel(SC_CA_GEARUPD, SC_CA53_GEARUPD); + writel(0, sc_base + SC_CA53_GEARSET); /* Gear0: CPLL/2 */ + writel(SC_CA_GEARUPD, sc_base + SC_CA53_GEARUPD); } diff --git a/arch/arm/mach-uniphier/clk/pll-ld20.c b/arch/arm/mach-uniphier/clk/pll-ld20.c index 682bd1e0c12..04b3312a2a5 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-ld20.c @@ -11,23 +11,23 @@ #include "pll.h" /* PLL type: SSC */ -#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */ -#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */ -#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */ -#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* Video codec */ -#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* VPE etc. */ -#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* GPU/Mali */ -#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* DDR memory 0 */ -#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* DDR memory 1 */ -#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 2 */ +#define SC_CPLLCTRL 0x1400 /* CPU/ARM */ +#define SC_SPLLCTRL 0x1410 /* misc */ +#define SC_SPLL2CTRL 0x1420 /* DSP */ +#define SC_MPLLCTRL 0x1430 /* Video codec */ +#define SC_VPPLLCTRL 0x1440 /* VPE etc. */ +#define SC_GPPLLCTRL 0x1450 /* GPU/Mali */ +#define SC_DPLL0CTRL 0x1460 /* DDR memory 0 */ +#define SC_DPLL1CTRL 0x1470 /* DDR memory 1 */ +#define SC_DPLL2CTRL 0x1480 /* DDR memory 2 */ /* PLL type: VPLL27 */ -#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) -#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) +#define SC_VPLL27FCTRL 0x1500 +#define SC_VPLL27ACTRL 0x1520 /* PLL type: DSPLL */ -#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540) -#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0) +#define SC_VPLL8KCTRL 0x1540 +#define SC_A2PLLCTRL 0x15C0 void uniphier_ld20_pll_init(void) { diff --git a/arch/arm/mach-uniphier/clk/pll-ld4.c b/arch/arm/mach-uniphier/clk/pll-ld4.c index 34f1c9cc289..c66031bdd05 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld4.c +++ b/arch/arm/mach-uniphier/clk/pll-ld4.c @@ -21,9 +21,9 @@ static void upll_init(void) clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ - tmp = readl(SC_UPLLCTRL); + tmp = readl(sc_base + SC_UPLLCTRL); tmp &= ~0x18000000; - writel(tmp, SC_UPLLCTRL); + writel(tmp, sc_base + SC_UPLLCTRL); if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) { if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || @@ -38,18 +38,18 @@ static void upll_init(void) } } - writel(tmp, SC_UPLLCTRL); + writel(tmp, sc_base + SC_UPLLCTRL); /* set 1 to K_LD(UPLLCTRL.bit[27]) */ tmp |= 0x08000000; - writel(tmp, SC_UPLLCTRL); + writel(tmp, sc_base + SC_UPLLCTRL); /* wait 10 usec */ udelay(10); /* set 1 to SNRT(UPLLCTRL.bit[28]) */ tmp |= 0x10000000; - writel(tmp, SC_UPLLCTRL); + writel(tmp, sc_base + SC_UPLLCTRL); } static void vpll_init(void) @@ -60,88 +60,88 @@ static void vpll_init(void) clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; /* set 1 to VPLA27WP and VPLA27WP */ - tmp = readl(SC_VPLL27ACTRL); + tmp = readl(sc_base + SC_VPLL27ACTRL); tmp |= 0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); + writel(tmp, sc_base + SC_VPLL27ACTRL); + tmp = readl(sc_base + SC_VPLL27BCTRL); tmp |= 0x00000001; - writel(tmp, SC_VPLL27BCTRL); + writel(tmp, sc_base + SC_VPLL27BCTRL); /* Set 0 to VPLA_K_LD and VPLB_K_LD */ - tmp = readl(SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27ACTRL3); tmp &= ~0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27BCTRL3); tmp &= ~0x10000000; - writel(tmp, SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27BCTRL3); /* Set 0 to VPLA_SNRST and VPLB_SNRST */ - tmp = readl(SC_VPLL27ACTRL2); + tmp = readl(sc_base + SC_VPLL27ACTRL2); tmp &= ~0x10000000; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); + writel(tmp, sc_base + SC_VPLL27ACTRL2); + tmp = readl(sc_base + SC_VPLL27BCTRL2); tmp &= ~0x10000000; - writel(tmp, SC_VPLL27BCTRL2); + writel(tmp, sc_base + SC_VPLL27BCTRL2); /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ - tmp = readl(SC_VPLL27ACTRL2); + tmp = readl(sc_base + SC_VPLL27ACTRL2); tmp &= ~0x0000007f; tmp |= 0x00000020; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); + writel(tmp, sc_base + SC_VPLL27ACTRL2); + tmp = readl(sc_base + SC_VPLL27BCTRL2); tmp &= ~0x0000007f; tmp |= 0x00000020; - writel(tmp, SC_VPLL27BCTRL2); + writel(tmp, sc_base + SC_VPLL27BCTRL2); if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { /* AXO: 25MHz */ - tmp = readl(SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27ACTRL3); tmp &= ~0x000fffff; tmp |= 0x00066664; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27BCTRL3); tmp &= ~0x000fffff; tmp |= 0x00066664; - writel(tmp, SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27BCTRL3); } else { /* AXO: default 24.576MHz */ - tmp = readl(SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27ACTRL3); tmp &= ~0x000fffff; tmp |= 0x000f5800; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27BCTRL3); tmp &= ~0x000fffff; tmp |= 0x000f5800; - writel(tmp, SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27BCTRL3); } /* Set 1 to VPLA_K_LD and VPLB_K_LD */ - tmp = readl(SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27ACTRL3); tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27BCTRL3); tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27BCTRL3); /* wait 10 usec */ udelay(10); /* Set 0 to VPLA_SNRST and VPLB_SNRST */ - tmp = readl(SC_VPLL27ACTRL2); + tmp = readl(sc_base + SC_VPLL27ACTRL2); tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); + writel(tmp, sc_base + SC_VPLL27ACTRL2); + tmp = readl(sc_base + SC_VPLL27BCTRL2); tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL2); + writel(tmp, sc_base + SC_VPLL27BCTRL2); /* set 0 to VPLA27WP and VPLA27WP */ - tmp = readl(SC_VPLL27ACTRL); + tmp = readl(sc_base + SC_VPLL27ACTRL); tmp &= ~0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); + writel(tmp, sc_base + SC_VPLL27ACTRL); + tmp = readl(sc_base + SC_VPLL27BCTRL); tmp |= ~0x00000001; - writel(tmp, SC_VPLL27BCTRL); + writel(tmp, sc_base + SC_VPLL27BCTRL); } void uniphier_ld4_pll_init(void) diff --git a/arch/arm/mach-uniphier/clk/pll-pro4.c b/arch/arm/mach-uniphier/clk/pll-pro4.c index 312a5fcfdfc..b7dc3e261f8 100644 --- a/arch/arm/mach-uniphier/clk/pll-pro4.c +++ b/arch/arm/mach-uniphier/clk/pll-pro4.c @@ -26,80 +26,80 @@ static void vpll_init(void) return; /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */ - tmp = readl(SC_VPLL27ACTRL); + tmp = readl(sc_base + SC_VPLL27ACTRL); tmp |= 0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); + writel(tmp, sc_base + SC_VPLL27ACTRL); + tmp = readl(sc_base + SC_VPLL27BCTRL); tmp |= 0x00000001; - writel(tmp, SC_VPLL27BCTRL); + writel(tmp, sc_base + SC_VPLL27BCTRL); /* Unset VPLA_K_LD and VPLB_K_LD bit */ - tmp = readl(SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27ACTRL3); tmp &= ~0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27BCTRL3); tmp &= ~0x10000000; - writel(tmp, SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27BCTRL3); /* Set VPLA_M and VPLB_M to 0x20 */ - tmp = readl(SC_VPLL27ACTRL2); + tmp = readl(sc_base + SC_VPLL27ACTRL2); tmp &= ~0x0000007f; tmp |= 0x00000020; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); + writel(tmp, sc_base + SC_VPLL27ACTRL2); + tmp = readl(sc_base + SC_VPLL27BCTRL2); tmp &= ~0x0000007f; tmp |= 0x00000020; - writel(tmp, SC_VPLL27BCTRL2); + writel(tmp, sc_base + SC_VPLL27BCTRL2); if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ || clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) { /* Set VPLA_K and VPLB_K for AXO: 25MHz */ - tmp = readl(SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27ACTRL3); tmp &= ~0x000fffff; tmp |= 0x00066666; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27BCTRL3); tmp &= ~0x000fffff; tmp |= 0x00066666; - writel(tmp, SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27BCTRL3); } else { /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */ - tmp = readl(SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27ACTRL3); tmp &= ~0x000fffff; tmp |= 0x000f5800; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27BCTRL3); tmp &= ~0x000fffff; tmp |= 0x000f5800; - writel(tmp, SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27BCTRL3); } /* wait 1 usec */ udelay(1); /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */ - tmp = readl(SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27ACTRL3); tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27ACTRL3); + tmp = readl(sc_base + SC_VPLL27BCTRL3); tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL3); + writel(tmp, sc_base + SC_VPLL27BCTRL3); /* Unset VPLA_SNRST and VPLB_SNRST bit */ - tmp = readl(SC_VPLL27ACTRL2); + tmp = readl(sc_base + SC_VPLL27ACTRL2); tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); + writel(tmp, sc_base + SC_VPLL27ACTRL2); + tmp = readl(sc_base + SC_VPLL27BCTRL2); tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL2); + writel(tmp, sc_base + SC_VPLL27BCTRL2); /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */ - tmp = readl(SC_VPLL27ACTRL); + tmp = readl(sc_base + SC_VPLL27ACTRL); tmp &= ~0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); + writel(tmp, sc_base + SC_VPLL27ACTRL); + tmp = readl(sc_base + SC_VPLL27BCTRL); tmp &= ~0x00000001; - writel(tmp, SC_VPLL27BCTRL); + writel(tmp, sc_base + SC_VPLL27BCTRL); } void uniphier_pro4_pll_init(void) diff --git a/arch/arm/mach-uniphier/clk/pll-pxs3.c b/arch/arm/mach-uniphier/clk/pll-pxs3.c index 5a1b1d25aca..278f530ea9a 100644 --- a/arch/arm/mach-uniphier/clk/pll-pxs3.c +++ b/arch/arm/mach-uniphier/clk/pll-pxs3.c @@ -10,25 +10,25 @@ #include "pll.h" /* PLL type: SSC */ -#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */ -#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */ -#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */ -#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1430) /* VPE */ -#define SC_VGPLLCTRL (SC_BASE_ADDR | 0x1440) -#define SC_DECPLLCTRL (SC_BASE_ADDR | 0x1450) -#define SC_ENCPLLCTRL (SC_BASE_ADDR | 0x1460) -#define SC_PXFPLLCTRL (SC_BASE_ADDR | 0x1470) -#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 0 */ -#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1490) /* DDR memory 1 */ -#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x14a0) /* DDR memory 2 */ -#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x14c0) +#define SC_CPLLCTRL 0x1400 /* CPU/ARM */ +#define SC_SPLLCTRL 0x1410 /* misc */ +#define SC_SPLL2CTRL 0x1420 /* DSP */ +#define SC_VPPLLCTRL 0x1430 /* VPE */ +#define SC_VGPLLCTRL 0x1440 +#define SC_DECPLLCTRL 0x1450 +#define SC_ENCPLLCTRL 0x1460 +#define SC_PXFPLLCTRL 0x1470 +#define SC_DPLL0CTRL 0x1480 /* DDR memory 0 */ +#define SC_DPLL1CTRL 0x1490 /* DDR memory 1 */ +#define SC_DPLL2CTRL 0x14a0 /* DDR memory 2 */ +#define SC_VSPLLCTRL 0x14c0 /* PLL type: VPLL27 */ -#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) -#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) +#define SC_VPLL27FCTRL 0x1500 +#define SC_VPLL27ACTRL 0x1520 /* PLL type: DSPLL */ -#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540) +#define SC_VPLL8KCTRL 0x1540 void uniphier_pxs3_pll_init(void) { diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-ld6b.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-ld6b.c index 22d2caa1099..f64ff39c9e6 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart-ld6b.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-ld6b.c @@ -22,9 +22,9 @@ unsigned int uniphier_ld6b_debug_uart_init(void) sg_set_pinsel(115, 0, 8, 4); /* TXD1 -> TXD1 */ sg_set_pinsel(113, 2, 8, 4); /* SBO0 -> TXD2 */ - tmp = readl(SC_CLKCTRL); + tmp = readl(sc_base + SC_CLKCTRL); tmp |= SC_CLKCTRL_CEN_PERI; - writel(tmp, SC_CLKCTRL); + writel(tmp, sc_base + SC_CLKCTRL); return DIV_ROUND_CLOSEST(UNIPHIER_LD6B_UART_CLK, 16 * CONFIG_BAUDRATE); } diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c index 9017a24a104..79c6c101e22 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c @@ -22,9 +22,9 @@ unsigned int uniphier_pro4_debug_uart_init(void) writel(1, sg_base + SG_LOADPINCTRL); - tmp = readl(SC_CLKCTRL); + tmp = readl(sc_base + SC_CLKCTRL); tmp |= SC_CLKCTRL_CEN_PERI; - writel(tmp, SC_CLKCTRL); + writel(tmp, sc_base + SC_CLKCTRL); return DIV_ROUND_CLOSEST(UNIPHIER_PRO4_UART_CLK, 16 * CONFIG_BAUDRATE); } diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c index 8e4d15c2913..ef3b383ee43 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c @@ -25,9 +25,9 @@ unsigned int uniphier_pro5_debug_uart_init(void) writel(1, sg_base + SG_LOADPINCTRL); - tmp = readl(SC_CLKCTRL); + tmp = readl(sc_base + SC_CLKCTRL); tmp |= SC_CLKCTRL_CEN_PERI; - writel(tmp, SC_CLKCTRL); + writel(tmp, sc_base + SC_CLKCTRL); return DIV_ROUND_CLOSEST(UNIPHIER_PRO5_UART_CLK, 16 * CONFIG_BAUDRATE); } diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-pxs2.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-pxs2.c index 5d50c4fa244..ee8caad1d45 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart-pxs2.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-pxs2.c @@ -23,9 +23,9 @@ unsigned int uniphier_pxs2_debug_uart_init(void) sg_set_pinsel(113, 8, 8, 4); /* TXD2 -> TXD2 */ sg_set_pinsel(219, 8, 8, 4); /* TXD3 -> TXD3 */ - tmp = readl(SC_CLKCTRL); + tmp = readl(sc_base + SC_CLKCTRL); tmp |= SC_CLKCTRL_CEN_PERI; - writel(tmp, SC_CLKCTRL); + writel(tmp, sc_base + SC_CLKCTRL); return DIV_ROUND_CLOSEST(UNIPHIER_PXS2_UART_CLK, 16 * CONFIG_BAUDRATE); } diff --git a/arch/arm/mach-uniphier/reset.c b/arch/arm/mach-uniphier/reset.c index 28c95e2ce58..31685d00094 100644 --- a/arch/arm/mach-uniphier/reset.c +++ b/arch/arm/mach-uniphier/reset.c @@ -22,14 +22,14 @@ void __SECURE reset_cpu(unsigned long ignored) { u32 tmp; - writel(5, SC_IRQTIMSET); /* default value */ + writel(5, sc_base + SC_IRQTIMSET); /* default value */ - tmp = readl(SC_SLFRSTSEL); + tmp = readl(sc_base + SC_SLFRSTSEL); tmp &= ~0x3; /* mask [1:0] */ tmp |= 0x0; /* XRST reboot */ - writel(tmp, SC_SLFRSTSEL); + writel(tmp, sc_base + SC_SLFRSTSEL); - tmp = readl(SC_SLFRSTCTL); + tmp = readl(sc_base + SC_SLFRSTCTL); tmp |= 0x1; - writel(tmp, SC_SLFRSTCTL); + writel(tmp, sc_base + SC_SLFRSTCTL); } diff --git a/arch/arm/mach-uniphier/sc-regs.h b/arch/arm/mach-uniphier/sc-regs.h index 28de19c039c..e43116e064b 100644 --- a/arch/arm/mach-uniphier/sc-regs.h +++ b/arch/arm/mach-uniphier/sc-regs.h @@ -10,31 +10,36 @@ #ifndef ARCH_SC_REGS_H #define ARCH_SC_REGS_H -#define SC_BASE_ADDR 0x61840000 +#ifndef __ASSEMBLY__ +#include +#define sc_base ((void __iomem *)SC_BASE) +#endif -#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200) +#define SC_BASE 0x61840000 + +#define SC_DPLLCTRL 0x1200 #define SC_DPLLCTRL_SSC_EN (0x1 << 31) #define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16) #define SC_DPLLCTRL_SSC_RATE (0x1 << 15) -#define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204) +#define SC_DPLLCTRL2 0x1204 #define SC_DPLLCTRL2_NRSTDS (0x1 << 28) -#define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208) +#define SC_DPLLCTRL3 0x1208 #define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31) #define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31) -#define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210) +#define SC_UPLLCTRL 0x1210 -#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270) -#define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274) -#define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278) +#define SC_VPLL27ACTRL 0x1270 +#define SC_VPLL27ACTRL2 0x1274 +#define SC_VPLL27ACTRL3 0x1278 -#define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290) -#define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294) -#define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298) +#define SC_VPLL27BCTRL 0x1290 +#define SC_VPLL27BCTRL2 0x1294 +#define SC_VPLL27BCTRL3 0x1298 -#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) +#define SC_RSTCTRL 0x2000 #define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */ #define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */ #define SC_RSTCTRL_NRST_ETHER (0x1 << 12) @@ -44,14 +49,14 @@ #define SC_RSTCTRL_NRST_UMC0 (0x1 << 4) #define SC_RSTCTRL_NRST_NAND (0x1 << 2) -#define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004) +#define SC_RSTCTRL2 0x2004 #define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) /* USB3 #1 bus */ #define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) /* USB3 #1 core */ -#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) +#define SC_RSTCTRL3 0x2008 /* Pro5 or newer */ -#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c) +#define SC_RSTCTRL4 0x200c #define SC_RSTCTRL4_NRST_UMCSB (0x1 << 12) /* UMC system bus */ #define SC_RSTCTRL4_NRST_UMCA2 (0x1 << 10) /* UMC ch2 standby */ #define SC_RSTCTRL4_NRST_UMCA1 (0x1 << 9) /* UMC ch1 standby */ @@ -60,11 +65,11 @@ #define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */ #define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */ -#define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010) +#define SC_RSTCTRL5 0x2010 -#define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014) +#define SC_RSTCTRL6 0x2014 -#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104) +#define SC_CLKCTRL 0x2104 #define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */ #define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */ #define SC_CLKCTRL_CEN_ETHER (0x1 << 12) @@ -76,15 +81,15 @@ #define SC_CLKCTRL_CEN_PERI (0x1 << 0) /* Pro5 or newer */ -#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c) +#define SC_CLKCTRL4 0x210c #define SC_CLKCTRL4_CEN_UMCSB (0x1 << 12) /* UMC system bus */ #define SC_CLKCTRL4_CEN_UMC2 (0x1 << 2) /* UMC ch2 */ #define SC_CLKCTRL4_CEN_UMC1 (0x1 << 1) /* UMC ch1 */ #define SC_CLKCTRL4_CEN_UMC0 (0x1 << 0) /* UMC ch0 */ /* System reset control register */ -#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000) -#define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010) -#define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014) +#define SC_IRQTIMSET 0x3000 +#define SC_SLFRSTSEL 0x3010 +#define SC_SLFRSTCTL 0x3014 #endif /* ARCH_SC_REGS_H */ diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h index 83f34e3faf1..1f3b41a336b 100644 --- a/arch/arm/mach-uniphier/sc64-regs.h +++ b/arch/arm/mach-uniphier/sc64-regs.h @@ -9,28 +9,33 @@ #ifndef SC64_REGS_H #define SC64_REGS_H -#define SC_BASE_ADDR 0x61840000 +#ifndef __ASSEMBLY__ +#include +#define sc_base ((void __iomem *)SC_BASE) +#endif -#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) -#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) -#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c) -#define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010) -#define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014) -#define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018) +#define SC_BASE 0x61840000 -#define SC_CLKCTRL (SC_BASE_ADDR | 0x2100) -#define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108) -#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c) -#define SC_CLKCTRL5 (SC_BASE_ADDR | 0x2110) -#define SC_CLKCTRL6 (SC_BASE_ADDR | 0x2114) -#define SC_CLKCTRL7 (SC_BASE_ADDR | 0x2118) +#define SC_RSTCTRL 0x2000 +#define SC_RSTCTRL3 0x2008 +#define SC_RSTCTRL4 0x200c +#define SC_RSTCTRL5 0x2010 +#define SC_RSTCTRL6 0x2014 +#define SC_RSTCTRL7 0x2018 -#define SC_CA72_GEARST (SC_BASE_ADDR | 0x8000) -#define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8004) -#define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8008) -#define SC_CA53_GEARST (SC_BASE_ADDR | 0x8080) -#define SC_CA53_GEARSET (SC_BASE_ADDR | 0x8084) -#define SC_CA53_GEARUPD (SC_BASE_ADDR | 0x8088) +#define SC_CLKCTRL 0x2100 +#define SC_CLKCTRL3 0x2108 +#define SC_CLKCTRL4 0x210c +#define SC_CLKCTRL5 0x2110 +#define SC_CLKCTRL6 0x2114 +#define SC_CLKCTRL7 0x2118 + +#define SC_CA72_GEARST 0x8000 +#define SC_CA72_GEARSET 0x8004 +#define SC_CA72_GEARUPD 0x8008 +#define SC_CA53_GEARST 0x8080 +#define SC_CA53_GEARSET 0x8084 +#define SC_CA53_GEARUPD 0x8088 #define SC_CA_GEARUPD (1 << 0) #endif /* SC64_REGS_H */ -- cgit v1.2.3 From 34ded875067306961a684186cf23227b58802b28 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:42 +0900 Subject: ARM: uniphier: detect register base addresses run-time Until the last SoC, the register addresses have been hard-coded because they are always constant. For a planned new SoC, the register bases will be completely changed. I insist on supporting multiple SoCs/boards by a single defconfig (uniphier_v8_defconfig) since duplicating similar defconfig files is a maintenance burden. The base addresses must be fixed-up at run-time somehow. Previously, the board init code identified the SoC by reading out the SG_REVISION register. This is much easier than parsing DT. You cannot do it any more because the base address of SG will be changed. The SG_REVISION register exists to read out the SoC ID, but you never know its address before identifying the SoC. Oh well. So, the possible solution is to parse the DT, and find out the node with "*-soc-glue" compatible string. Then, sg_base is set to the value of the "reg" property. The sc_base is set up likewise. It is worth noting a pit-fall. Having sc_base and sg_base in the global scope will make the life easier, but the global variables are poorly supported before the relocation. In fact, the .bss section overwraps with DT. Allocating them in the .bss section would break DT. So, I gave dummy initializers to assign them in the .data section. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/Makefile | 1 + arch/arm/mach-uniphier/base-address.c | 67 +++++++++++++++++++++++++++++++++++ arch/arm/mach-uniphier/base-address.h | 18 ++++++++++ arch/arm/mach-uniphier/cpu-info.c | 6 ++++ arch/arm/mach-uniphier/sc64-regs.h | 2 +- arch/arm/mach-uniphier/sg-regs.h | 4 +++ 6 files changed, 97 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-uniphier/base-address.c create mode 100644 arch/arm/mach-uniphier/base-address.h diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index caa79d1e53e..115af244cd5 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -13,6 +13,7 @@ else obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o obj-y += dram_init.o obj-y += board_init.o +obj-$(CONFIG_ARCH_UNIPHIER_V8_MULTI) += base-address.o obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o ifndef CONFIG_SYSRESET obj-y += reset.o diff --git a/arch/arm/mach-uniphier/base-address.c b/arch/arm/mach-uniphier/base-address.c new file mode 100644 index 00000000000..5ee742e363f --- /dev/null +++ b/arch/arm/mach-uniphier/base-address.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright (C) 2019 Socionext Inc. +// Author: Masahiro Yamada + +#include +#include +#include +#include +#include +#include +#include + +#include "base-address.h" +#include "sc64-regs.h" +#include "sg-regs.h" + +/* + * Dummy initializers are needed to allocate these to .data section instead of + * .bss section. The .bss section is unusable before relocation because the + * .bss section and DT share the same address. Without the initializers, + * DT would be broken. + */ +void __iomem *sc_base = (void *)0xdeadbeef; +void __iomem *sg_base = (void *)0xdeadbeef; + +static u64 uniphier_base_address_get(const char *compat_tail) +{ + DECLARE_GLOBAL_DATA_PTR; + const void *fdt = gd->fdt_blob; + int offset, len, i; + const char *str; + + for (offset = fdt_next_node(fdt, 0, NULL); + offset >= 0; + offset = fdt_next_node(fdt, offset, NULL)) { + for (i = 0; + (str = fdt_stringlist_get(fdt, offset, "compatible", i, &len)); + i++) { + if (!memcmp(compat_tail, + str + len - strlen(compat_tail), + strlen(compat_tail))) + return fdt_get_base_address(fdt, offset); + } + } + + return OF_BAD_ADDR; +} + +int uniphier_base_address_init(void) +{ + u64 base; + + base = uniphier_base_address_get("-soc-glue"); + if (base == OF_BAD_ADDR) + return -EINVAL; + + sg_base = ioremap(base, SZ_8K); + + base = uniphier_base_address_get("-sysctrl"); + if (base == OF_BAD_ADDR) + return -EINVAL; + + sc_base = ioremap(base, SZ_64K); + + return 0; +} diff --git a/arch/arm/mach-uniphier/base-address.h b/arch/arm/mach-uniphier/base-address.h new file mode 100644 index 00000000000..6158ce7d66a --- /dev/null +++ b/arch/arm/mach-uniphier/base-address.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Socionext Inc. + */ + +#ifndef __UNIPHIER_BASE_ADDRESS_H +#define __UNIPHIER_BASE_ADDRESS_H + +#ifdef CONFIG_ARCH_UNIPHIER_V8_MULTI +int uniphier_base_address_init(void); +#else +static inline int uniphier_base_address_init(void) +{ + return 0; +} +#endif + +#endif /* __UNIPHIER_BASE_ADDRESS_H */ diff --git a/arch/arm/mach-uniphier/cpu-info.c b/arch/arm/mach-uniphier/cpu-info.c index 9f5f5051b31..6a7b203a44d 100644 --- a/arch/arm/mach-uniphier/cpu-info.c +++ b/arch/arm/mach-uniphier/cpu-info.c @@ -10,11 +10,17 @@ #include #include +#include "base-address.h" #include "soc-info.h" int print_cpuinfo(void) { unsigned int id, model, rev, required_model = 1, required_rev = 1; + int ret; + + ret = uniphier_base_address_init(); + if (ret) + return ret; id = uniphier_get_soc_id(); model = uniphier_get_soc_model(); diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h index 1f3b41a336b..fdcca232b61 100644 --- a/arch/arm/mach-uniphier/sc64-regs.h +++ b/arch/arm/mach-uniphier/sc64-regs.h @@ -11,7 +11,7 @@ #ifndef __ASSEMBLY__ #include -#define sc_base ((void __iomem *)SC_BASE) +extern void __iomem *sc_base; #endif #define SC_BASE 0x61840000 diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h index cba02d1f4ae..f47d1019498 100644 --- a/arch/arm/mach-uniphier/sg-regs.h +++ b/arch/arm/mach-uniphier/sg-regs.h @@ -12,8 +12,12 @@ #ifndef __ASSEMBLY__ #include +#ifdef CONFIG_ARCH_UNIPHIER_V8_MULTI +extern void __iomem *sg_base; +#else #define sg_base ((void __iomem *)SG_BASE) #endif +#endif /* __ASSEMBLY__ */ /* Base Address */ #define SG_BASE 0x5f800000 -- cgit v1.2.3 From 6f47c99423c67e4cda251ac43a404e16af616ff9 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:43 +0900 Subject: ARM: uniphier: make dram_init() independent of SG_MEMCONF Currently, dram_init() code relies on the fact the DRAM size configuration exists in the SG_MEMCONF register. This will no longer be true for a planned new SoC, which will replace SG_MEMCONF with a different register. Refactor the hook in a more generic way. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/dram_init.c | 148 +++++++++++++++++++++---------------- 1 file changed, 84 insertions(+), 64 deletions(-) diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index eca340b094e..4a75d22db54 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -18,73 +18,17 @@ DECLARE_GLOBAL_DATA_PTR; -struct uniphier_memif_data { - unsigned int soc_id; - unsigned long sparse_ch1_base; - int have_ch2; -}; - -static const struct uniphier_memif_data uniphier_memif_data[] = { - { - .soc_id = UNIPHIER_LD4_ID, - .sparse_ch1_base = 0xc0000000, - }, - { - .soc_id = UNIPHIER_PRO4_ID, - .sparse_ch1_base = 0xa0000000, - }, - { - .soc_id = UNIPHIER_SLD8_ID, - .sparse_ch1_base = 0xc0000000, - }, - { - .soc_id = UNIPHIER_PRO5_ID, - .sparse_ch1_base = 0xc0000000, - }, - { - .soc_id = UNIPHIER_PXS2_ID, - .sparse_ch1_base = 0xc0000000, - .have_ch2 = 1, - }, - { - .soc_id = UNIPHIER_LD6B_ID, - .sparse_ch1_base = 0xc0000000, - .have_ch2 = 1, - }, - { - .soc_id = UNIPHIER_LD11_ID, - .sparse_ch1_base = 0xc0000000, - }, - { - .soc_id = UNIPHIER_LD20_ID, - .sparse_ch1_base = 0xc0000000, - .have_ch2 = 1, - }, - { - .soc_id = UNIPHIER_PXS3_ID, - .sparse_ch1_base = 0xc0000000, - .have_ch2 = 1, - }, -}; -UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_memif_data, uniphier_memif_data) - struct uniphier_dram_map { unsigned long base; unsigned long size; }; -static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map) +static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map, + unsigned long sparse_ch1_base, bool have_ch2) { - const struct uniphier_memif_data *data; unsigned long size; u32 val; - data = uniphier_get_memif_data(); - if (!data) { - pr_err("unsupported SoC\n"); - return -EINVAL; - } - val = readl(sg_base + SG_MEMCONF); /* set up ch0 */ @@ -120,14 +64,14 @@ static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map) dram_map[1].base = dram_map[0].base + size; if (val & SG_MEMCONF_SPARSEMEM) { - if (dram_map[1].base > data->sparse_ch1_base) { + if (dram_map[1].base > sparse_ch1_base) { pr_warn("Sparse mem is enabled, but ch0 and ch1 overlap\n"); pr_warn("Only ch0 is available\n"); dram_map[1].base = 0; return 0; } - dram_map[1].base = data->sparse_ch1_base; + dram_map[1].base = sparse_ch1_base; } switch (val & SG_MEMCONF_CH1_SZ_MASK) { @@ -156,7 +100,7 @@ static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map) dram_map[1].size = size; - if (!data->have_ch2 || val & SG_MEMCONF_CH2_DISABLE) + if (!have_ch2 || val & SG_MEMCONF_CH2_DISABLE) return 0; /* set up ch2 */ @@ -191,6 +135,80 @@ static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map) return 0; } +static int uniphier_ld4_dram_map_get(struct uniphier_dram_map dram_map[]) +{ + return uniphier_memconf_decode(dram_map, 0xc0000000, false); +} + +static int uniphier_pro4_dram_map_get(struct uniphier_dram_map dram_map[]) +{ + return uniphier_memconf_decode(dram_map, 0xa0000000, false); +} + +static int uniphier_pxs2_dram_map_get(struct uniphier_dram_map dram_map[]) +{ + return uniphier_memconf_decode(dram_map, 0xc0000000, true); +} + +struct uniphier_dram_init_data { + unsigned int soc_id; + int (*dram_map_get)(struct uniphier_dram_map dram_map[]); +}; + +static const struct uniphier_dram_init_data uniphier_dram_init_data[] = { + { + .soc_id = UNIPHIER_LD4_ID, + .dram_map_get = uniphier_ld4_dram_map_get, + }, + { + .soc_id = UNIPHIER_PRO4_ID, + .dram_map_get = uniphier_pro4_dram_map_get, + }, + { + .soc_id = UNIPHIER_SLD8_ID, + .dram_map_get = uniphier_ld4_dram_map_get, + }, + { + .soc_id = UNIPHIER_PRO5_ID, + .dram_map_get = uniphier_ld4_dram_map_get, + }, + { + .soc_id = UNIPHIER_PXS2_ID, + .dram_map_get = uniphier_pxs2_dram_map_get, + }, + { + .soc_id = UNIPHIER_LD6B_ID, + .dram_map_get = uniphier_pxs2_dram_map_get, + }, + { + .soc_id = UNIPHIER_LD11_ID, + .dram_map_get = uniphier_ld4_dram_map_get, + }, + { + .soc_id = UNIPHIER_LD20_ID, + .dram_map_get = uniphier_pxs2_dram_map_get, + }, + { + .soc_id = UNIPHIER_PXS3_ID, + .dram_map_get = uniphier_pxs2_dram_map_get, + }, +}; +UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_dram_init_data, + uniphier_dram_init_data) + +static int uniphier_dram_map_get(struct uniphier_dram_map *dram_map) +{ + const struct uniphier_dram_init_data *data; + + data = uniphier_get_dram_init_data(); + if (!data) { + pr_err("unsupported SoC\n"); + return -ENOTSUPP; + } + + return data->dram_map_get(dram_map); +} + int dram_init(void) { struct uniphier_dram_map dram_map[3] = {}; @@ -198,7 +216,7 @@ int dram_init(void) gd->ram_size = 0; - ret = uniphier_memconf_decode(dram_map); + ret = uniphier_dram_map_get(dram_map); if (ret) return ret; @@ -249,9 +267,11 @@ int dram_init(void) int dram_init_banksize(void) { struct uniphier_dram_map dram_map[3] = {}; - int i; + int ret, i; - uniphier_memconf_decode(dram_map); + ret = uniphier_dram_map_get(dram_map); + if (ret) + return ret; for (i = 0; i < ARRAY_SIZE(dram_map); i++) { if (i >= ARRAY_SIZE(gd->bd->bi_dram)) -- cgit v1.2.3 From df72534121b7e593f2a8043ad1c0c86bae0aa75b Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:44 +0900 Subject: ARM: uniphier: make dram_init() more generic Make this function work with any channel being empty. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/dram_init.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 4a75d22db54..ab4aa93f42a 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -212,6 +212,8 @@ static int uniphier_dram_map_get(struct uniphier_dram_map *dram_map) int dram_init(void) { struct uniphier_dram_map dram_map[3] = {}; + bool valid_bank_found = false; + unsigned long prev_top; int ret, i; gd->ram_size = 0; @@ -224,15 +226,14 @@ int dram_init(void) unsigned long max_size; if (!dram_map[i].size) - break; + continue; /* * U-Boot relocates itself to the tail of the memory region, * but it does not expect sparse memory. We use the first * contiguous chunk here. */ - if (i > 0 && dram_map[i - 1].base + dram_map[i - 1].size < - dram_map[i].base) + if (valid_bank_found && prev_top < dram_map[i].base) break; /* @@ -252,6 +253,9 @@ int dram_init(void) } gd->ram_size += dram_map[i].size; + + prev_top = dram_map[i].base + dram_map[i].size; + valid_bank_found = true; } /* -- cgit v1.2.3 From 34e29f7d94aa0243793081751ea0eeae598a0273 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:45 +0900 Subject: ARM: uniphier: make mem_map run-time configurable Currently, mem_map is hard-coded, and it worked well until the last SoC. For a planned new SoC, the addresses of peripherals and DRAM will be changed. Set it up run-time. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/arm64/mem_map.c | 10 ++++++++++ arch/arm/mach-uniphier/dram_init.c | 24 ++++++++++++++++++++---- arch/arm/mach-uniphier/init.h | 8 ++++++++ 3 files changed, 38 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-uniphier/arm64/mem_map.c b/arch/arm/mach-uniphier/arm64/mem_map.c index 35e75e2ab2d..7653bd2d3c6 100644 --- a/arch/arm/mach-uniphier/arm64/mem_map.c +++ b/arch/arm/mach-uniphier/arm64/mem_map.c @@ -7,6 +7,8 @@ #include #include +#include "../init.h" + static struct mm_region uniphier_mem_map[] = { { .virt = 0x00000000, @@ -27,3 +29,11 @@ static struct mm_region uniphier_mem_map[] = { }; struct mm_region *mem_map = uniphier_mem_map; + +void uniphier_mem_map_init(unsigned long dram_base, unsigned long dram_size) +{ + uniphier_mem_map[0].size = dram_base; + uniphier_mem_map[1].virt = dram_base; + uniphier_mem_map[1].phys = dram_base; + uniphier_mem_map[1].size = dram_size; +} diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index ab4aa93f42a..970fa09ef03 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -13,6 +13,7 @@ #include #include +#include "init.h" #include "sg-regs.h" #include "soc-info.h" @@ -271,6 +272,8 @@ int dram_init(void) int dram_init_banksize(void) { struct uniphier_dram_map dram_map[3] = {}; + unsigned long base, top; + bool valid_bank_found = false; int ret, i; ret = uniphier_dram_map_get(dram_map); @@ -278,12 +281,25 @@ int dram_init_banksize(void) return ret; for (i = 0; i < ARRAY_SIZE(dram_map); i++) { - if (i >= ARRAY_SIZE(gd->bd->bi_dram)) - break; + if (i < ARRAY_SIZE(gd->bd->bi_dram)) { + gd->bd->bi_dram[i].start = dram_map[i].base; + gd->bd->bi_dram[i].size = dram_map[i].size; + } + + if (!dram_map[i].size) + continue; - gd->bd->bi_dram[i].start = dram_map[i].base; - gd->bd->bi_dram[i].size = dram_map[i].size; + if (!valid_bank_found) + base = dram_map[i].base; + top = dram_map[i].base + dram_map[i].size; + valid_bank_found = true; } + if (!valid_bank_found) + return -EINVAL; + + /* map all the DRAM regions */ + uniphier_mem_map_init(base, top - base); + return 0; } diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index c6b3f3656cc..b37ab2fa508 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -102,5 +102,13 @@ unsigned int uniphier_boot_device_raw(void); int uniphier_have_internal_stm(void); int uniphier_boot_from_backend(void); int uniphier_pin_init(const char *pinconfig_name); +#ifdef CONFIG_ARM64 +void uniphier_mem_map_init(unsigned long dram_base, unsigned long dram_size); +#else +static inline void uniphier_mem_map_init(unsigned long dram_base, + unsigned long dram_size) +{ +} +#endif #endif /* __MACH_INIT_H */ -- cgit v1.2.3 From 1f8357c3ab27685fa32693ed9cba793932407a69 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:46 +0900 Subject: ARM: uniphier: remove CONFIG_SYS_SDRAM_BASE The base address of DRAM was 0x80000000 for all the ARM SoCs of this family in the past. It will be changed to 0x20000000 for a planned new SoC. To support multiple SoCs by the single uniphier_v8_defconfig, the base must be run-time determined. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/dram_init.c | 5 ++++- include/configs/uniphier.h | 6 ------ 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 970fa09ef03..13821a92883 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -33,7 +33,7 @@ static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map, val = readl(sg_base + SG_MEMCONF); /* set up ch0 */ - dram_map[0].base = CONFIG_SYS_SDRAM_BASE; + dram_map[0].base = 0x80000000; switch (val & SG_MEMCONF_CH0_SZ_MASK) { case SG_MEMCONF_CH0_SZ_64M: @@ -255,6 +255,9 @@ int dram_init(void) gd->ram_size += dram_map[i].size; + if (!valid_bank_found) + gd->ram_base = dram_map[i].base; + prev_top = dram_map[i].base + dram_map[i].size; valid_bank_found = true; } diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 6979165260c..46d576d54aa 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -90,10 +90,6 @@ #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) - /* * Network Configuration */ @@ -215,8 +211,6 @@ #define CONFIG_SYS_BOOTMAPSZ 0x20000000 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) /* only for SPL */ -- cgit v1.2.3 From 72cd83ab81969b970247c6c74e710cdce2c2bdae Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:47 +0900 Subject: ARM: uniphier: turn uniphier_set_fdt_file() into void function For consistency with a function that will be added. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/board_late_init.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index 86b128a91f9..37b375c0198 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -31,24 +31,25 @@ static void nand_denali_wp_disable(void) #endif } -static int uniphier_set_fdt_file(void) +static void uniphier_set_env_fdt_file(void) { DECLARE_GLOBAL_DATA_PTR; const char *compat; char dtb_name[256]; int buf_len = sizeof(dtb_name); + int ret; if (env_get("fdtfile")) - return 0; /* do nothing if it is already set */ + return; /* do nothing if it is already set */ compat = fdt_stringlist_get(gd->fdt_blob, 0, "compatible", 0, NULL); if (!compat) - return -EINVAL; + goto fail; /* rip off the vendor prefix "socionext," */ compat = strchr(compat, ','); if (!compat) - return -EINVAL; + goto fail; compat++; strncpy(dtb_name, compat, buf_len); @@ -56,7 +57,13 @@ static int uniphier_set_fdt_file(void) strncat(dtb_name, ".dtb", buf_len); - return env_set("fdtfile", dtb_name); + ret = env_set("fdtfile", dtb_name); + if (ret) + goto fail; + + return; +fail: + pr_warn("\"fdt_file\" environment variable was not set correctly\n"); } int board_late_init(void) @@ -96,8 +103,7 @@ int board_late_init(void) printf("\n"); - if (uniphier_set_fdt_file()) - pr_warn("fdt_file environment was not set correctly\n"); + uniphier_set_env_fdt_file(); return 0; } -- cgit v1.2.3 From 3cc936d8ab508855b095bbd7fecb02b21cf82f32 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:48 +0900 Subject: ARM: uniphier: set loadaddr at boot-time The base of DRAM will be changed for the next generation SoC. To support it along with existing SoCs in the single defconfig, set 'loadaddr' at boot-time by adding the offset to the DRAM base. CONFIG_SYS_LOAD_ADDR is still hard-coded for compilation, but the value from environment variable 'loadaddr' should be used. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/board_late_init.c | 32 ++++++++++++++++++++++++++++++++ include/configs/uniphier.h | 4 ++-- 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index 37b375c0198..dbd1f17e832 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -66,6 +66,36 @@ fail: pr_warn("\"fdt_file\" environment variable was not set correctly\n"); } +static void uniphier_set_env_addr(const char *env, const char *offset_env) +{ + unsigned long offset = 0; + const char *str; + char *end; + int ret; + + if (env_get(env)) + return; /* do nothing if it is already set */ + + if (offset_env) { + str = env_get(offset_env); + if (!str) + goto fail; + + offset = simple_strtoul(str, &end, 16); + if (*end) + goto fail; + } + + ret = env_set_hex(env, gd->ram_base + offset); + if (ret) + goto fail; + + return; + +fail: + pr_warn("\"%s\" environment variable was not set correctly\n", env); +} + int board_late_init(void) { puts("MODE: "); @@ -105,5 +135,7 @@ int board_late_init(void) uniphier_set_env_fdt_file(); + uniphier_set_env_addr("loadaddr", "loadaddr_offset"); + return 0; } diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 46d576d54aa..6d3d9b31888 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -98,8 +98,7 @@ #define CONFIG_GATEWAYIP 192.168.11.1 #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 0x85000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_LOAD_ADDR 0x85000000 #define CONFIG_SYS_BOOTM_LEN (32 << 20) #if defined(CONFIG_ARM64) @@ -158,6 +157,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "initrd_high=0xffffffffffffffff\0" \ + "loadaddr_offset=0x05000000\0" \ "script=boot.scr\0" \ "scriptaddr=0x85000000\0" \ "nor_base=0x42000000\0" \ -- cgit v1.2.3 From 7095678787d98e51dbaa123d49abdd2d066d45e9 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:49 +0900 Subject: ARM: uniphier: set dram_base environment variable The base of DRAM will be changed for the next generation SoC. Set the base address to the 'dram_base' environment variable, which will be useful for scripting. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/board_late_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index dbd1f17e832..4701a289237 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -135,6 +135,8 @@ int board_late_init(void) uniphier_set_env_fdt_file(); + uniphier_set_env_addr("dram_base", NULL); + uniphier_set_env_addr("loadaddr", "loadaddr_offset"); return 0; -- cgit v1.2.3 From 2ce6b82d340cf1b1e5a43f1b5c8965d0067d5246 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 10 Jul 2019 20:07:50 +0900 Subject: ARM: uniphier: set {kernel, ramdisk, fdt}_addr_r at boot-time The base of DRAM will be changed for the next generation SoC. The addresses needed for booting the kernel should be shifted according to the DRAM base. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/board_late_init.c | 4 ++++ include/configs/uniphier.h | 14 +++++++------- 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index 4701a289237..3180b24330b 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -139,5 +139,9 @@ int board_late_init(void) uniphier_set_env_addr("loadaddr", "loadaddr_offset"); + uniphier_set_env_addr("kernel_addr_r", "kernel_addr_r_offset"); + uniphier_set_env_addr("ramdisk_addr_r", "ramdisk_addr_r_offset"); + uniphier_set_env_addr("fdt_addr_r", "fdt_addr_r_offset"); + return 0; } diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 6d3d9b31888..68568f41224 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -121,8 +121,8 @@ #ifdef CONFIG_FIT #define CONFIG_BOOTFILE "fitImage" +#define KERNEL_ADDR_R_OFFSET "0x05100000" #define LINUXBOOT_ENV_SETTINGS \ - "kernel_addr_r=0x85100000\0" \ "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ "bootm $kernel_addr_r\0" \ "__nfsboot=run tftpboot\0" @@ -130,17 +130,13 @@ #ifdef CONFIG_ARM64 #define CONFIG_BOOTFILE "Image" #define LINUXBOOT_CMD "booti" -#define KERNEL_ADDR_R "kernel_addr_r=0x82080000\0" +#define KERNEL_ADDR_R_OFFSET "0x02080000" #else #define CONFIG_BOOTFILE "zImage" #define LINUXBOOT_CMD "bootz" -#define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0" +#define KERNEL_ADDR_R_OFFSET "0x00208000" #endif #define LINUXBOOT_ENV_SETTINGS \ - "fdt_addr_r=0x85100000\0" \ - KERNEL_ADDR_R \ - "ramdisk_addr_r=0x86000000\0" \ - "ramdisk_file=rootfs.cpio.gz\0" \ "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 && " \ LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ "tftpboot=tftpboot $kernel_addr_r $bootfile && " \ @@ -155,6 +151,10 @@ #endif #define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_addr_r_offset=0x05100000\0" \ + "kernel_addr_r_offset=" KERNEL_ADDR_R_OFFSET "\0" \ + "ramdisk_addr_r_offset=0x06000000\0" \ + "ramdisk_file=rootfs.cpio.gz\0" \ "netdev=eth0\0" \ "initrd_high=0xffffffffffffffff\0" \ "loadaddr_offset=0x05000000\0" \ -- cgit v1.2.3