From 3fafced74df234c708e645a373a70db665e4e6ce Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Tue, 26 Dec 2017 13:55:59 +0800 Subject: riscv: doc: Add relative doc to describe RISC-V Add documents to describe NX25 and AE250. Also update other documents for RISC-V. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Signed-off-by: Greentime Hu --- README | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'README') diff --git a/README b/README index 06f3ed057d5..b53ea7dfe3f 100644 --- a/README +++ b/README @@ -143,6 +143,7 @@ Directory Hierarchy: /nios2 Files generic to Altera NIOS2 architecture /openrisc Files generic to OpenRISC architecture /powerpc Files generic to PowerPC architecture + /riscv Files generic to RISC-V architecture /sandbox Files generic to HW-independent "sandbox" /sh Files generic to SH architecture /x86 Files generic to x86 architecture @@ -3510,7 +3511,7 @@ Low Level (hardware related) configuration options: globally (CONFIG_CMD_MEMORY). - CONFIG_SKIP_LOWLEVEL_INIT - [ARM, NDS32, MIPS only] If this variable is defined, then certain + [ARM, NDS32, MIPS, RISC-V only] If this variable is defined, then certain low level initializations (like setting up the memory controller) are omitted and/or U-Boot does not relocate itself into RAM. @@ -4964,6 +4965,22 @@ On NDS32, the following registers are used: NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope, or current versions of GCC may "optimize" the code too much. +On RISC-V, the following registers are used: + + x0: hard-wired zero (zero) + x1: return address (ra) + x2: stack pointer (sp) + x3: global pointer (gp) + x4: thread pointer (tp) + x5: link register (t0) + x8: frame pointer (fp) + x10-x11: arguments/return values (a0-1) + x12-x17: arguments (a2-7) + x28-31: temporaries (t3-6) + pc: program counter (pc) + + ==> U-Boot will use gp to hold a pointer to the global data + Memory Management: ------------------ -- cgit v1.2.3