From 38c9f08b41ed9e6625b56320b78d4954cbf5fae6 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Thu, 15 Aug 2019 14:29:37 -0500 Subject: clk: aspeed: Add support for SD clock Add code to enable the SD clock on the ast2500 SoC. Reviewed-by: Cédric Le Goater Signed-off-by: Eddie James --- arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h index 4988ced7ddc..8db4901cc9b 100644 --- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h @@ -22,6 +22,8 @@ #define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT) #define SCU_PCLK_DIV_SHIFT 23 #define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT) +#define SCU_SDCLK_DIV_SHIFT 12 +#define SCU_SDCLK_DIV_MASK (7 << SCU_SDCLK_DIV_SHIFT) #define SCU_HPLL_DENUM_SHIFT 0 #define SCU_HPLL_DENUM_MASK 0x1f #define SCU_HPLL_NUM_SHIFT 5 @@ -107,6 +109,7 @@ #define SCU_CLKSTOP_MAC1 (1 << 20) #define SCU_CLKSTOP_MAC2 (1 << 21) +#define SCU_CLKSTOP_SDCLK (1 << 27) #define SCU_D2PLL_EXT1_OFF (1 << 0) #define SCU_D2PLL_EXT1_BYPASS (1 << 1) -- cgit v1.2.3