From 69fdf900105d9f730b526c760c082d1f6641a489 Mon Sep 17 00:00:00 2001 From: Liu Gang Date: Tue, 7 May 2013 16:30:50 +0800 Subject: powerpc/t4qds: Slave module for boot from SRIO and PCIE When a T4 board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang Signed-off-by: Andy Fleming --- arch/powerpc/include/asm/immap_85xx.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/powerpc') diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 8545a0c42bd..db70d048f5b 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1839,6 +1839,7 @@ typedef struct ccsr_gur { #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3 +#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25 -- cgit v1.2.3