From e622d9ed3b4a44cd5646654ba12dd6894fd49382 Mon Sep 17 00:00:00 2001 From: gaurav rana Date: Thu, 26 Mar 2015 15:52:47 +0530 Subject: powerpc/T104xD4: Add Secure boot support for T104xD4RDB platforms defconfig files are added and SFP version for these platforms is updated. Signed-off-by: Gaurav Rana Reviewed-by: York Sun --- arch/powerpc/include/asm/config_mpc85xx.h | 1 + arch/powerpc/include/asm/fsl_secure_boot.h | 2 ++ 2 files changed, 3 insertions(+) (limited to 'arch/powerpc') diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 9d56bc17732..7878c87d77a 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -806,6 +806,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_SFP_VER_3_0 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 8f794ef3812..7810ae21473 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -37,7 +37,9 @@ defined(CONFIG_T2080QDS) || \ defined(CONFIG_T2080RDB) || \ defined(CONFIG_T1040QDS) || \ + defined(CONFIG_T104xD4QDS) || \ defined(CONFIG_T104xRDB) || \ + defined(CONFIG_T104xD4RDB) || \ defined(CONFIG_PPC_T1023) || \ defined(CONFIG_PPC_T1024) #define CONFIG_SYS_CPC_REINIT_F -- cgit v1.2.3 From b99b6452bce169df009a1e99b5b5e25b3320cacc Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Thu, 14 May 2015 16:51:39 +0800 Subject: powerpc/t1024: update fman liodn for mac1 MAC1 acts as 1G/10G dual-role MAC on T1024. We introduce macro SET_FMAN_RX_10G_TYPE2_LIODN for 10G MACs which have same Port ID and same offset of address with 1G MAC. Update it to match with the setting of fman in t1024 device tree, otherwise there is no 'fsl,liodn' in /proc/device-tree/soc@ffe000000/fman@400000/port@88000/ Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/t1024_ids.c | 3 +-- arch/powerpc/include/asm/fsl_liodn.h | 6 ++++++ 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'arch/powerpc') diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c b/arch/powerpc/cpu/mpc85xx/t1024_ids.c index 132689b26eb..8a1092ea655 100644 --- a/arch/powerpc/cpu/mpc85xx/t1024_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1024_ids.c @@ -51,11 +51,10 @@ int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN struct liodn_id_table fman1_liodn_tbl[] = { - SET_FMAN_RX_1G_LIODN(1, 0, 88), + SET_FMAN_RX_10G_TYPE2_LIODN(1, 0, 88), SET_FMAN_RX_1G_LIODN(1, 1, 89), SET_FMAN_RX_1G_LIODN(1, 2, 90), SET_FMAN_RX_1G_LIODN(1, 3, 91), - SET_FMAN_RX_10G_LIODN(1, 0, 94), }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); #endif diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 811f0342935..6206bee5d33 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -145,6 +145,12 @@ extern void fdt_fixup_liodn(void *blob); FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \ +/* enetNum is 0, 1, 2... so we + 8 for type-2 10g to get to HW Port ID */ +#define SET_FMAN_RX_10G_TYPE2_LIODN(fmNum, enetNum, liodn) \ + SET_LIODN_ENTRY_1("fsl,fman-port-10g-rx", liodn, \ + FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ + CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) \ + /* * handle both old and new versioned SEC properties: * "fsl,secX.Y" became "fsl,sec-vX.Y" during development -- cgit v1.2.3 From 1ff10a87c32acf8ec4e8676c4e01dbcc8b255ec3 Mon Sep 17 00:00:00 2001 From: Nikhil Badola Date: Thu, 21 May 2015 09:07:53 +0530 Subject: powerpc/mpc85xx: Correct CONFIG_USB_MAX_CONTROLLER_COUNT for p1025 Correct the value CONFIG_USB_MAX_CONTROLLER_COUNT macro to 1 for p1025 as it has one USB controller Signed-off-by: Nikhil Badola Reviewed-by: York Sun --- arch/powerpc/include/asm/config_mpc85xx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/powerpc') diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 7878c87d77a..7a5487be884 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -334,7 +334,7 @@ #elif defined(CONFIG_P1025) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM -- cgit v1.2.3 From 467a40dfe35f48d830f01a72617207d03ca85b4d Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 16 Jun 2015 10:36:00 +0530 Subject: powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 Secure Boot Target is added for NAND for P3041. For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on SRAM configured at address 0xBFF00000. In the U-Boot code, TLB entries are created to map the virtual address 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. Signed-off-by: Saksham Jain Signed-off-by: Ruchika Gupta Signed-off-by: Aneesh Bansal Reviewed-by: York Sun --- Makefile | 4 ++++ arch/powerpc/cpu/mpc85xx/start.S | 11 +++++++++++ arch/powerpc/include/asm/fsl_secure_boot.h | 5 +++++ board/freescale/common/p_corenet/tlb.c | 15 +++++++++++++++ board/freescale/corenet_ds/MAINTAINERS | 5 +++++ configs/P3041DS_NAND_SECURE_BOOT_defconfig | 5 +++++ include/configs/corenet_ds.h | 8 ++++++++ 7 files changed, 53 insertions(+) create mode 100644 configs/P3041DS_NAND_SECURE_BOOT_defconfig (limited to 'arch/powerpc') diff --git a/Makefile b/Makefile index 54ef2cd1a04..a95d0e33866 100644 --- a/Makefile +++ b/Makefile @@ -738,8 +738,12 @@ ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin ifeq ($(CONFIG_SPL_FSL_PBL),y) ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin else +ifneq ($(CONFIG_SECURE_BOOT), y) +# For Secure Boot The Image needs to be signed and Header must also +# be included. So The image has to be built explicitly ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl endif +endif ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index e61d8e0fc2b..a70fb711c7b 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1052,6 +1052,17 @@ create_init_ram_area: CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 + +#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT) + /* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE + * to L3 Address configured by PBL for ISBC code + */ + create_tlb1_entry 15, \ + 1, BOOKE_PAGESZ_1M, \ + CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ + CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 + #else /* * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 7810ae21473..442853c2391 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -48,6 +48,11 @@ #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 #endif +#if defined(CONFIG_RAMBOOT_PBL) +#undef CONFIG_SYS_INIT_L3_ADDR +#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#endif + #if defined(CONFIG_C29XPCIE) #define CONFIG_KEY_REVOCATION #endif diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index 8148e46efa6..56e4f633483 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -43,6 +43,8 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + +#if !defined(CONFIG_SECURE_BOOT) /* * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the * SRAM is at 0xfff00000, it covered the 0xfffff000. @@ -50,6 +52,19 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), +#else + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot + * the physical address of the SRAM is at CONFIG_SYS_INIT_L3_ADDR, + * and virtual address is CONFIG_SYS_MONITOR_BASE + */ + + SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE & 0xfff00000, + CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#endif + #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS index 745847cdbaa..6855446ca82 100644 --- a/board/freescale/corenet_ds/MAINTAINERS +++ b/board/freescale/corenet_ds/MAINTAINERS @@ -28,3 +28,8 @@ F: configs/P5040DS_NAND_defconfig F: configs/P5040DS_SDCARD_defconfig F: configs/P5040DS_SPIFLASH_defconfig F: configs/P5040DS_SECURE_BOOT_defconfig + +CORENET_DS_SECURE_BOOT BOARD +M: Aneesh Bansal +S: Maintained +F: configs/P3041DS_NAND_SECURE_BOOT_defconfig diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig new file mode 100644 index 00000000000..2f18bc17775 --- /dev/null +++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig @@ -0,0 +1,5 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P3041DS=y +CONFIG_SPI_FLASH=y diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 88750e057e8..7c8b73d06c3 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -16,6 +16,13 @@ #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_RAMBOOT_PBL +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#ifdef CONFIG_NAND +#define CONFIG_RAMBOOT_NAND +#endif +#else #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg @@ -29,6 +36,7 @@ #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg #endif #endif +#endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -- cgit v1.2.3 From 5050f6f0e56af0e02c3e362d9af2b628d6c8da12 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 16 Jun 2015 10:36:43 +0530 Subject: powerpc/mpc85xx: SECURE BOOT-Copy Boot Script on RAM For running Chain of Trust when doing Secure Boot from NAND, the Bootscript header and bootscript must be copied from NAND to RAM(DDR). The addresses and commands for the same have been defined. Signed-off-by: Saksham Jain Signed-off-by: Ruchika Gupta Signed-off-by: Aneesh Bansal Reviewed-by: York Sun --- arch/powerpc/include/asm/fsl_secure_boot.h | 14 ++++++++++++++ include/config_fsl_secboot.h | 29 ++++++++++++++++++++++++++++- include/configs/corenet_ds.h | 1 + 3 files changed, 43 insertions(+), 1 deletion(-) (limited to 'arch/powerpc') diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 442853c2391..d57bb556927 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -75,6 +75,18 @@ #endif #ifndef CONFIG_FIT_SIGNATURE +/* If Boot Script is not on NOR and is required to be copied on RAM */ +#ifdef CONFIG_BOOTSCRIPT_COPY_RAM +#define CONFIG_BS_HDR_ADDR_RAM 0x00010000 +#define CONFIG_BS_HDR_ADDR_FLASH 0x00800000 +#define CONFIG_BS_HDR_SIZE 0x00002000 +#define CONFIG_BS_ADDR_RAM 0x00012000 +#define CONFIG_BS_ADDR_FLASH 0x00802000 +#define CONFIG_BS_SIZE 0x00001000 + +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM +#else + /* The bootscript header address is different for B4860 because the NOR * mapping is different on B4 due to reduced NOR size. */ @@ -90,6 +102,8 @@ #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000 #endif +#endif + #include #endif diff --git a/include/config_fsl_secboot.h b/include/config_fsl_secboot.h index 050b1579021..fc6788a7a61 100644 --- a/include/config_fsl_secboot.h +++ b/include/config_fsl_secboot.h @@ -55,6 +55,22 @@ /* For secure boot flow, default environment used will be used */ #if defined(CONFIG_SYS_RAMBOOT) +#ifdef CONFIG_BOOTSCRIPT_COPY_RAM +#define CONFIG_BS_COPY_ENV \ + "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \ + "setenv bs_hdr_flash " __stringify(CONFIG_BS_HDR_ADDR_FLASH)";" \ + "setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \ + "setenv bs_ram " __stringify(CONFIG_BS_ADDR_RAM)";" \ + "setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \ + "setenv bs_size " __stringify(CONFIG_BS_SIZE)";" + +#if defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_BS_COPY_CMD \ + "nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \ + "nand read $bs_ram $bs_flash $bs_size ;" +#endif /* CONFIG_RAMBOOT_NAND */ +#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ + #if defined(CONFIG_RAMBOOT_SPIFLASH) #undef CONFIG_ENV_IS_IN_SPI_FLASH #elif defined(CONFIG_RAMBOOT_NAND) @@ -68,6 +84,17 @@ #define CONFIG_ENV_IS_NOWHERE +#ifndef CONFIG_BS_COPY_ENV +#define CONFIG_BS_COPY_ENV +#endif + +#ifndef CONFIG_BS_COPY_CMD +#define CONFIG_BS_COPY_CMD +#endif + +#define CONFIG_SECBOOT_CMD CONFIG_BS_COPY_ENV \ + CONFIG_BS_COPY_CMD \ + CONFIG_SECBOOT /* * We don't want boot delay for secure boot flow * before autoboot starts @@ -75,7 +102,7 @@ #undef CONFIG_BOOTDELAY #define CONFIG_BOOTDELAY 0 #undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND CONFIG_SECBOOT +#define CONFIG_BOOTCOMMAND CONFIG_SECBOOT_CMD /* * CONFIG_ZERO_BOOTDELAY_CHECK should not be defined for diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 7c8b73d06c3..9aaa0f533b8 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -22,6 +22,7 @@ #ifdef CONFIG_NAND #define CONFIG_RAMBOOT_NAND #endif +#define CONFIG_BOOTSCRIPT_COPY_RAM #else #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -- cgit v1.2.3 From 4bf7f908250f21bb0ea6b81f36e115914167790a Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Wed, 29 Jul 2015 11:28:36 +0800 Subject: powerpc/t4240: update serdes table Serdes Lanes availability on T4160 and T4080 are same, which serdes 2 & 3 support 8 Lanes, but serdes 1 & 4 support only 4 Lanes E/F/G/H, Lanes A/B/C/D are not available, updated the serdes table accordingly with some minor fix. Signed-off-by: Shaohui Xie Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 103 +++++++++++++++----------------- 1 file changed, 48 insertions(+), 55 deletions(-) (limited to 'arch/powerpc') diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c index 74c4c81887c..7b43b282bb6 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -214,8 +214,8 @@ static const struct serdes_config serdes3_cfg_tbl[] = { {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}}, {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}}, - {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} }, - {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}}, + {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, + {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}}, {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, @@ -266,37 +266,30 @@ static const struct serdes_config serdes4_cfg_tbl[] = { #elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080) static const struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ - {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, - XAUI_FM1_MAC9, XAUI_FM1_MAC9, + {1, {NONE, NONE, NONE, NONE, XAUI_FM1_MAC10, XAUI_FM1_MAC10, XAUI_FM1_MAC10, XAUI_FM1_MAC10} }, - {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, - HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + {2, {NONE, NONE, NONE, NONE, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} }, - {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, - HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + {4, {NONE, NONE, NONE, NONE, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} }, - {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, - SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + {27, {NONE, NONE, NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, - {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, - SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + {28, {NONE, NONE, NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, - {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, - SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + {35, {NONE, NONE, NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, - {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, - SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + {36, {NONE, NONE, NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, - {37, {NONE, NONE, QSGMII_FM1_B, NONE, + {37, {NONE, NONE, NONE, NONE, NONE, NONE, QSGMII_FM1_A, NONE} }, - {38, {NONE, NONE, QSGMII_FM1_B, NONE, + {38, {NONE, NONE, NONE, NONE, NONE, NONE, QSGMII_FM1_A, NONE} }, {} }; @@ -363,45 +356,45 @@ static const struct serdes_config serdes2_cfg_tbl[] = { SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {37, {NONE, NONE, QSGMII_FM2_B, NONE, - NONE, QSGMII_FM1_A, NONE, NONE} }, + NONE, NONE, QSGMII_FM2_A, NONE} }, {38, {NONE, NONE, QSGMII_FM2_B, NONE, - NONE, QSGMII_FM1_A, NONE, NONE} }, + NONE, NONE, QSGMII_FM2_A, NONE} }, {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - NONE, QSGMII_FM1_A, NONE, NONE} }, + NONE, NONE, QSGMII_FM2_A, NONE} }, {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - NONE, QSGMII_FM1_A, NONE, NONE} }, + NONE, NONE, QSGMII_FM2_A, NONE} }, {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - NONE, QSGMII_FM1_A, NONE, NONE} }, + NONE, NONE, QSGMII_FM2_A, NONE} }, {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - NONE, QSGMII_FM1_A, NONE, NONE} }, + NONE, NONE, QSGMII_FM2_A, NONE} }, {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - NONE, QSGMII_FM1_A, NONE, NONE} }, + NONE, NONE, QSGMII_FM2_A, NONE} }, {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - NONE, QSGMII_FM1_A, NONE, NONE} }, + NONE, NONE, QSGMII_FM2_A, NONE} }, {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, - NONE, NONE, NONE, NONE} }, + NONE, NONE, QSGMII_FM2_A, NONE} }, {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, - NONE, NONE, NONE, NONE} }, + NONE, NONE, QSGMII_FM2_A, NONE} }, {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - NONE, NONE, NONE, NONE} }, + NONE, NONE, QSGMII_FM2_A, NONE} }, {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - NONE, NONE, NONE, NONE} }, + NONE, NONE, QSGMII_FM2_A, NONE} }, {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - NONE, NONE, NONE, NONE} }, + NONE, NONE, QSGMII_FM2_A, NONE} }, {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - NONE, NONE, NONE, NONE} }, + NONE, NONE, QSGMII_FM2_A, NONE} }, {55, {NONE, XFI_FM1_MAC10, XFI_FM2_MAC10, NONE, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, @@ -424,51 +417,51 @@ static const struct serdes_config serdes3_cfg_tbl[] = { {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, - {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} }, - {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} }, + {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, + {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} }, {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} }, - {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + {11, {NONE, NONE, NONE, NONE, PCIE2, PCIE2, PCIE2, PCIE2} }, - {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + {12, {NONE, NONE, NONE, NONE, PCIE2, PCIE2, PCIE2, PCIE2} }, {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, PCIE2, PCIE2, PCIE2, PCIE2} }, {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, PCIE2, PCIE2, PCIE2, PCIE2} }, - {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + {15, {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1} }, - {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + {16, {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1} }, - {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + {17, {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1} }, {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, SRIO1, SRIO1, SRIO1, SRIO1} }, {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, SRIO1, SRIO1, SRIO1, SRIO1} }, {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, - NONE, NONE, NONE, NONE} }, + SRIO1, SRIO1, SRIO1, SRIO1} }, {} }; static const struct serdes_config serdes4_cfg_tbl[] = { /* SerDes 4 */ - {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} }, - {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} }, - {5, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, - {6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, - {7, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, - {8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, - {9, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} }, - {10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} }, - {11, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} }, - {12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} }, - {13, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, - {14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, - {15, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, - {16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, - {18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} }, + {3, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} }, + {4, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} }, + {5, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} }, + {6, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} }, + {7, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} }, + {8, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} }, + {9, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} }, + {10, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} }, + {11, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} }, + {12, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} }, + {13, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} }, + {14, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} }, + {15, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} }, + {16, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} }, + {18, {NONE, NONE, NONE, NONE, AURORA, AURORA, AURORA, AURORA} }, {} } ; -- cgit v1.2.3