From d04a46426b92cc175a73e5d2c5220503c428fc6c Mon Sep 17 00:00:00 2001 From: Sagar Shrikant Kadam Date: Wed, 29 Jul 2020 02:36:13 -0700 Subject: sifive: reset: add DM based reset driver for SiFive SoC's PRCI module within SiFive SoC's has register with which we can reset the sub-systems within the SoC. The resets to DDR and ethernet sub systems within FU540-C000 SoC are active low, and are hold low by default on power-up. Currently these are directly asserted within prci driver via register read/write. With the DM based reset driver support here, we bind the reset driver with clock (prci) driver and assert the reset signals of both sub-system's appropriately. Signed-off-by: Sagar Shrikant Kadam Reviewed-by: Pragnesh Patel Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/riscv/include/asm/arch-fu540/reset.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 arch/riscv/include/asm/arch-fu540/reset.h (limited to 'arch/riscv') diff --git a/arch/riscv/include/asm/arch-fu540/reset.h b/arch/riscv/include/asm/arch-fu540/reset.h new file mode 100644 index 00000000000..e42797a3958 --- /dev/null +++ b/arch/riscv/include/asm/arch-fu540/reset.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2020 SiFive, Inc. + * + * Author: Sagar Kadam + */ + +#ifndef __RESET_SIFIVE_H +#define __RESET_SIFIVE_H + +int sifive_reset_bind(struct udevice *dev, ulong count); + +#endif -- cgit v1.2.3