From cefd764222ee0d030b90e594f84eddeac7b9b423 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 24 Aug 2015 11:03:50 +0200 Subject: arm: mvebu: Fix internal register config on A38x Currently booting on A38x is broken. As the current code tries to detect the SoC family to disable the MMU for the A38x at runtime. But before the internal registers are switched to the new location (0xf100.0000), this runtime detection does not work. As all macros / defines are already assigned to the new location at 0xf100.0000. But the registers are sill mapped to the default location at 0xd000.0000. This patch now makes sure, no such runtime detection is used before the internal registers are configured to the new location. After this, the remaining cache cleanup is executed. Signed-off-by: Stefan Roese Reported-by: Kevin Smith Cc: Luka Perkov --- arch/arm/mach-mvebu/cpu.c | 36 ++++++++++++++++++++++-------------- 1 file changed, 22 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index ea83e21d433..efd4d04ea85 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -214,32 +214,40 @@ static void setup_usb_phys(void) int arch_cpu_init(void) { -#ifndef CONFIG_SPL_BUILD +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMADA_38X) + /* + * Only with disabled MMU its possible to switch the base + * register address on Armada 38x. Without this the SDRAM + * located at >= 0x4000.0000 is also not accessible, as its + * still locked to cache. + */ + mmu_disable(); +#endif + + /* Linux expects the internal registers to be at 0xf1000000 */ + writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); + set_cbar(SOC_REGS_PHY_BASE + 0xC000); + +#if !defined(CONFIG_SPL_BUILD) + /* + * From this stage on, the SoC detection is working. As we have + * configured the internal register base to the value used + * in the macros / defines in the U-Boot header (soc.h). + */ if (mvebu_soc_family() == MVEBU_SOC_A38X) { struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; /* - * Only with disabled MMU its possible to switch the base - * register address on Armada 38x. Without this the SDRAM - * located at >= 0x4000.0000 is also not accessible, as its - * still locked to cache. - * - * So to fully release / unlock this area from cache, we need - * to first flush all caches, then disable the MMU and - * disable the L2 cache. + * To fully release / unlock this area from cache, we need + * to flush all caches and disable the L2 cache. */ icache_disable(); dcache_disable(); - mmu_disable(); clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } #endif - /* Linux expects the internal registers to be at 0xf1000000 */ - writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); - set_cbar(SOC_REGS_PHY_BASE + 0xC000); - /* * We need to call mvebu_mbus_probe() before calling * update_sdram_window_sizes() as it disables all previously -- cgit v1.2.3 From 787ddb7cd141bda9f0c4818023a2fd684053c15a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 3 Sep 2015 12:47:07 +0200 Subject: arm: mvebu: timer.c: Explicitly move "init_done" var to data section As reported by Simon Guinot, commit ade741b3 "arm: mvebu: Call timer_init early before PHY and DDR init" breaks Kirkwood platforms. As the static variable "init_done" is not available at that early boot time. This patch moves it to explicitly to the data section, making it available at that time. Signed-off-by: Stefan Roese Reported-by: Simon Guinot Cc: Luka Perkov Tested-by: Simon Guinot --- arch/arm/mach-mvebu/timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/timer.c b/arch/arm/mach-mvebu/timer.c index c516c419eda..5449a8926c5 100644 --- a/arch/arm/mach-mvebu/timer.c +++ b/arch/arm/mach-mvebu/timer.c @@ -41,7 +41,7 @@ #define timestamp gd->arch.tbl #define lastdec gd->arch.lastinc -static int init_done; +static int init_done __attribute__((section(".data"))) = 0; /* Timer reload and current value registers */ struct kwtmr_val { -- cgit v1.2.3