From 4a5a7fcac24498aa1535a467f0739e2fda5b4324 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 18 Oct 2017 18:20:53 -0700 Subject: x86: braswell: Fix unexpected crash during Linux kernel boot It was observed that when booting Linux kernel on Intel Cherry Hill board, unexpected crash happens quite randomly. Sometimes kernel just oops, while sometimes kernel throws MCE errors and hangs: mce: [Hardware Error]: Machine check events logged mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 4: c400000000010151 mce: [Hardware Error]: TSC 0 ADDR 130f3f2c0 mce: [Hardware Error]: PROCESSOR 0:406c3 TIME 1508160686 SOCKET 0 APIC 0 microcode 363 This looks like a hardware error per mcelog. After debugging, it seems turning off turbo mode on the processor does not expose this behavior, although U-Boot runs OK with turbo mode on. Suspect it is related to an errata of Braswell processor. To fix this, remove the Braswell cpu driver which does the turbo mode configuration, and switch to use the generic cpu-x86 driver. Also there is a configuration option in the FSP that turns on the turbo mode and that has been turned off too. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/cpu/braswell/Makefile | 2 +- arch/x86/cpu/braswell/cpu.c | 170 ----------------------------------------- arch/x86/dts/cherryhill.dts | 9 +-- 3 files changed, 5 insertions(+), 176 deletions(-) delete mode 100644 arch/x86/cpu/braswell/cpu.c (limited to 'arch') diff --git a/arch/x86/cpu/braswell/Makefile b/arch/x86/cpu/braswell/Makefile index ddf6d2804a5..4a639b83f50 100644 --- a/arch/x86/cpu/braswell/Makefile +++ b/arch/x86/cpu/braswell/Makefile @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += braswell.o cpu.o early_uart.o fsp_configs.o +obj-y += braswell.o early_uart.o fsp_configs.o diff --git a/arch/x86/cpu/braswell/cpu.c b/arch/x86/cpu/braswell/cpu.c deleted file mode 100644 index 6ff90365975..00000000000 --- a/arch/x86/cpu/braswell/cpu.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright (C) 2017, Bin Meng - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Derived from arch/x86/cpu/baytrail/cpu.c - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static const unsigned int braswell_bus_freq_table[] = { - 83333333, - 100000000, - 133333333, - 116666666, - 80000000, - 93333333, - 90000000, - 88900000, - 87500000 -}; - -static unsigned int braswell_bus_freq(void) -{ - msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL); - - if ((clk_info.lo & 0xf) < (ARRAY_SIZE(braswell_bus_freq_table))) - return braswell_bus_freq_table[clk_info.lo & 0xf]; - - return 0; -} - -static unsigned long braswell_tsc_freq(void) -{ - msr_t platform_info; - ulong bclk = braswell_bus_freq(); - - if (!bclk) - return 0; - - platform_info = msr_read(MSR_PLATFORM_INFO); - - return bclk * ((platform_info.lo >> 8) & 0xff); -} - -static int braswell_get_info(struct udevice *dev, struct cpu_info *info) -{ - info->cpu_freq = braswell_tsc_freq(); - info->features = (1 << CPU_FEAT_L1_CACHE) | (1 << CPU_FEAT_MMU); - - return 0; -} - -static int braswell_get_count(struct udevice *dev) -{ - int ecx = 0; - - /* - * Use the algorithm described in Intel 64 and IA-32 Architectures - * Software Developer's Manual Volume 3 (3A, 3B & 3C): System - * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping - * of CPUID Extended Topology Leaf. - */ - while (1) { - struct cpuid_result leaf_b; - - leaf_b = cpuid_ext(0xb, ecx); - - /* - * Braswell doesn't have hyperthreading so just determine the - * number of cores by from level type (ecx[15:8] == * 2) - */ - if ((leaf_b.ecx & 0xff00) == 0x0200) - return leaf_b.ebx & 0xffff; - - ecx++; - } - - return 0; -} - -static void braswell_set_max_freq(void) -{ - msr_t perf_ctl; - msr_t msr; - - /* Enable speed step */ - msr = msr_read(MSR_IA32_MISC_ENABLES); - msr.lo |= (1 << 16); - msr_write(MSR_IA32_MISC_ENABLES, msr); - - /* Enable Burst Mode */ - msr = msr_read(MSR_IA32_MISC_ENABLES); - msr.hi = 0; - msr_write(MSR_IA32_MISC_ENABLES, msr); - - /* - * Set guaranteed ratio [21:16] from IACORE_TURBO_RATIOS to - * bits [15:8] of the PERF_CTL - */ - msr = msr_read(MSR_IACORE_TURBO_RATIOS); - perf_ctl.lo = (msr.lo & 0x3f0000) >> 8; - - /* - * Set guaranteed vid [22:16] from IACORE_TURBO_VIDS to - * bits [7:0] of the PERF_CTL - */ - msr = msr_read(MSR_IACORE_TURBO_VIDS); - perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; - - perf_ctl.hi = 0; - msr_write(MSR_IA32_PERF_CTL, perf_ctl); -} - -static int braswell_probe(struct udevice *dev) -{ - debug("Init Braswell core\n"); - - /* - * On Braswell the turbo disable bit is actually scoped at the - * building-block level, not package. For non-BSP cores that are - * within a building block, enable turbo. The cores within the BSP's - * building block will just see it already enabled and move on. - */ - if (lapicid()) - turbo_enable(); - - /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ - msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f080f, 0xe0008), - msr_clrsetbits_64(MSR_POWER_MISC, - ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK, 0); - - /* Disable C1E */ - msr_clrsetbits_64(MSR_POWER_CTL, 2, 0); - msr_setbits_64(MSR_POWER_MISC, 0x44); - - /* Set this core to max frequency ratio */ - braswell_set_max_freq(); - - return 0; -} - -static const struct udevice_id braswell_ids[] = { - { .compatible = "intel,braswell-cpu" }, - { } -}; - -static const struct cpu_ops braswell_ops = { - .get_desc = cpu_x86_get_desc, - .get_info = braswell_get_info, - .get_count = braswell_get_count, - .get_vendor = cpu_x86_get_vendor, -}; - -U_BOOT_DRIVER(cpu_x86_braswell_drv) = { - .name = "cpu_x86_braswell", - .id = UCLASS_CPU, - .of_match = braswell_ids, - .bind = cpu_x86_bind, - .probe = braswell_probe, - .ops = &braswell_ops, -}; diff --git a/arch/x86/dts/cherryhill.dts b/arch/x86/dts/cherryhill.dts index 1ccb6059911..840a6699568 100644 --- a/arch/x86/dts/cherryhill.dts +++ b/arch/x86/dts/cherryhill.dts @@ -37,28 +37,28 @@ cpu@0 { device_type = "cpu"; - compatible = "intel,braswell-cpu"; + compatible = "cpu-x86"; reg = <0>; intel,apic-id = <0>; }; cpu@1 { device_type = "cpu"; - compatible = "intel,braswell-cpu"; + compatible = "cpu-x86"; reg = <1>; intel,apic-id = <2>; }; cpu@2 { device_type = "cpu"; - compatible = "intel,braswell-cpu"; + compatible = "cpu-x86"; reg = <2>; intel,apic-id = <4>; }; cpu@3 { device_type = "cpu"; - compatible = "intel,braswell-cpu"; + compatible = "cpu-x86"; reg = <3>; intel,apic-id = <6>; }; @@ -194,7 +194,6 @@ fsp,pmic-i2c-bus = <0>; fsp,enable-isp; fsp,isp-pci-dev-config = ; - fsp,turbo-mode; fsp,pnp-settings = ; fsp,sd-detect-chk; }; -- cgit v1.2.3 From 3a856473fdb05f8c20686f6240781ecb2c0c1b61 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 18 Oct 2017 18:20:54 -0700 Subject: env: x86: braswell: Set ENV_IS_IN_SPI_FLASH as default Imply does not work for a Kconfig choice. Update ENV_IS_IN_SPI_FLASH to be the default one for Intel Braswell. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/cpu/braswell/Kconfig | 1 - env/Kconfig | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/cpu/braswell/Kconfig b/arch/x86/cpu/braswell/Kconfig index 0e214a7432c..616f2287883 100644 --- a/arch/x86/cpu/braswell/Kconfig +++ b/arch/x86/cpu/braswell/Kconfig @@ -12,7 +12,6 @@ config INTEL_BRASWELL imply HAVE_INTEL_ME imply HAVE_VBT imply ENABLE_MRC_CACHE - imply ENV_IS_IN_SPI_FLASH imply AHCI_PCI imply ICH_SPI imply MMC diff --git a/env/Kconfig b/env/Kconfig index 02cb7cbb751..8c9d800f485 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -16,6 +16,7 @@ choice default ENV_IS_IN_FLASH if SH && !CPU_SH4 default ENV_IS_IN_SPI_FLASH if ARMADA_XP default ENV_IS_IN_SPI_FLASH if INTEL_BAYTRAIL + default ENV_IS_IN_SPI_FLASH if INTEL_BRASWELL default ENV_IS_IN_SPI_FLASH if INTEL_BROADWELL default ENV_IS_IN_SPI_FLASH if NORTHBRIDGE_INTEL_IVYBRIDGE default ENV_IS_IN_SPI_FLASH if INTEL_QUARK -- cgit v1.2.3 From aa9c5956c9b921f3745e024d1572fd3dcc283091 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 18 Oct 2017 18:20:55 -0700 Subject: x86: Fix ACPI resume dependency to MRC cache In an S3 resume path, MRC cache is mandatory. Enforce the dependency in the Kconfig. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index c869ae25489..b2ae865c72d 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -664,6 +664,7 @@ endmenu config HAVE_ACPI_RESUME bool "Enable ACPI S3 resume" + select ENABLE_MRC_CACHE help Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping state where all system context is lost except system memory. U-Boot -- cgit v1.2.3 From fb2c53091ff457ce8a0b547f37e7374d10d855ea Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 18 Oct 2017 18:20:56 -0700 Subject: Revert "x86: fsp: Configure SPI opcode registers before SPI is locked down" This reverts commit 1e6ebee667da47fd3a87839a239a7574c66f5659. It's not appropriate to call the Intel SPI driver specific stuff in the FSP codes. We may add a simple DTS property "intel,spi-lock-down" and let the Intel SPI driver call these stuff instead. Signed-off-by: Bin Meng --- arch/x86/Kconfig | 9 --------- arch/x86/lib/fsp/fsp_common.c | 24 ------------------------ 2 files changed, 33 deletions(-) (limited to 'arch') diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index b2ae865c72d..98c56ad7dc7 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -402,15 +402,6 @@ config FSP_BROKEN_HOB do not overwrite the important boot service data which is used by FSP, otherwise the subsequent call to fsp_notify() will fail. -config FSP_LOCKDOWN_SPI - bool - depends on HAVE_FSP - help - Some Intel FSP (like Braswell) does SPI lock-down during the call - to fsp_notify(INIT_PHASE_BOOT). This option should be turned on - for such FSP and U-Boot will configure the SPI opcode registers - before the lock-down. - config ENABLE_MRC_CACHE bool "Enable MRC cache" depends on !EFI && !SYS_COREBOOT diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 1714d13228e..3397bb83eaf 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -19,8 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; -extern void ich_spi_config_opcode(struct udevice *dev); - int checkcpu(void) { return 0; @@ -51,28 +49,6 @@ void board_final_cleanup(void) { u32 status; -#ifdef CONFIG_FSP_LOCKDOWN_SPI - struct udevice *dev; - - /* - * Some Intel FSP (like Braswell) does SPI lock-down during the call - * to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done, - * it's bootloader's responsibility to configure the SPI controller's - * opcode registers properly otherwise SPI controller driver doesn't - * know how to communicate with the SPI flash device. - * - * Note we cannot do such configuration elsewhere (eg: during the SPI - * controller driver's probe() routine), because: - * - * 1). U-Boot SPI controller driver does not set the lock-down bit - * 2). Any SPI transfer will corrupt the contents of these registers - * - * Hence we have to do it right here before SPI lock-down bit is set. - */ - if (!uclass_first_device_err(UCLASS_SPI, &dev)) - ich_spi_config_opcode(dev); -#endif - /* call into FspNotify */ debug("Calling into FSP (notify phase INIT_PHASE_BOOT): "); status = fsp_notify(NULL, INIT_PHASE_BOOT); -- cgit v1.2.3 From 4c9f4c5ee4ac15a285f3ceb25752432990084dc1 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 18 Oct 2017 18:20:58 -0700 Subject: x86: braswell: cherryhill: Update dts for SPI lock down Intel Braswell FSP requires SPI controller settings to be locked down, let's do this in the chrryhill.dts and remove previous Kconfig option. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/cpu/braswell/Kconfig | 4 ---- arch/x86/dts/cherryhill.dts | 1 + 2 files changed, 1 insertion(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/x86/cpu/braswell/Kconfig b/arch/x86/cpu/braswell/Kconfig index 616f2287883..31ac279c568 100644 --- a/arch/x86/cpu/braswell/Kconfig +++ b/arch/x86/cpu/braswell/Kconfig @@ -31,8 +31,4 @@ config FSP_ADDR hex default 0xfff20000 -config FSP_LOCKDOWN_SPI - bool - default y - endif diff --git a/arch/x86/dts/cherryhill.dts b/arch/x86/dts/cherryhill.dts index 840a6699568..41e72f3eb62 100644 --- a/arch/x86/dts/cherryhill.dts +++ b/arch/x86/dts/cherryhill.dts @@ -143,6 +143,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "intel,ich9-spi"; + intel,spi-lock-down; spi-flash@0 { #address-cells = <1>; -- cgit v1.2.3 From dc80d3b2309b7c6f94daa2a2bd843b8febfa0369 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 18 Oct 2017 18:20:59 -0700 Subject: x86: fsp: graphics: Add some notes about the graphics info hob On some platforms (eg: Braswell), the FSP will not produce the graphics info HOB unless you plug some cables to the display interface (eg: HDMI) on the board. Add such notes in the FSP video driver. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/lib/fsp/fsp_graphics.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c index a19b067f8fd..af7127691f1 100644 --- a/arch/x86/lib/fsp/fsp_graphics.c +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -37,6 +37,10 @@ static int save_vesa_mode(struct vesa_mode_info *vesa) /* * If there is no graphics info structure, bail out and keep * running on the serial console. + * + * Note: on some platforms (eg: Braswell), the FSP will not produce + * the graphics info HOB unless you plug some cables to the display + * interface (eg: HDMI) on the board. */ if (!ginfo) { debug("FSP graphics hand-off block not found\n"); -- cgit v1.2.3 From 411898dc87c09d0cd103a4243c8cb4a72b115c51 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 18 Oct 2017 18:21:00 -0700 Subject: x86: acpi: Put sleepstates.asl to the common place The supported sleep states are generic on Intel processors. Move the ASL definition to the common place. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/include/asm/acpi/sleepstates.asl | 15 +++++++++++++++ arch/x86/include/asm/arch-baytrail/acpi/platform.asl | 2 +- arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl | 15 --------------- arch/x86/include/asm/arch-quark/acpi/platform.asl | 2 +- arch/x86/include/asm/arch-quark/acpi/sleepstates.asl | 10 ---------- 5 files changed, 17 insertions(+), 27 deletions(-) create mode 100644 arch/x86/include/asm/acpi/sleepstates.asl delete mode 100644 arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl delete mode 100644 arch/x86/include/asm/arch-quark/acpi/sleepstates.asl (limited to 'arch') diff --git a/arch/x86/include/asm/acpi/sleepstates.asl b/arch/x86/include/asm/acpi/sleepstates.asl new file mode 100644 index 00000000000..56007230843 --- /dev/null +++ b/arch/x86/include/asm/acpi/sleepstates.asl @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2016 Bin Meng + * + * Modified from coreboot src/soc/intel/baytrail/acpi/sleepstates.asl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0}) +#ifdef CONFIG_HAVE_ACPI_RESUME +Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0}) +#endif +Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0}) +Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0}) diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl index a80d2c0e515..cf3de7cde44 100644 --- a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl +++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl @@ -36,4 +36,4 @@ Scope (\_SB) } /* Chipset specific sleep states */ -#include "sleepstates.asl" +#include diff --git a/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl b/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl deleted file mode 100644 index 56007230843..00000000000 --- a/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2016 Bin Meng - * - * Modified from coreboot src/soc/intel/baytrail/acpi/sleepstates.asl - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0}) -#ifdef CONFIG_HAVE_ACPI_RESUME -Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0}) -#endif -Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0}) -Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0}) diff --git a/arch/x86/include/asm/arch-quark/acpi/platform.asl b/arch/x86/include/asm/arch-quark/acpi/platform.asl index 1ecf153c0f9..db59c460e35 100644 --- a/arch/x86/include/asm/arch-quark/acpi/platform.asl +++ b/arch/x86/include/asm/arch-quark/acpi/platform.asl @@ -33,4 +33,4 @@ Scope (\_SB) } /* Chipset specific sleep states */ -#include "sleepstates.asl" +#include diff --git a/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl b/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl deleted file mode 100644 index 63c82fa1235..00000000000 --- a/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (C) 2016, Bin Meng - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0}) -Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0}) -Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0}) -Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0}) -- cgit v1.2.3