From cea0ed2e3f37a36e6243bed8c3491d2281c30287 Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Tue, 28 May 2024 20:49:57 +0800 Subject: riscv: remove cache enablement in start.S Cache could be enabled in harts_early_init board-specific hook, so remove cache enablement in start.S Signed-off-by: Leo Yu-Chi Liang --- arch/riscv/cpu/start.S | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch') diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index a9e19356928..8e58f641f1b 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -210,10 +210,6 @@ wait_for_gd_init: bnez s2, secondary_hart_loop #endif - /* Enable cache */ - jal icache_enable - jal dcache_enable - #ifdef CONFIG_DEBUG_UART jal debug_uart_init #endif -- cgit v1.2.3 From 1d29c718b7ba09807f8060796d9c21772e3c1b52 Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Tue, 28 May 2024 20:57:50 +0800 Subject: andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND Use CSR_UCCTLCOMMAND instead of CSR_MCCTLCOMMAND to do cache flush operation in M-mode and S-mode. Signed-off-by: Leo Yu-Chi Liang --- arch/riscv/cpu/andes/cache.c | 4 +--- arch/riscv/include/asm/arch-andes/csr.h | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/riscv/cpu/andes/cache.c b/arch/riscv/cpu/andes/cache.c index 7d3df8722dd..bb57498d75a 100644 --- a/arch/riscv/cpu/andes/cache.c +++ b/arch/riscv/cpu/andes/cache.c @@ -43,9 +43,7 @@ static void cache_ops(int (*ops)(struct udevice *dev)) void flush_dcache_all(void) { -#if CONFIG_IS_ENABLED(RISCV_MMODE) - csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL); -#endif + csr_write(CSR_UCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL); } void flush_dcache_range(unsigned long start, unsigned long end) diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h index 028fd01c2f3..7d6104a24e5 100644 --- a/arch/riscv/include/asm/arch-andes/csr.h +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -12,7 +12,7 @@ #define CSR_MCACHE_CTL 0x7ca #define CSR_MMISC_CTL 0x7d0 -#define CSR_MCCTLCOMMAND 0x7cc +#define CSR_UCCTLCOMMAND 0x80c /* mcache_ctl register */ -- cgit v1.2.3