From dc11d83a2e4f534242d634f65427e07c6ecf2c6c Mon Sep 17 00:00:00 2001 From: Vikas Manocha Date: Mon, 27 Mar 2017 13:02:45 -0700 Subject: stm32f7: enable instruction & data cache It also enables commands for cache enable/disable/status. Signed-off-by: Vikas Manocha cc: Christophe KERELLO --- arch/arm/mach-stm32/stm32f7/soc.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-stm32/stm32f7/soc.c b/arch/arm/mach-stm32/stm32f7/soc.c index 06af631cc10..6f9704ab788 100644 --- a/arch/arm/mach-stm32/stm32f7/soc.c +++ b/arch/arm/mach-stm32/stm32f7/soc.c @@ -58,6 +58,8 @@ int arch_cpu_init(void) (V7M_MPU_RASR_XN_ENABLE | V7M_MPU_RASR_AP_RW_RW | 0x01 << V7M_MPU_RASR_TEX_SHIFT + | 0x01 << V7M_MPU_RASR_B_SHIFT + | 0x01 << V7M_MPU_RASR_C_SHIFT | V7M_MPU_RASR_SIZE_8MB | V7M_MPU_RASR_EN) , &V7M_MPU->rasr -- cgit v1.2.3