From 9f798766aa85e62eb8fa8c721e148df609b78137 Mon Sep 17 00:00:00 2001 From: Eugene O'Brien Date: Tue, 23 Oct 2007 08:29:10 +0200 Subject: ppc4xx: Fixed offset of refresh rate type for Bamboo on-board DDR SDRAM This patch also adds a note to the fixed DDR setup for Bamboo NAND booting: Note: As found out by Eugene O'Brien , the fixed DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM modules are still plugged in. So it is recommended to remove the DIMM modules while using the NAND booting code with the fixed SDRAM setup! Signed-off-by: Eugene O'Brien Signed-off-by: Stefan Roese --- board/amcc/bamboo/bamboo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board/amcc/bamboo') diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 00c793afd01..c4eace58049 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -67,13 +67,13 @@ const unsigned char cfg_simulate_spd_eeprom[128] = { 0x00, /* Module data width continued: +0 */ 0x04, /* 2.5 Volt */ 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */ + 0x00, /* SDRAM Access from clock */ #ifdef CONFIG_DDR_ECC 0x02, /* ECC ON : 02 OFF : 00 */ #else 0x00, /* ECC ON : 02 OFF : 00 */ #endif - 0x82, /* refresh Rate Type: Normal (15.625us) + Self refresh */ - 0, + 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */ 0, 0, 0x01, /* wcsbc = 1 */ -- cgit v1.2.3